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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
12 *
13 * Configuation settings for the WindRiver PPMC8260 board.
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/*****************************************************************************
38 *
39 * These settings must match the way _your_ board is set up
40 *
41 *****************************************************************************/
42
43/* What is the oscillator's (UX2) frequency in Hz? */
44#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
45
46/*-----------------------------------------------------------------------
47 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
48 *-----------------------------------------------------------------------
49 * What should MODCK_H be? It is dependent on the oscillator
50 * frequency, MODCK[1-3], and desired CPM and core frequencies.
51 * Here are some example values (all frequencies are in MHz):
52 *
53 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
54 * ------- ---------- --- --- ---- ----- ----- -----
55 * 0x2 0x2 33 133 133 Close Open Close
56 * 0x2 0x3 33 133 166 Close Open Open
57 * 0x2 0x4 33 133 200 Open Close Close
58 * 0x2 0x5 33 133 233 Open Close Open
59 * 0x2 0x6 33 133 266 Open Open Close
60 *
61 * 0x5 0x5 66 133 133 Open Close Open
62 * 0x5 0x6 66 133 166 Open Open Close
63 * 0x5 0x7 66 133 200 Open Open Open
64 * 0x6 0x0 66 133 233 Close Close Close
65 * 0x6 0x1 66 133 266 Close Close Open
66 * 0x6 0x2 66 133 300 Close Open Close
67 */
68#define CFG_PPMC_MODCK_H 0x05
69
70/* Define this if you want to boot from 0x00000100. If you don't define
71 * this, you will need to program the bootloader to 0xfff00000, and
72 * get the hardware reset config words at 0xfe000000. The simplest
73 * way to do that is to program the bootloader at both addresses.
74 * It is suggested that you just let U-Boot live at 0x00000000.
75 */
76#define CFG_PPMC_BOOT_LOW 1
77
78/* What should the base address of the main FLASH be and how big is
79 * it (in MBytes)? This must contain TEXT_BASE from board/ppmc8260/config.mk
80 * The main FLASH is whichever is connected to *CS0. U-Boot expects
81 * this to be the SIMM.
82 */
83#define CFG_FLASH0_BASE 0xFE000000
84#define CFG_FLASH0_SIZE 16
85
86/* What should be the base address of the first SDRAM DIMM and how big is
87 * it (in Mbytes)?
88*/
89#define CFG_SDRAM0_BASE 0x00000000
90#define CFG_SDRAM0_SIZE 128
91
92/* What should be the base address of the second SDRAM DIMM and how big is
93 * it (in Mbytes)?
94*/
95#define CFG_SDRAM1_BASE 0x08000000
96#define CFG_SDRAM1_SIZE 128
97
98/* What should be the base address of the on board SDRAM and how big is
99 * it (in Mbytes)?
100*/
101#define CFG_SDRAM2_BASE 0x38000000
102#define CFG_SDRAM2_SIZE 16
103
104/* What should be the base address of the MAILBOX and how big is it
105 * (in Bytes)
106 * The eeprom lives at CFG_MAILBOX_BASE + 0x80000000
107 */
108#define CFG_MAILBOX_BASE 0x32000000
109#define CFG_MAILBOX_SIZE 8192
110
111/* What is the base address of the I/O select lines and how big is it
112 * (In Mbytes)?
113 */
114
115#define CFG_IOSELECT_BASE 0xE0000000
116#define CFG_IOSELECT_SIZE 32
117
118
119/* What should be the base address of the LEDs and switch S0?
120 * If you don't want them enabled, don't define this.
121 */
122#define CFG_LED_BASE 0xF1000000
123
124/*
125 * PPMC8260 with 256 16 MB DIMM:
126 *
127 * 0x0000 0000 Exception Vector code, 8k
128 * :
129 * 0x0000 1FFF
130 * 0x0000 2000 Free for Application Use
131 * :
132 * :
133 *
134 * :
135 * :
136 * 0x0FF5 FF30 Monitor Stack (Growing downward)
137 * Monitor Stack Buffer (0x80)
138 * 0x0FF5 FFB0 Board Info Data
139 * 0x0FF6 0000 Malloc Arena
140 * : CFG_ENV_SECT_SIZE, 256k
141 * : CFG_MALLOC_LEN, 128k
142 * 0x0FFC 0000 RAM Copy of Monitor Code
143 * : CFG_MONITOR_LEN, 256k
144 * 0x0FFF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
145 */
146
147
148/*
149 * select serial console configuration
150 *
151 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
152 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
153 * for SCC).
154 *
155 * if CONFIG_CONS_NONE is defined, then the serial console routines must
156 * defined elsewhere.
157 * The console can be on SMC1 or SMC2
158 */
159#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
160#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
161#undef CONFIG_CONS_NONE /* define if console on neither */
162#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
163
164/*
165 * select ethernet configuration
166 *
167 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
168 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
169 * for FCC)
170 *
171 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500172 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkfe8c2802002-11-03 00:38:21 +0000173 */
174
175#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
176#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
177#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
178#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
179#define CONFIG_MII /* MII PHY management */
180#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
181/*
182 * Port pins used for bit-banged MII communictions (if applicable).
183 */
184#define MDIO_PORT 2 /* Port C */
185#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
186#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
187#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
188
189#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
190 else iop->pdat &= ~0x00400000
191
192#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
193 else iop->pdat &= ~0x00200000
194
195#define MIIDELAY udelay(1)
196
197
198/* Define this to reserve an entire FLASH sector (256 KB) for
199 * environment variables. Otherwise, the environment will be
200 * put in the same sector as U-Boot, and changing variables
201 * will erase U-Boot temporarily
202 */
203#define CFG_ENV_IN_OWN_SECT 1
204
205/* Define to allow the user to overwrite serial and ethaddr */
206#define CONFIG_ENV_OVERWRITE
207
208/* What should the console's baud rate be? */
209#define CONFIG_BAUDRATE 9600
210
211/* Ethernet MAC address */
212
213#define CONFIG_ETHADDR 00:a0:1e:90:2b:00
214
215/* Define this to set the last octet of the ethernet address
216 * from the DS0-DS7 switch and light the leds with the result
217 * The DS0-DS7 switch and the leds are backwards with respect
218 * to each other. DS7 is on the board edge side of both the
219 * led strip and the DS0-DS7 switch.
220 */
221#define CONFIG_MISC_INIT_R
222
223/* Set to a positive value to delay for running BOOTCOMMAND */
224#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
225
226#if 0
227/* Be selective on what keys can delay or stop the autoboot process
228 * To stop use: " "
229 */
230# define CONFIG_AUTOBOOT_KEYED
231# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"
232# define CONFIG_AUTOBOOT_STOP_STR " "
233# undef CONFIG_AUTOBOOT_DELAY_STR
234# define DEBUG_BOOTKEYS 0
235#endif
236
237/* Define a command string that is automatically executed when no character
238 * is read on the console interface withing "Boot Delay" after reset.
239 */
wdenkb79a11c2004-03-25 15:14:43 +0000240#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
241#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
wdenkfe8c2802002-11-03 00:38:21 +0000242
wdenk42dfe7a2004-03-14 22:25:36 +0000243#ifdef CONFIG_BOOT_ROOT_INITRD
wdenkfe8c2802002-11-03 00:38:21 +0000244#define CONFIG_BOOTCOMMAND \
245 "version;" \
246 "echo;" \
247 "bootp;" \
248 "setenv bootargs root=/dev/ram0 rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100249 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000250 "bootm"
251#endif /* CONFIG_BOOT_ROOT_INITRD */
252
wdenk42dfe7a2004-03-14 22:25:36 +0000253#ifdef CONFIG_BOOT_ROOT_NFS
wdenkfe8c2802002-11-03 00:38:21 +0000254#define CONFIG_BOOTCOMMAND \
255 "version;" \
256 "echo;" \
257 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100258 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
259 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000260 "bootm"
261#endif /* CONFIG_BOOT_ROOT_NFS */
262
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500263
264/*
265 * BOOTP options
wdenkfe8c2802002-11-03 00:38:21 +0000266 */
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500267#define CONFIG_BOOTP_SUBNETMASK
268#define CONFIG_BOOTP_GATEWAY
269#define CONFIG_BOOTP_HOSTNAME
270#define CONFIG_BOOTP_BOOTPATH
271#define CONFIG_BOOTP_BOOTFILESIZE
272#define CONFIG_BOOTP_DNS
273
wdenkfe8c2802002-11-03 00:38:21 +0000274
275/* undef this to save memory */
276#define CFG_LONGHELP
277
278/* Monitor Command Prompt */
279#define CFG_PROMPT "=> "
280
Jon Loeliger26a34562007-07-04 22:33:17 -0500281
282/*
283 * Command line configuration.
284 */
285#include <config_cmd_default.h>
286
287#define CONFIG_CMD_ELF
288#define CONFIG_CMD_ASKENV
289#define CONFIG_CMD_REGINFO
290#define CONFIG_CMD_MEMTEST
291#define CONFIG_CMD_MII
292#define CONFIG_CMD_IMMAP
293
294#undef CONFIG_CMD_KGDB
wdenkfe8c2802002-11-03 00:38:21 +0000295
296
297/* Where do the internal registers live? */
298#define CFG_IMMR 0xf0000000
299
300/*****************************************************************************
301 *
302 * You should not have to modify any of the following settings
303 *
304 *****************************************************************************/
305
306#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
307#define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500308#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkfe8c2802002-11-03 00:38:21 +0000309
wdenkfe8c2802002-11-03 00:38:21 +0000310/*
311 * Miscellaneous configurable options
312 */
Jon Loeliger26a34562007-07-04 22:33:17 -0500313#if defined(CONFIG_CMD_KGDB)
wdenkfe8c2802002-11-03 00:38:21 +0000314# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
315#else
316# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
317#endif
318
319/* Print Buffer Size */
320#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
321
322#define CFG_MAXARGS 32 /* max number of command args */
323
324#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
325
326#define CFG_LOAD_ADDR 0x140000 /* default load address */
327#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
328
329#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
330 /* the exception vector table */
331 /* to the end of the DRAM */
332 /* less monitor and malloc area */
333#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
334#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
335 + CFG_MALLOC_LEN \
336 + CFG_ENV_SECT_SIZE \
337 + CFG_STACK_USAGE )
338
339#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
340 - CFG_MEM_END_USAGE )
341
342/* valid baudrates */
343#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
344
345/*
346 * Low Level Configuration Settings
347 * (address mappings, register initial values, etc.)
348 * You should know what you are doing if you make changes here.
349 */
350
351#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
352/*
353 * Attention: This is board specific
354 * - RX clk is CLK11
355 * - TX clk is CLK12
356 */
357#define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 |\
358 CMXSCR_TS1CS_CLK12)
359
360#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
361/*
362 * Attention: this is board-specific
363 * - Rx-CLK is CLK13
364 * - Tx-CLK is CLK14
365 * - Select bus for bd/buffers (see 28-13)
366 * - Enable Full Duplex in FSMR
367 */
368#define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
369#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
370#define CFG_CPMFCR_RAMTYPE 0
371#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
372#endif /* CONFIG_ETHER_INDEX */
373
374#define CFG_FLASH_BASE CFG_FLASH0_BASE
375#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
376#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
377#define CFG_SDRAM_SIZE (CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE)
378
379/*-----------------------------------------------------------------------
380 * Hard Reset Configuration Words
381 */
382#if defined(CFG_PPMC_BOOT_LOW)
383# define CFG_PPMC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
384#else
385# define CFG_PPMC_HRCW_BOOT_FLAGS (0)
386#endif /* defined(CFG_PPMC_BOOT_LOW) */
387
388/* get the HRCW ISB field from CFG_IMMR */
389#define CFG_PPMC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
390 ((CFG_IMMR & 0x01000000) >> 7) | \
391 ((CFG_IMMR & 0x00100000) >> 4) )
392
393#define CFG_HRCW_MASTER ( HRCW_EBM | \
394 HRCW_BPS11 | \
395 HRCW_L2CPC10 | \
396 HRCW_DPPC00 | \
397 CFG_PPMC_HRCW_IMMR | \
398 HRCW_MMR00 | \
399 HRCW_LBPC00 | \
400 HRCW_APPC10 | \
401 HRCW_CS10PC00 | \
402 (CFG_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
403 CFG_PPMC_HRCW_BOOT_FLAGS )
404
405/* no slaves */
406#define CFG_HRCW_SLAVE1 0
407#define CFG_HRCW_SLAVE2 0
408#define CFG_HRCW_SLAVE3 0
409#define CFG_HRCW_SLAVE4 0
410#define CFG_HRCW_SLAVE5 0
411#define CFG_HRCW_SLAVE6 0
412#define CFG_HRCW_SLAVE7 0
413
414/*-----------------------------------------------------------------------
415 * Definitions for initial stack pointer and data area (in DPRAM)
416 */
417#define CFG_INIT_RAM_ADDR CFG_IMMR
418#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
419#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
420#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
421#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
422
423/*-----------------------------------------------------------------------
424 * Start addresses for the final memory configuration
425 * (Set up by the startup code)
426 * Please note that CFG_SDRAM_BASE _must_ start at 0
427 * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
428 */
429#define CFG_MONITOR_BASE CFG_FLASH0_BASE
430
431#ifndef CFG_MONITOR_BASE
432#define CFG_MONITOR_BASE 0x0ff80000
433#endif
434
435#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
436# define CFG_RAMBOOT
437#endif
438
439#define CFG_MONITOR_LEN (256 << 10) /* Reserve 374 kB for Monitor */
440#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
441
442/*
443 * For booting Linux, the board info and command line data
444 * have to be in the first 8 MB of memory, since this is
445 * the maximum mapped by the Linux kernel during initialization.
446 */
447#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
448
449/*-----------------------------------------------------------------------
450 * FLASH and environment organization
451 */
452
453#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
wdenkbf9e3b32004-02-12 00:47:09 +0000454#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
wdenkfe8c2802002-11-03 00:38:21 +0000455#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
456#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
457#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
458#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
459#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
460
461
462#ifndef CFG_RAMBOOT
463
464# define CFG_ENV_IS_IN_FLASH 1
465# ifdef CFG_ENV_IN_OWN_SECT
466# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
467# define CFG_ENV_SECT_SIZE 0x40000
468# else
469# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
470# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
471# define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
472# endif /* CFG_ENV_IN_OWN_SECT */
473
474#else
475# define CFG_ENV_IS_IN_FLASH 1
476# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000)
477#define CFG_ENV_SIZE 0x1000
478# define CFG_ENV_SECT_SIZE 0x40000
479#endif /* CFG_RAMBOOT */
480
481/*-----------------------------------------------------------------------
482 * Cache Configuration
483 */
484#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
485
Jon Loeliger26a34562007-07-04 22:33:17 -0500486#if defined(CONFIG_CMD_KGDB)
wdenkfe8c2802002-11-03 00:38:21 +0000487# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
488#endif
489
490/*-----------------------------------------------------------------------
491 * HIDx - Hardware Implementation-dependent Registers 2-11
492 *-----------------------------------------------------------------------
493 * HID0 also contains cache control - initially enable both caches and
494 * invalidate contents, then the final state leaves only the instruction
495 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
496 * but Soft reset does not.
497 *
498 * HID1 has only read-only information - nothing to set.
499 */
500#define CFG_HID0_INIT (HID0_ICE |\
501 HID0_DCE |\
502 HID0_ICFI |\
503 HID0_DCI |\
504 HID0_IFEM |\
505 HID0_ABE)
506
507#define CFG_HID0_FINAL (HID0_ICE |\
508 HID0_IFEM |\
509 HID0_ABE |\
510 HID0_EMCP)
511#define CFG_HID2 0
512
513/*-----------------------------------------------------------------------
514 * RMR - Reset Mode Register
515 *-----------------------------------------------------------------------
516 */
517#define CFG_RMR 0
518
519/*-----------------------------------------------------------------------
520 * BCR - Bus Configuration 4-25
521 *-----------------------------------------------------------------------
522 */
523#define CFG_BCR (BCR_EBM |\
524 0x30000000)
525
526/*-----------------------------------------------------------------------
527 * SIUMCR - SIU Module Configuration 4-31
528 * Ref Section 4.3.2.6 page 4-31
529 *-----------------------------------------------------------------------
530 */
531
532#define CFG_SIUMCR (SIUMCR_ESE |\
533 SIUMCR_DPPC00 |\
534 SIUMCR_L2CPC10 |\
535 SIUMCR_LBPC00 |\
536 SIUMCR_APPC10 |\
537 SIUMCR_CS10PC00 |\
538 SIUMCR_BCTLC00 |\
539 SIUMCR_MMR00)
540
541
542/*-----------------------------------------------------------------------
543 * SYPCR - System Protection Control 11-9
544 * SYPCR can only be written once after reset!
545 *-----------------------------------------------------------------------
546 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
547 */
548#define CFG_SYPCR (SYPCR_SWTC |\
549 SYPCR_BMT |\
550 SYPCR_PBME |\
551 SYPCR_LBME |\
552 SYPCR_SWRI |\
553 SYPCR_SWP)
554
555/*-----------------------------------------------------------------------
556 * TMCNTSC - Time Counter Status and Control 4-40
557 *-----------------------------------------------------------------------
558 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
559 * and enable Time Counter
560 */
561#define CFG_TMCNTSC (TMCNTSC_SEC |\
562 TMCNTSC_ALR |\
563 TMCNTSC_TCF |\
564 TMCNTSC_TCE)
565
566/*-----------------------------------------------------------------------
567 * PISCR - Periodic Interrupt Status and Control 4-42
568 *-----------------------------------------------------------------------
569 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
570 * Periodic timer
571 */
572#define CFG_PISCR (PISCR_PS |\
573 PISCR_PTF |\
574 PISCR_PTE)
575
576/*-----------------------------------------------------------------------
577 * SCCR - System Clock Control 9-8
578 *-----------------------------------------------------------------------
579 */
580#define CFG_SCCR 0
581
582/*-----------------------------------------------------------------------
583 * RCCR - RISC Controller Configuration 13-7
584 *-----------------------------------------------------------------------
585 */
586#define CFG_RCCR 0
587
588/*
589 * Initialize Memory Controller:
590 *
591 * Bank Bus Machine PortSz Device
592 * ---- --- ------- ------ ------
593 * 0 60x GPCM 32 bit FLASH (SIMM - 32MB) *
594 * 1 unused
595 * 2 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
596 * 3 60x SDRAM 64 bit SDRAM (DIMM - 128MB)
597 * 4 Local SDRAM 32 bit SDRAM (on board - 16MB)
598 * 5 60x GPCM 8 bit Mailbox/EEPROM (8KB)
599 * 6 60x GPCM 8 bit FLASH (on board - 2MB) *
600 * 7 60x GPCM 8 bit LEDs, switches
601 *
602 * (*) This configuration requires the PPMC8260 be configured
603 * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
604 * the on board FLASH. In other words, JP24 should have
605 * pins 1 and 2 jumpered and pins 3 and 4 jumpered.
606 *
607 */
608
609/*-----------------------------------------------------------------------
610 * BR0,BR1 - Base Register
611 * Ref: Section 10.3.1 on page 10-14
612 * OR0,OR1 - Option Register
613 * Ref: Section 10.3.2 on page 10-18
614 *-----------------------------------------------------------------------
615 */
616
617/* Bank 0,1 - FLASH SIMM
618 *
619 * This expects the FLASH SIMM to be connected to *CS0
620 * It consists of 4 AM29F080B parts.
621 *
622 * Note: For the 4 MB SIMM, *CS1 is unused.
623 */
624
625/* BR0 is configured as follows:
626 *
627 * - Base address of 0xFE000000
628 * - 32 bit port size
629 * - Data errors checking is disabled
630 * - Read and write access
631 * - GPCM 60x bus
632 * - Access are handled by the memory controller according to MSEL
633 * - Not used for atomic operations
634 * - No data pipelining is done
635 * - Valid
636 */
637#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
638 BRx_PS_32 |\
639 BRx_MS_GPCM_P |\
640 BRx_V)
641
642/* OR0 is configured as follows:
643 *
644 * - 32 MB
645 * - *BCTL0 is asserted upon access to the current memory bank
646 * - *CW / *WE are negated a quarter of a clock earlier
647 * - *CS is output at the same time as the address lines
648 * - Uses a clock cycle length of 5
649 * - *PSDVAL is generated internally by the memory controller
650 * unless *GTA is asserted earlier externally.
651 * - Relaxed timing is generated by the GPCM for accesses
652 * initiated to this memory region.
653 * - One idle clock is inserted between a read access from the
654 * current bank and the next access.
655 */
656#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
657 ORxG_CSNT |\
658 ORxG_ACS_DIV1 |\
659 ORxG_SCY_5_CLK |\
660 ORxG_TRLX |\
661 ORxG_EHTR)
662
663/*-----------------------------------------------------------------------
664 * BR2,BR3 - Base Register
665 * Ref: Section 10.3.1 on page 10-14
666 * OR2,OR3 - Option Register
667 * Ref: Section 10.3.2 on page 10-16
668 *-----------------------------------------------------------------------
669 */
670
671/*
672 * Bank 2,3 - 128 MB SDRAM DIMM
673 */
674
675/* With a 128 MB DIMM, the BR2 is configured as follows:
676 *
677 * - Base address of 0x00000000/0x08000000
678 * - 64 bit port size (60x bus only)
679 * - Data errors checking is disabled
680 * - Read and write access
681 * - SDRAM 60x bus
682 * - Access are handled by the memory controller according to MSEL
683 * - Not used for atomic operations
684 * - No data pipelining is done
685 * - Valid
686 */
687#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
688 BRx_PS_64 |\
689 BRx_MS_SDRAM_P |\
690 BRx_V)
691
692#define CFG_BR3_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
693 BRx_PS_64 |\
694 BRx_MS_SDRAM_P |\
695 BRx_V)
696
697/* With a 128 MB DIMM, the OR2 is configured as follows:
698 *
699 * - 128 MB
700 * - 4 internal banks per device
701 * - Row start address bit is A8 with PSDMR[PBI] = 0
702 * - 13 row address lines
703 * - Back-to-back page mode
704 * - Internal bank interleaving within save device enabled
705 */
706
707#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
708 ORxS_BPD_4 |\
709 ORxS_ROWST_PBI0_A7 |\
710 ORxS_NUMR_13)
711
712#define CFG_OR3_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE) |\
713 ORxS_BPD_4 |\
714 ORxS_ROWST_PBI0_A7 |\
715 ORxS_NUMR_13)
716
717
718/*-----------------------------------------------------------------------
719 * PSDMR - 60x Bus SDRAM Mode Register
720 * Ref: Section 10.3.3 on page 10-21
721 *-----------------------------------------------------------------------
722 */
723
724/* With a 128 MB DIMM, the PSDMR is configured as follows:
725 *
726 * - Page Based Interleaving,
727 * - Refresh Enable,
728 * - Normal Operation
729 * - Address Multiplexing where A5 is output on A14 pin
730 * (A6 on A15, and so on),
731 * - use address pins A13-A15 as bank select,
732 * - A9 is output on SDA10 during an ACTIVATE command,
733 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
734 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
735 * is 3 clocks,
736 * - earliest timing for READ/WRITE command after ACTIVATE command is
737 * 2 clocks,
738 * - earliest timing for PRECHARGE after last data was read is 1 clock,
739 * - earliest timing for PRECHARGE after last data was written is 1 clock,
740 * - External Address Multiplexing enabled
741 * - CAS Latency is 2.
742 */
743#define CFG_PSDMR (PSDMR_RFEN |\
744 PSDMR_SDAM_A14_IS_A5 |\
745 PSDMR_BSMA_A13_A15 |\
746 PSDMR_SDA10_PBI0_A9 |\
747 PSDMR_RFRC_7_CLK |\
748 PSDMR_PRETOACT_3W |\
749 PSDMR_ACTTORW_2W |\
750 PSDMR_LDOTOPRE_1C |\
751 PSDMR_WRC_1C |\
752 PSDMR_EAMUX |\
753 PSDMR_CL_2)
754
755
756#define CFG_PSRT 0x0e
757#define CFG_MPTPR MPTPR_PTP_DIV32
758
759
760/*-----------------------------------------------------------------------
761 * BR4 - Base Register
762 * Ref: Section 10.3.1 on page 10-14
763 * OR4 - Option Register
764 * Ref: Section 10.3.2 on page 10-16
765 *-----------------------------------------------------------------------
766 */
767
768/*
769 * Bank 4 - On board SDRAM
770 *
771 */
772/* With 16 MB of onboard SDRAM BR4 is configured as follows
773 *
774 * - Base address 0x38000000
775 * - 32 bit port size
776 * - Data error checking disabled
777 * - Read/Write access
778 * - SDRAM local bus
779 * - Not used for atomic operations
780 * - No data pipelining is done
781 * - Valid
782 *
783 */
784
785#define CFG_BR4_PRELIM ((CFG_SDRAM2_BASE & BRx_BA_MSK) |\
786 BRx_PS_32 |\
787 BRx_DECC_NONE |\
788 BRx_MS_SDRAM_L |\
789 BRx_V)
790
791/*
792 * With 16MB SDRAM, OR4 is configured as follows
793 * - 4 internal banks per device
794 * - Row start address bit is A10 with LSDMR[PBI] = 0
795 * - 12 row address lines
796 * - Back-to-back page mode
797 * - Internal bank interleaving within save device enabled
798 */
799
800#define CFG_OR4_PRELIM (MEG_TO_AM(CFG_SDRAM2_SIZE) |\
801 ORxS_BPD_4 |\
802 ORxS_ROWST_PBI0_A10 |\
803 ORxS_NUMR_12)
804
805
806/*-----------------------------------------------------------------------
807 * LSDMR - Local Bus SDRAM Mode Register
808 * Ref: Section 10.3.4 on page 10-24
809 *-----------------------------------------------------------------------
810 */
811
812/* With a 16 MB onboard SDRAM, the LSDMR is configured as follows:
813 *
814 * - Page Based Interleaving,
815 * - Refresh Enable,
816 * - Normal Operation
817 * - Address Multiplexing where A5 is output on A13 pin
818 * (A6 on A15, and so on),
819 * - use address pins A15-A17 as bank select,
820 * - A11 is output on SDA10 during an ACTIVATE command,
821 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
822 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
823 * is 2 clocks,
824 * - earliest timing for READ/WRITE command after ACTIVATE command is
825 * 2 clocks,
826 * - SDRAM burst length is 8
827 * - earliest timing for PRECHARGE after last data was read is 1 clock,
828 * - earliest timing for PRECHARGE after last data was written is 1 clock,
829 * - External Address Multiplexing disabled
830 * - CAS Latency is 2.
831 */
832#define CFG_LSDMR (PSDMR_RFEN |\
833 PSDMR_SDAM_A13_IS_A5 |\
834 PSDMR_BSMA_A15_A17 |\
835 PSDMR_SDA10_PBI0_A11 |\
836 PSDMR_RFRC_7_CLK |\
837 PSDMR_PRETOACT_2W |\
838 PSDMR_ACTTORW_2W |\
839 PSDMR_BL |\
840 PSDMR_LDOTOPRE_1C |\
841 PSDMR_WRC_1C |\
842 PSDMR_CL_2)
843
844#define CFG_LSRT 0x0e
845
846/*-----------------------------------------------------------------------
847 * BR5 - Base Register
848 * Ref: Section 10.3.1 on page 10-14
849 * OR5 - Option Register
850 * Ref: Section 10.3.2 on page 10-16
851 *-----------------------------------------------------------------------
852 */
853
854/*
855 * Bank 5 EEProm and Mailbox
856 *
857 * The EEPROM and mailbox live on the same chip select.
858 * the eeprom is selected if the MSb of the address is set and the mailbox is
859 * selected if the MSb of the address is clear.
860 *
861 */
862
863/* BR5 is configured as follows:
864 *
865 * - Base address of 0x32000000/0xF2000000
866 * - 8 bit
867 * - Data error checking disabled
868 * - Read/Write access
869 * - GPCM 60x Bus
870 * - SDRAM local bus
871 * - No data pipelining is done
872 * - Valid
873 */
874
875#define CFG_BR5_PRELIM ((CFG_MAILBOX_BASE & BRx_BA_MSK) |\
876 BRx_PS_8 |\
877 BRx_DECC_NONE |\
878 BRx_MS_GPCM_P |\
879 BRx_V)
880/* OR5 is configured as follows
881 * - buffer control enabled
882 * - chip select negated normally
883 * - CS output 1/2 clock after address
884 * - 15 wait states
885 * - *PSDVAL is generated internally by the memory controller
886 * unless *GTA is asserted earlier externally.
887 * - Relaxed timing is generated by the GPCM for accesses
888 * initiated to this memory region.
889 * - One idle clock is inserted between a read access from the
890 * current bank and the next access.
891 */
892
893#define CFG_OR5_PRELIM ((P2SZ_TO_AM(CFG_MAILBOX_SIZE) & ~0x80000000) |\
894 ORxG_ACS_DIV2 |\
895 ORxG_SCY_15_CLK |\
896 ORxG_TRLX |\
897 ORxG_EHTR)
898
899/*-----------------------------------------------------------------------
900 * BR6 - Base Register
901 * Ref: Section 10.3.1 on page 10-14
902 * OR6 - Option Register
903 * Ref: Section 10.3.2 on page 10-18
904 *-----------------------------------------------------------------------
905 */
906
907/* Bank 6 - I/O select
908 *
909 */
910
911/* BR6 is configured as follows:
912 *
913 * - Base address of 0xE0000000
914 * - 16 bit port size
915 * - Data errors checking is disabled
916 * - Read and write access
917 * - GPCM 60x bus
918 * - Access are handled by the memory controller according to MSEL
919 * - Not used for atomic operations
920 * - No data pipelining is done
921 * - Valid
922 */
923#define CFG_BR6_PRELIM ((CFG_IOSELECT_BASE & BRx_BA_MSK) |\
924 BRx_PS_16 |\
925 BRx_MS_GPCM_P |\
926 BRx_V)
927
928/* OR6 is configured as follows
929 * - buffer control enabled
930 * - chip select negated normally
931 * - CS output 1/2 clock after address
932 * - 15 wait states
933 * - *PSDVAL is generated internally by the memory controller
934 * unless *GTA is asserted earlier externally.
935 * - Relaxed timing is generated by the GPCM for accesses
936 * initiated to this memory region.
937 * - One idle clock is inserted between a read access from the
938 * current bank and the next access.
939 */
940
941#define CFG_OR6_PRELIM (MEG_TO_AM(CFG_IOSELECT_SIZE) |\
942 ORxG_ACS_DIV2 |\
943 ORxG_SCY_15_CLK |\
944 ORxG_TRLX |\
945 ORxG_EHTR)
946
947
948/*-----------------------------------------------------------------------
949 * BR7 - Base Register
950 * Ref: Section 10.3.1 on page 10-14
951 * OR7 - Option Register
952 * Ref: Section 10.3.2 on page 10-18
953 *-----------------------------------------------------------------------
954 */
955
956/* Bank 7 - LEDs and switches
957 *
958 * LEDs are at 0x00001 (write only)
959 * switches are at 0x00001 (read only)
960 */
961#ifdef CFG_LED_BASE
962
963/* BR7 is configured as follows:
964 *
965 * - Base address of 0xA0000000
966 * - 8 bit port size
967 * - Data errors checking is disabled
968 * - Read and write access
969 * - GPCM 60x bus
970 * - Access are handled by the memory controller according to MSEL
971 * - Not used for atomic operations
972 * - No data pipelining is done
973 * - Valid
974 */
975#define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\
976 BRx_PS_8 |\
977 BRx_DECC_NONE |\
978 BRx_MS_GPCM_P |\
979 BRx_V)
980
981/* OR7 is configured as follows:
982 *
983 * - 1 byte
984 * - *BCTL0 is asserted upon access to the current memory bank
985 * - *CW / *WE are negated a quarter of a clock earlier
986 * - *CS is output at the same time as the address lines
987 * - Uses a clock cycle length of 15
988 * - *PSDVAL is generated internally by the memory controller
989 * unless *GTA is asserted earlier externally.
990 * - Relaxed timing is generated by the GPCM for accesses
991 * initiated to this memory region.
992 * - One idle clock is inserted between a read access from the
993 * current bank and the next access.
994 */
995#define CFG_OR7_PRELIM (ORxG_AM_MSK |\
996 ORxG_CSNT |\
997 ORxG_ACS_DIV1 |\
998 ORxG_SCY_15_CLK |\
999 ORxG_TRLX |\
1000 ORxG_EHTR)
1001#endif /* CFG_LED_BASE */
1002
1003/*
1004 * Internal Definitions
1005 *
1006 * Boot Flags
1007 */
1008#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
1009#define BOOTFLAG_WARM 0x02 /* Software reboot */
1010
1011#endif /* __CONFIG_H */