blob: 53a791ea292ef546ca43785ff1fb386bdde03ad7 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sekhar Nori8ed58852010-01-27 11:10:40 -05002/*
3 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Driver for SPI controller on DaVinci. Based on atmel_spi.c
6 * by Atmel Corporation
7 *
8 * Copyright (C) 2007 Atmel Corporation
Sekhar Nori8ed58852010-01-27 11:10:40 -05009 */
Jagan Tekiff6e31d2015-06-27 00:51:29 +053010
Sekhar Nori8ed58852010-01-27 11:10:40 -050011#include <common.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
Sekhar Nori8ed58852010-01-27 11:10:40 -050013#include <spi.h>
14#include <malloc.h>
15#include <asm/io.h>
16#include <asm/arch/hardware.h>
Vignesh R192bb752016-07-06 09:58:56 +053017#include <dm.h>
Jagan Tekiba3c22b2018-09-03 23:00:23 +053018#include <dm/platform_data/spi_davinci.h>
Simon Glasscd93d622020-05-10 11:40:13 -060019#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060020#include <linux/delay.h>
Jagan Tekie6d2fbf2015-06-27 00:51:28 +053021
Jagan Tekie6d2fbf2015-06-27 00:51:28 +053022/* SPIGCR0 */
23#define SPIGCR0_SPIENA_MASK 0x1
24#define SPIGCR0_SPIRST_MASK 0x0
25
26/* SPIGCR0 */
27#define SPIGCR1_CLKMOD_MASK BIT(1)
28#define SPIGCR1_MASTER_MASK BIT(0)
29#define SPIGCR1_SPIENA_MASK BIT(24)
30
31/* SPIPC0 */
32#define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */
33#define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */
34#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
35#define SPIPC0_EN0FUN_MASK BIT(0)
36
37/* SPIFMT0 */
38#define SPIFMT_SHIFTDIR_SHIFT 20
39#define SPIFMT_POLARITY_SHIFT 17
40#define SPIFMT_PHASE_SHIFT 16
41#define SPIFMT_PRESCALE_SHIFT 8
42
43/* SPIDAT1 */
44#define SPIDAT1_CSHOLD_SHIFT 28
45#define SPIDAT1_CSNR_SHIFT 16
46
47/* SPIDELAY */
48#define SPI_C2TDELAY_SHIFT 24
49#define SPI_T2CDELAY_SHIFT 16
50
51/* SPIBUF */
52#define SPIBUF_RXEMPTY_MASK BIT(31)
53#define SPIBUF_TXFULL_MASK BIT(29)
54
55/* SPIDEF */
56#define SPIDEF_CSDEF0_MASK BIT(0)
57
Vignesh R192bb752016-07-06 09:58:56 +053058DECLARE_GLOBAL_DATA_PTR;
Jagan Tekie6d2fbf2015-06-27 00:51:28 +053059
Jagan Tekiff6e31d2015-06-27 00:51:29 +053060/* davinci spi register set */
61struct davinci_spi_regs {
62 dv_reg gcr0; /* 0x00 */
63 dv_reg gcr1; /* 0x04 */
64 dv_reg int0; /* 0x08 */
65 dv_reg lvl; /* 0x0c */
66 dv_reg flg; /* 0x10 */
67 dv_reg pc0; /* 0x14 */
68 dv_reg pc1; /* 0x18 */
69 dv_reg pc2; /* 0x1c */
70 dv_reg pc3; /* 0x20 */
71 dv_reg pc4; /* 0x24 */
72 dv_reg pc5; /* 0x28 */
73 dv_reg rsvd[3];
74 dv_reg dat0; /* 0x38 */
75 dv_reg dat1; /* 0x3c */
76 dv_reg buf; /* 0x40 */
77 dv_reg emu; /* 0x44 */
78 dv_reg delay; /* 0x48 */
79 dv_reg def; /* 0x4c */
80 dv_reg fmt0; /* 0x50 */
81 dv_reg fmt1; /* 0x54 */
82 dv_reg fmt2; /* 0x58 */
83 dv_reg fmt3; /* 0x5c */
84 dv_reg intvec0; /* 0x60 */
85 dv_reg intvec1; /* 0x64 */
86};
87
88/* davinci spi slave */
Jagan Tekie6d2fbf2015-06-27 00:51:28 +053089struct davinci_spi_slave {
Jagan Tekie6d2fbf2015-06-27 00:51:28 +053090 struct davinci_spi_regs *regs;
Vignesh R192bb752016-07-06 09:58:56 +053091 unsigned int freq; /* current SPI bus frequency */
92 unsigned int mode; /* current SPI mode used */
93 u8 num_cs; /* total no. of CS available */
94 u8 cur_cs; /* CS of current slave */
95 bool half_duplex; /* true, if master is half-duplex only */
Jagan Tekie6d2fbf2015-06-27 00:51:28 +053096};
97
Nick Thompson77436d62010-06-22 11:06:01 -040098/*
99 * This functions needs to act like a macro to avoid pipeline reloads in the
100 * loops below. Use always_inline. This gains us about 160KiB/s and the bloat
101 * appears to be zero bytes (da830).
102 */
103__attribute__((always_inline))
104static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data)
105{
106 u32 buf_reg_val;
107
108 /* send out data */
109 writel(data, &ds->regs->dat1);
110
111 /* wait for the data to clock in/out */
112 while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK)
113 ;
114
115 return buf_reg_val;
116}
117
Vignesh R192bb752016-07-06 09:58:56 +0530118static int davinci_spi_read(struct davinci_spi_slave *ds, unsigned int len,
Nick Thompson77436d62010-06-22 11:06:01 -0400119 u8 *rxp, unsigned long flags)
120{
Nick Thompson77436d62010-06-22 11:06:01 -0400121 unsigned int data1_reg_val;
122
123 /* enable CS hold, CS[n] and clear the data bits */
124 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
Vignesh R192bb752016-07-06 09:58:56 +0530125 (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
Nick Thompson77436d62010-06-22 11:06:01 -0400126
127 /* wait till TXFULL is deasserted */
128 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
129 ;
130
131 /* preload the TX buffer to avoid clock starvation */
132 writel(data1_reg_val, &ds->regs->dat1);
133
134 /* keep reading 1 byte until only 1 byte left */
135 while ((len--) > 1)
136 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val);
137
138 /* clear CS hold when we reach the end */
139 if (flags & SPI_XFER_END)
140 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
141
142 /* read the last byte */
143 *rxp = davinci_spi_xfer_data(ds, data1_reg_val);
144
145 return 0;
146}
147
Vignesh R192bb752016-07-06 09:58:56 +0530148static int davinci_spi_write(struct davinci_spi_slave *ds, unsigned int len,
Nick Thompsondce65382010-07-05 20:00:40 -0400149 const u8 *txp, unsigned long flags)
Nick Thompson77436d62010-06-22 11:06:01 -0400150{
Nick Thompson77436d62010-06-22 11:06:01 -0400151 unsigned int data1_reg_val;
152
153 /* enable CS hold and clear the data bits */
154 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
Vignesh R192bb752016-07-06 09:58:56 +0530155 (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
Nick Thompson77436d62010-06-22 11:06:01 -0400156
157 /* wait till TXFULL is deasserted */
158 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
159 ;
160
161 /* preload the TX buffer to avoid clock starvation */
162 if (len > 2) {
163 writel(data1_reg_val | *txp++, &ds->regs->dat1);
164 len--;
165 }
166
167 /* keep writing 1 byte until only 1 byte left */
168 while ((len--) > 1)
169 davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
170
171 /* clear CS hold when we reach the end */
172 if (flags & SPI_XFER_END)
173 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
174
175 /* write the last byte */
176 davinci_spi_xfer_data(ds, data1_reg_val | *txp);
177
178 return 0;
179}
180
Vignesh R192bb752016-07-06 09:58:56 +0530181static int davinci_spi_read_write(struct davinci_spi_slave *ds, unsigned
182 int len, u8 *rxp, const u8 *txp,
183 unsigned long flags)
Nick Thompson77436d62010-06-22 11:06:01 -0400184{
Nick Thompson77436d62010-06-22 11:06:01 -0400185 unsigned int data1_reg_val;
186
187 /* enable CS hold and clear the data bits */
188 data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
Vignesh R192bb752016-07-06 09:58:56 +0530189 (ds->cur_cs << SPIDAT1_CSNR_SHIFT));
Nick Thompson77436d62010-06-22 11:06:01 -0400190
191 /* wait till TXFULL is deasserted */
192 while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
193 ;
194
195 /* keep reading and writing 1 byte until only 1 byte left */
196 while ((len--) > 1)
197 *rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
198
199 /* clear CS hold when we reach the end */
200 if (flags & SPI_XFER_END)
201 data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
202
203 /* read and write the last byte */
204 *rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp);
205
206 return 0;
207}
Vignesh R192bb752016-07-06 09:58:56 +0530208
209
210static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs)
211{
212 unsigned int mode = 0, scalar;
213
214 /* Enable the SPI hardware */
215 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
216 udelay(1000);
217 writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
218
219 /* Set master mode, powered up and not activated */
220 writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
221
222 /* CS, CLK, SIMO and SOMI are functional pins */
223 writel(((1 << cs) | SPIPC0_CLKFUN_MASK |
224 SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
225
226 /* setup format */
227 scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
228
229 /*
230 * Use following format:
231 * character length = 8,
232 * MSB shifted out first
233 */
234 if (ds->mode & SPI_CPOL)
235 mode |= SPI_CPOL;
236 if (!(ds->mode & SPI_CPHA))
237 mode |= SPI_CPHA;
238 writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
239 (mode << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
240
241 /*
242 * Including a minor delay. No science here. Should be good even with
243 * no delay
244 */
245 writel((50 << SPI_C2TDELAY_SHIFT) |
246 (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
247
248 /* default chip select register */
249 writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
250
251 /* no interrupts */
252 writel(0, &ds->regs->int0);
253 writel(0, &ds->regs->lvl);
254
255 /* enable SPI */
256 writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
257
258 return 0;
259}
260
261static int __davinci_spi_release_bus(struct davinci_spi_slave *ds)
262{
263 /* Disable the SPI hardware */
264 writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
265
266 return 0;
267}
268
269static int __davinci_spi_xfer(struct davinci_spi_slave *ds,
270 unsigned int bitlen, const void *dout, void *din,
271 unsigned long flags)
272{
273 unsigned int len;
274
275 if (bitlen == 0)
276 /* Finish any previously submitted transfers */
277 goto out;
278
279 /*
280 * It's not clear how non-8-bit-aligned transfers are supposed to be
281 * represented as a stream of bytes...this is a limitation of
282 * the current SPI interface - here we terminate on receiving such a
283 * transfer request.
284 */
285 if (bitlen % 8) {
286 /* Errors always terminate an ongoing transfer */
287 flags |= SPI_XFER_END;
288 goto out;
289 }
290
291 len = bitlen / 8;
292
293 if (!dout)
294 return davinci_spi_read(ds, len, din, flags);
295 if (!din)
296 return davinci_spi_write(ds, len, dout, flags);
297 if (!ds->half_duplex)
298 return davinci_spi_read_write(ds, len, din, dout, flags);
299
300 printf("SPI full duplex not supported\n");
301 flags |= SPI_XFER_END;
302
303out:
304 if (flags & SPI_XFER_END) {
305 u8 dummy = 0;
306 davinci_spi_write(ds, 1, &dummy, flags);
307 }
308 return 0;
309}
310
Vignesh R192bb752016-07-06 09:58:56 +0530311static int davinci_spi_set_speed(struct udevice *bus, uint max_hz)
312{
313 struct davinci_spi_slave *ds = dev_get_priv(bus);
Sekhar Nori8ed58852010-01-27 11:10:40 -0500314
Vignesh R192bb752016-07-06 09:58:56 +0530315 debug("%s speed %u\n", __func__, max_hz);
316 if (max_hz > CONFIG_SYS_SPI_CLK / 2)
317 return -EINVAL;
318
319 ds->freq = max_hz;
320
Sekhar Nori8ed58852010-01-27 11:10:40 -0500321 return 0;
322}
Vignesh R192bb752016-07-06 09:58:56 +0530323
324static int davinci_spi_set_mode(struct udevice *bus, uint mode)
325{
326 struct davinci_spi_slave *ds = dev_get_priv(bus);
327
328 debug("%s mode %u\n", __func__, mode);
329 ds->mode = mode;
330
331 return 0;
332}
333
334static int davinci_spi_claim_bus(struct udevice *dev)
335{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700336 struct dm_spi_slave_plat *slave_plat =
Simon Glasscaa4daa2020-12-03 16:55:18 -0700337 dev_get_parent_plat(dev);
Vignesh R192bb752016-07-06 09:58:56 +0530338 struct udevice *bus = dev->parent;
339 struct davinci_spi_slave *ds = dev_get_priv(bus);
340
341 if (slave_plat->cs >= ds->num_cs) {
342 printf("Invalid SPI chipselect\n");
343 return -EINVAL;
344 }
345 ds->half_duplex = slave_plat->mode & SPI_PREAMBLE;
346
347 return __davinci_spi_claim_bus(ds, slave_plat->cs);
348}
349
350static int davinci_spi_release_bus(struct udevice *dev)
351{
352 struct davinci_spi_slave *ds = dev_get_priv(dev->parent);
353
354 return __davinci_spi_release_bus(ds);
355}
356
357static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen,
358 const void *dout, void *din,
359 unsigned long flags)
360{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700361 struct dm_spi_slave_plat *slave =
Simon Glasscaa4daa2020-12-03 16:55:18 -0700362 dev_get_parent_plat(dev);
Vignesh R192bb752016-07-06 09:58:56 +0530363 struct udevice *bus = dev->parent;
364 struct davinci_spi_slave *ds = dev_get_priv(bus);
365
366 if (slave->cs >= ds->num_cs) {
367 printf("Invalid SPI chipselect\n");
368 return -EINVAL;
369 }
370 ds->cur_cs = slave->cs;
371
372 return __davinci_spi_xfer(ds, bitlen, dout, din, flags);
373}
374
Vignesh R192bb752016-07-06 09:58:56 +0530375static const struct dm_spi_ops davinci_spi_ops = {
376 .claim_bus = davinci_spi_claim_bus,
377 .release_bus = davinci_spi_release_bus,
378 .xfer = davinci_spi_xfer,
379 .set_speed = davinci_spi_set_speed,
380 .set_mode = davinci_spi_set_mode,
381};
382
Jagan Tekiba3c22b2018-09-03 23:00:23 +0530383static int davinci_spi_probe(struct udevice *bus)
384{
385 struct davinci_spi_slave *ds = dev_get_priv(bus);
Simon Glass0fd3d912020-12-22 19:30:28 -0700386 struct davinci_spi_plat *plat = dev_get_plat(bus);
Jagan Tekiba3c22b2018-09-03 23:00:23 +0530387 ds->regs = plat->regs;
388 ds->num_cs = plat->num_cs;
389
390 return 0;
391}
392
393#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
394static int davinci_ofdata_to_platadata(struct udevice *bus)
395{
Simon Glass0fd3d912020-12-22 19:30:28 -0700396 struct davinci_spi_plat *plat = dev_get_plat(bus);
Jagan Tekiba3c22b2018-09-03 23:00:23 +0530397 fdt_addr_t addr;
398
Masahiro Yamada25484932020-07-17 14:36:48 +0900399 addr = dev_read_addr(bus);
Jagan Tekiba3c22b2018-09-03 23:00:23 +0530400 if (addr == FDT_ADDR_T_NONE)
401 return -EINVAL;
402
403 plat->regs = (struct davinci_spi_regs *)addr;
404 plat->num_cs = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "num-cs", 4);
405
406 return 0;
407}
408
Vignesh R192bb752016-07-06 09:58:56 +0530409static const struct udevice_id davinci_spi_ids[] = {
410 { .compatible = "ti,keystone-spi" },
411 { .compatible = "ti,dm6441-spi" },
Adam Fordab0ac272017-09-17 20:43:45 -0500412 { .compatible = "ti,da830-spi" },
Vignesh R192bb752016-07-06 09:58:56 +0530413 { }
414};
Jagan Tekiba3c22b2018-09-03 23:00:23 +0530415#endif
Vignesh R192bb752016-07-06 09:58:56 +0530416
417U_BOOT_DRIVER(davinci_spi) = {
418 .name = "davinci_spi",
419 .id = UCLASS_SPI,
Jagan Tekiba3c22b2018-09-03 23:00:23 +0530420#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
Vignesh R192bb752016-07-06 09:58:56 +0530421 .of_match = davinci_spi_ids,
Simon Glassd1998a92020-12-03 16:55:21 -0700422 .of_to_plat = davinci_ofdata_to_platadata,
Simon Glass8a8d24b2020-12-03 16:55:23 -0700423 .plat_auto = sizeof(struct davinci_spi_plat),
Jagan Tekiba3c22b2018-09-03 23:00:23 +0530424#endif
Vignesh R192bb752016-07-06 09:58:56 +0530425 .probe = davinci_spi_probe,
Jagan Tekiba3c22b2018-09-03 23:00:23 +0530426 .ops = &davinci_spi_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700427 .priv_auto = sizeof(struct davinci_spi_slave),
Vignesh R192bb752016-07-06 09:58:56 +0530428};