| Wolfgang Denk | 72a087e | 2006-10-24 14:27:35 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Register definitions for Parallel Input/Output Controller |
| 3 | */ |
| 4 | #ifndef __CPU_AT32AP_PIO2_H__ |
| 5 | #define __CPU_AT32AP_PIO2_H__ |
| 6 | |
| 7 | /* PIO2 register offsets */ |
| 8 | #define PIO2_PER 0x0000 |
| 9 | #define PIO2_PDR 0x0004 |
| 10 | #define PIO2_PSR 0x0008 |
| 11 | #define PIO2_OER 0x0010 |
| 12 | #define PIO2_ODR 0x0014 |
| 13 | #define PIO2_OSR 0x0018 |
| 14 | #define PIO2_IFER 0x0020 |
| 15 | #define PIO2_IFDR 0x0024 |
| 16 | #define PIO2_ISFR 0x0028 |
| 17 | #define PIO2_SODR 0x0030 |
| 18 | #define PIO2_CODR 0x0034 |
| 19 | #define PIO2_ODSR 0x0038 |
| 20 | #define PIO2_PDSR 0x003c |
| 21 | #define PIO2_IER 0x0040 |
| 22 | #define PIO2_IDR 0x0044 |
| 23 | #define PIO2_IMR 0x0048 |
| 24 | #define PIO2_ISR 0x004c |
| 25 | #define PIO2_MDER 0x0050 |
| 26 | #define PIO2_MDDR 0x0054 |
| 27 | #define PIO2_MDSR 0x0058 |
| 28 | #define PIO2_PUDR 0x0060 |
| 29 | #define PIO2_PUER 0x0064 |
| 30 | #define PIO2_PUSR 0x0068 |
| 31 | #define PIO2_ASR 0x0070 |
| 32 | #define PIO2_BSR 0x0074 |
| 33 | #define PIO2_ABSR 0x0078 |
| 34 | #define PIO2_OWER 0x00a0 |
| 35 | #define PIO2_OWDR 0x00a4 |
| 36 | #define PIO2_OWSR 0x00a8 |
| 37 | |
| 38 | /* Register access macros */ |
| Haavard Skinnemoen | df548d3 | 2006-11-19 18:06:53 +0100 | [diff] [blame] | 39 | #define pio2_readl(base,reg) \ |
| 40 | readl((void *)base + PIO2_##reg) |
| 41 | #define pio2_writel(base,reg,value) \ |
| 42 | writel((value), (void *)base + PIO2_##reg) |
| Wolfgang Denk | 72a087e | 2006-10-24 14:27:35 +0200 | [diff] [blame] | 43 | |
| 44 | #endif /* __CPU_AT32AP_PIO2_H__ */ |