blob: 5b332e40ee9718839f9d4bf7feffe961a2418210 [file] [log] [blame]
Scott McNutt9cc83372006-06-08 13:37:39 -04001/*
2 * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*------------------------------------------------------------------------
28 * BOARD/CPU
29 *----------------------------------------------------------------------*/
30#define CONFIG_EP1S40 1 /* EP1S40 board */
31#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
32
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */
34#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
35#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */
Scott McNutt9cc83372006-06-08 13:37:39 -040036
37/*------------------------------------------------------------------------
38 * CACHE -- the following will support II/s and II/f. The II/s does not
39 * have dcache, so the cache instructions will behave as NOPs.
40 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */
42#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */
43#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
44#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
Scott McNutt9cc83372006-06-08 13:37:39 -040045
46/*------------------------------------------------------------------------
47 * MEMORY BASE ADDRESSES
48 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */
50#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
51#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */
52#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */
53#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */
54#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB */
Scott McNutt9cc83372006-06-08 13:37:39 -040055
56/*------------------------------------------------------------------------
57 * MEMORY ORGANIZATION
58 * -Monitor at top.
59 * -The heap is placed below the monitor.
60 * -Global data is placed below the heap.
61 * -The stack is placed below global data (&grows down).
62 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */
64#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/
65#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) /* 256k heap */
Scott McNutt9cc83372006-06-08 13:37:39 -040066
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
68#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
69#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
70#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
Scott McNutt9cc83372006-06-08 13:37:39 -040071
72/*------------------------------------------------------------------------
73 * FLASH (AM29LV065D)
74 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */
76#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */
77#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
78#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
Scott McNutt9cc83372006-06-08 13:37:39 -040079
80/*------------------------------------------------------------------------
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081 * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
82 * CONFIG_SYS_FLASH_BASE, since we assume that u-boot is stored at the bottom
Scott McNutt9cc83372006-06-08 13:37:39 -040083 * of flash memory. This will keep the environment in user region
84 * of flash. NOTE: the monitor length must be multiple of sector size
85 * (which is common practice).
86 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020087#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020088#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
Scott McNutt9cc83372006-06-08 13:37:39 -040089#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
Scott McNutt9cc83372006-06-08 13:37:39 -040091
92/*------------------------------------------------------------------------
93 * CONSOLE
94 *----------------------------------------------------------------------*/
95#if defined(CONFIG_CONSOLE_JTAG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
Scott McNutt9cc83372006-06-08 13:37:39 -040097#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
Scott McNutt9cc83372006-06-08 13:37:39 -040099#endif
100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
Scott McNutt9cc83372006-06-08 13:37:39 -0400102#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
Scott McNutt9cc83372006-06-08 13:37:39 -0400104
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
Scott McNutt9cc83372006-06-08 13:37:39 -0400106
107/*------------------------------------------------------------------------
108 * EPCS Device -- None for stratix.
109 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#undef CONFIG_SYS_NIOS_EPCSBASE
Scott McNutt9cc83372006-06-08 13:37:39 -0400111
112/*------------------------------------------------------------------------
113 * DEBUG
114 *----------------------------------------------------------------------*/
115#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
116
117/*------------------------------------------------------------------------
118 * TIMEBASE --
119 *
120 * The high res timer defaults to 1 msec. Since it includes the period
121 * registers, we can slow it down to 10 msec using TMRCNT. If the default
122 * period is acceptable, TMRCNT can be left undefined.
123 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
125#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
126#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */
127#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
128#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1))
Scott McNutt9cc83372006-06-08 13:37:39 -0400129
130/*------------------------------------------------------------------------
131 * STATUS LED -- Provides a simple blinking led. For Nios2 each board
132 * must implement its own led routines -- since leds are board-specific.
133 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
Scott McNutt9cc83372006-06-08 13:37:39 -0400135#define CONFIG_STATUS_LED /* Enable status driver */
136
137#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
138#define STATUS_LED_STATE 1 /* Blinking */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */
Scott McNutt9cc83372006-06-08 13:37:39 -0400140
141/*------------------------------------------------------------------------
142 * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
143 * and really doesn't need any additional clutter. So I choose the lazy
144 * way out to avoid changes there -- define the base address to ensure
145 * cache bypass so there's no need to monkey with inx/outx macros.
146 *----------------------------------------------------------------------*/
147#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
Ben Warren7194ab82009-10-04 22:37:03 -0700148#define CONFIG_NET_MULTI
149#define CONFIG_SMC91111 /* Using SMC91c111 */
Scott McNutt9cc83372006-06-08 13:37:39 -0400150#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
151#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
152
153#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
154#define CONFIG_NETMASK 255.255.255.0
155#define CONFIG_IPADDR 192.168.2.21
156#define CONFIG_SERVERIP 192.168.2.16
157
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500158
159/*
Jon Loeliger11799432007-07-10 09:02:57 -0500160 * BOOTP options
161 */
162#define CONFIG_BOOTP_BOOTFILESIZE
163#define CONFIG_BOOTP_BOOTPATH
164#define CONFIG_BOOTP_GATEWAY
165#define CONFIG_BOOTP_HOSTNAME
166
167
168/*
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500169 * Command line configuration.
170 */
171#define CONFIG_CMD_BDI
172#define CONFIG_CMD_DHCP
173#define CONFIG_CMD_ECHO
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500174#define CONFIG_CMD_SAVEENV
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500175#define CONFIG_CMD_FLASH
176#define CONFIG_CMD_IMI
177#define CONFIG_CMD_IRQ
178#define CONFIG_CMD_LOADS
179#define CONFIG_CMD_LOADB
180#define CONFIG_CMD_MEMORY
181#define CONFIG_CMD_MISC
182#define CONFIG_CMD_NET
183#define CONFIG_CMD_PING
184#define CONFIG_CMD_RUN
185#define CONFIG_CMD_SAVES
186
Scott McNutt9cc83372006-06-08 13:37:39 -0400187
188/*------------------------------------------------------------------------
189 * MISC
190 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_LONGHELP /* Provide extended help*/
192#define CONFIG_SYS_PROMPT "==> " /* Command prompt */
193#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
194#define CONFIG_SYS_MAXARGS 16 /* Max command args */
195#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */
196#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
197#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */
198#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */
199#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000
Scott McNutt9cc83372006-06-08 13:37:39 -0400200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_HUSH_PARSER
202#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Scott McNutt9cc83372006-06-08 13:37:39 -0400203
204#endif /* __CONFIG_H */