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Timo Tuunainenea8d9892008-02-01 10:09:03 +00001/*
2 * Based on Modifications by Alan Lu / Artila and
3 * Rick Bronson <rick@efn.org>
4 *
5 * Configuration settings for the Artila M-501 starter kit,
6 * with V02 processor card.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/* ARM asynchronous clock */
31/* from 18.432 MHz crystal (18432000 / 4 * 39) */
32#define AT91C_MAIN_CLOCK 179712000
33/* Perip clock (AT91C_MASTER_CLOCK / 3) */
34#define AT91C_MASTER_CLOCK 59904000
35#define AT91_SLOW_CLOCK 32768 /* slow clock */
36
37#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
38#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
40#define CONFIG_SETUP_MEMORY_TAGS 1
41#define CONFIG_INITRD_TAG 1
42
Timo Tuunainenea8d9892008-02-01 10:09:03 +000043#define CONFIG_MENUPROMPT "."
Jean-Christophe PLAGNIOL-VILLARD8a486862009-01-03 17:22:26 +010044/*
45 * LowLevel Init
46 */
47#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
48/* flash */
Jean-Christophe PLAGNIOL-VILLARD8a486862009-01-03 17:22:26 +010049#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
50#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
51
52/* clocks */
53#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
54#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
55/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
56#define CONFIG_SYS_MCKR_VAL 0x00000202
57
58/* sdram */
59#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
60#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
61#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
62#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
63#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
64#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
65#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
66#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
67#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
68#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
69#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
70#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
71#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
Timo Tuunainenea8d9892008-02-01 10:09:03 +000072
73/*
74 * Size of malloc() pool
75 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
77#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Bytes reserved for initial data */
Timo Tuunainenea8d9892008-02-01 10:09:03 +000078
79#define CONFIG_BAUDRATE 115200
80
81/* Hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33
Timo Tuunainenea8d9892008-02-01 10:09:03 +000083
84/*
85 * Hardware drivers
86 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020088#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020089#define CONFIG_ENV_SECT_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
91#define CONFIG_SYS_FLASH_PROTECTION /*for Intel P30 Flash*/
Timo Tuunainenea8d9892008-02-01 10:09:03 +000092#define CONFIG_HARD_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_I2C_SPEED 100
94#define CONFIG_SYS_I2C_SLAVE 0
95#define CONFIG_SYS_CONSOLE_INFO_QUIET
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +020096#undef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
98#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
99#define CONFIG_SYS_EEPROM_AT24C16
100#define CONFIG_SYS_I2C_RTC_ADDR 0x32
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000101#undef CONFIG_RTC_DS1338
102#define CONFIG_RTC_RS5C372A
103#undef CONFIG_POST
104#define CONFIG_M501SK
105#define CONFIG_CMC_PU2
106
107/* define one of these to choose the DBGU, USART0 or USART1 as console */
Jean-Christophe PLAGNIOL-VILLARDbeebd852009-03-27 23:26:43 +0100108#define CONFIG_AT91RM9200_USART
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000109#define CONFIG_DBGU
110#undef CONFIG_USART0
111#undef CONFIG_USART1
112
113#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
114#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
115
116#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200 " \
117 "initrd=0x20800000,8192000 ramdisk_size=15360 " \
118 "root=/dev/ram0 rw mtdparts=phys_mapped_flash:" \
119 "128k(loader)ro,128k(reserved)ro,1408k(linux)" \
120 "ro,2560k(ramdisk)ro,-(userdisk)"
121#define CONFIG_BOOTCOMMAND "bootm 10040000 101a0000"
122#define CONFIG_BOOTDELAY 1
123#define CONFIG_BAUDRATE 115200
124#define CONFIG_IPADDR 192.168.1.100
125#define CONFIG_SERVERIP 192.168.1.1
126#define CONFIG_GATEWAYIP 192.168.1.254
127#define CONFIG_NETMASK 255.255.255.0
128#define CONFIG_BOOTFILE uImage
129#define CONFIG_ETHADDR 00:13:48:aa:bb:cc
130#define CONFIG_ENV_OVERWRITE 1
131#define BOARD_LATE_INIT
132
133#define CONFIG_EXTRA_ENV_SETTINGS \
134 "unlock=yes\0"
135
Jean-Christophe PLAGNIOL-VILLARD936897d2008-07-25 15:18:16 +0200136#define CONFIG_CMD_JFFS2
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000137#undef CONFIG_CMD_EEPROM
138#define CONFIG_CMD_NET
139#define CONFIG_CMD_RUN
140#define CONFIG_CMD_DHCP
141#define CONFIG_CMD_MEMORY
142#define CONFIG_CMD_PING
143#define CONFIG_CMD_SDRAM
144#define CONFIG_CMD_DIAG
145#define CONFIG_CMD_I2C
146#define CONFIG_CMD_DATE
147#define CONFIG_CMD_POST
148#define CONFIG_CMD_MISC
149#define CONFIG_CMD_LOADS
150#define CONFIG_CMD_IMI
151#define CONFIG_CMD_NFS
152#define CONFIG_CMD_FLASH
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500153#define CONFIG_CMD_SAVEENV
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_HUSH_PARSER
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000156#define CONFIG_AUTO_COMPLETE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_PROMPT_HUSH_PS2 ">>"
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_MAX_NAND_DEVICE 0 /* Max number of NAND devices */
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000160
161#define CONFIG_NR_DRAM_BANKS 1
162#define PHYS_SDRAM 0x20000000
163#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_MEMTEST_START 0x21000000 /* PHYS_SDRAM */
166/* CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */
167#define CONFIG_SYS_MEMTEST_END 0x00100000
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000168
169#define CONFIG_DRIVER_ETHER
170#define CONFIG_NET_RETRY_COUNT 20
171#define CONFIG_AT91C_USE_RMII
172
173#define PHYS_FLASH_1 0x10000000
174#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
176#define CONFIG_SYS_MAX_FLASH_BANKS 1
177#define CONFIG_SYS_MAX_FLASH_SECT 256
178#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
179#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000180
Jean-Christophe PLAGNIOL-VILLARD057c8492008-09-10 22:47:58 +0200181#ifdef CONFIG_ENV_IS_IN_DATAFLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200182#define CONFIG_ENV_OFFSET 0x20000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200184#define CONFIG_ENV_SIZE 0x2000
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000185#else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200186#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200187#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x00020000)
188#define CONFIG_ENV_SIZE 2048
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000189#endif
190
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200191#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200192#define CONFIG_ENV_OFFSET 1024
193#define CONFIG_ENV_SIZE 1024
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000194#endif
195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000197
198/* use for protect flash sectors */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */
200#define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
201#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_BAUDRATE_TABLE { 115200 , 19200, 38400, 57600, 9600 }
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
206#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
207#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000208/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_HZ 1000
212#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2
Timo Tuunainenea8d9892008-02-01 10:09:03 +0000213
214#define CONFIG_STACKSIZE (32*1024) /* regular stack */
215
216#ifdef CONFIG_USE_IRQ
217#error CONFIG_USE_IRQ not supported
218#endif
219
220#endif