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Heiko Schocher075866d2006-02-20 17:34:12 +01001/*
2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004-2005
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 * (easy to change)
33 */
34
35#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
38#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
39
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
Heiko Schocher075866d2006-02-20 17:34:12 +010041
42#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
43#define BOOTFLAG_WARM 0x02 /* Software reboot */
44
Becky Bruce31d82672008-05-08 19:02:12 -050045#define CONFIG_HIGH_BATS 1 /* High BATs supported */
46
Heiko Schocher075866d2006-02-20 17:34:12 +010047/*
48 * Serial console configuration
49 */
50#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
51#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Heiko Schocher075866d2006-02-20 17:34:12 +010053
54/* Partitions */
55#define CONFIG_MAC_PARTITION
56#define CONFIG_DOS_PARTITION
57#define CONFIG_ISO_PARTITION
58
59/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
61 CONFIG_SYS_POST_CPU | \
62 CONFIG_SYS_POST_I2C)
Heiko Schocher075866d2006-02-20 17:34:12 +010063
64#ifdef CONFIG_POST
Heiko Schocher075866d2006-02-20 17:34:12 +010065/* preserve space for the post_word at end of on-chip SRAM */
66#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
Heiko Schocher075866d2006-02-20 17:34:12 +010067#endif
68
Heiko Schocher075866d2006-02-20 17:34:12 +010069
Jon Loeliger46da1e92007-07-04 22:33:30 -050070/*
Jon Loeliger079a1362007-07-10 10:12:10 -050071 * BOOTP options
72 */
73#define CONFIG_BOOTP_BOOTFILESIZE
74#define CONFIG_BOOTP_BOOTPATH
75#define CONFIG_BOOTP_GATEWAY
76#define CONFIG_BOOTP_HOSTNAME
77
78
79/*
Jon Loeliger46da1e92007-07-04 22:33:30 -050080 * Command line configuration.
81 */
82#include <config_cmd_default.h>
83#define CONFIG_CMD_ASKENV
84#define CONFIG_CMD_DATE
85#define CONFIG_CMD_DHCP
86#define CONFIG_CMD_ECHO
87#define CONFIG_CMD_EEPROM
88#define CONFIG_CMD_I2C
89#define CONFIG_CMD_JFFS2
90#define CONFIG_CMD_MII
91#define CONFIG_CMD_NFS
92#define CONFIG_CMD_PING
Jon Loeliger46da1e92007-07-04 22:33:30 -050093#define CONFIG_CMD_REGINFO
94#define CONFIG_CMD_SNTP
95
Jon Loeligeraf075ee2007-07-08 17:02:01 -050096#ifdef CONFIG_POST
97#define CONFIG_CMD_DIAG
98#endif
99
Heiko Schocher075866d2006-02-20 17:34:12 +0100100
101#define CONFIG_TIMESTAMP /* display image timestamps */
102
103#if (TEXT_BASE == 0xFC000000) /* Boot low */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104# define CONFIG_SYS_LOWBOOT 1
Heiko Schocher075866d2006-02-20 17:34:12 +0100105#endif
106
107/*
108 * Autobooting
109 */
110#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
111
112#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100113 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Heiko Schocher075866d2006-02-20 17:34:12 +0100114 "echo"
115
116#undef CONFIG_BOOTARGS
117
118#define CONFIG_EXTRA_ENV_SETTINGS \
119 "netdev=eth0\0" \
120 "rootpath=/opt/eldk/ppc_6xx\0" \
121 "ramargs=setenv bootargs root=/dev/ram rw\0" \
122 "nfsargs=setenv bootargs root=/dev/nfs rw " \
123 "nfsroot=${serverip}:${rootpath}\0" \
124 "addip=setenv bootargs ${bootargs} " \
125 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
126 ":${hostname}:${netdev}:off panic=1\0" \
127 "flash_self=run ramargs addip;" \
128 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
129 "flash_nfs=run nfsargs addip;" \
130 "bootm ${kernel_addr}\0" \
131 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
132 "bootfile=/tftpboot/smmaco4/uImage\0" \
133 "load=tftp 200000 ${u-boot}\0" \
134 "u-boot=/tftpboot/smmaco4/u-boot.bin\0" \
135 "update=protect off FC000000 FC05FFFF;" \
136 "erase FC000000 FC05FFFF;" \
137 "cp.b 200000 FC000000 ${filesize};" \
138 "protect on FC000000 FC05FFFF\0" \
139 ""
140
141#define CONFIG_BOOTCOMMAND "run net_nfs"
142
143/*
144 * IPB Bus clocking configuration.
145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Heiko Schocher075866d2006-02-20 17:34:12 +0100147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
Heiko Schocher075866d2006-02-20 17:34:12 +0100149/*
150 * PCI Bus clocking configuration
151 *
152 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200154 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
Heiko Schocher075866d2006-02-20 17:34:12 +0100155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
Heiko Schocher075866d2006-02-20 17:34:12 +0100157#endif
158
159/*
160 * I2C configuration
161 */
162#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
163#ifdef CONFIG_TQM5200_REV100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
Heiko Schocher075866d2006-02-20 17:34:12 +0100165#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
Heiko Schocher075866d2006-02-20 17:34:12 +0100167#endif
168
169/*
170 * I2C clock frequency
171 *
172 * Please notice, that the resulting clock frequency could differ from the
173 * configured value. This is because the I2C clock is derived from system
174 * clock over a frequency divider with only a few divider values. U-boot
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
Heiko Schocher075866d2006-02-20 17:34:12 +0100176 * approximation allways lies below the configured value, never above.
177 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
179#define CONFIG_SYS_I2C_SLAVE 0x7F
Heiko Schocher075866d2006-02-20 17:34:12 +0100180
181/*
182 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
183 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
184 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
185 * same configuration could be used.
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
188#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
189#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
190#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
Heiko Schocher075866d2006-02-20 17:34:12 +0100191
192/*
193 * Flash configuration
194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_FLASH_BASE TEXT_BASE /* 0xFC000000 */
Heiko Schocher075866d2006-02-20 17:34:12 +0100196
197/* use CFI flash driver if no module variant is spezified */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200199#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
201#define CONFIG_SYS_FLASH_EMPTY_INFO
202#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
203#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
204#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
Heiko Schocher075866d2006-02-20 17:34:12 +0100205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#if !defined(CONFIG_SYS_LOWBOOT)
207#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
208#else /* CONFIG_SYS_LOWBOOT */
209#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
210#endif /* CONFIG_SYS_LOWBOOT */
211#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
Heiko Schocher075866d2006-02-20 17:34:12 +0100212 (= chip selects) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
214#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
Heiko Schocher075866d2006-02-20 17:34:12 +0100215
216/* Dynamic MTD partition support */
Stefan Roese68d7d652009-03-19 13:30:36 +0100217#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200218#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
219#define CONFIG_FLASH_CFI_MTD
Heiko Schocher075866d2006-02-20 17:34:12 +0100220#define MTDIDS_DEFAULT "nor0=TQM5200-0"
221#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
222 "1408k(kernel)," \
223 "2m(initrd)," \
224 "4m(small-fs)," \
225 "16m(big-fs)," \
226 "8m(misc)"
227
228/*
229 * Environment settings
230 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200231#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200232#define CONFIG_ENV_SIZE 0x10000
233#define CONFIG_ENV_SECT_SIZE 0x20000
234#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
235#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Heiko Schocher075866d2006-02-20 17:34:12 +0100236
237/*
238 * Memory map
239 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_MBAR 0xF0000000
241#define CONFIG_SYS_SDRAM_BASE 0x00000000
242#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Heiko Schocher075866d2006-02-20 17:34:12 +0100243
244/* Use ON-Chip SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Heiko Schocher075866d2006-02-20 17:34:12 +0100246#ifdef CONFIG_POST
247/* preserve space for the post_word at end of on-chip SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
Heiko Schocher075866d2006-02-20 17:34:12 +0100249#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
Heiko Schocher075866d2006-02-20 17:34:12 +0100251#endif
252
253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
255#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
256#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schocher075866d2006-02-20 17:34:12 +0100257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
259#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
260# define CONFIG_SYS_RAMBOOT 1
Heiko Schocher075866d2006-02-20 17:34:12 +0100261#endif
262
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
264#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
265#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schocher075866d2006-02-20 17:34:12 +0100266
267/*
268 * Ethernet configuration
269 */
270#define CONFIG_MPC5xxx_FEC 1
271/*
272 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
273 */
274/* #define CONFIG_FEC_10MBIT 1 */
275#define CONFIG_PHY_ADDR 0x00
276
277/*
278 * GPIO configuration
279 *
280 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
281 * Bit 0 (mask: 0x80000000): 1
282 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
283 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
284 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
285 * Use for REV200 STK52XX boards. Do not use with REV100 modules
286 * (because, there I2C1 is used as I2C bus)
287 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
288 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
289 * 000 -> All PSC2 pins are GIOPs
290 * 001 -> CAN1/2 on PSC2 pins
291 * Use for REV100 STK52xx boards
292 * use PSC6:
293 * on STK52xx:
294 * use as UART. Pins PSC6_0 to PSC6_3 are used.
295 * Bits 9:11 (mask: 0x00700000):
296 * 101 -> PSC6 : Extended POST test is not available
297 * on MINI-FAP and TQM5200_IB:
298 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
299 * 000 -> PSC6 could not be used as UART, CODEC or IrDA
300 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
301 * tests.
302 */
303#if defined (CONFIG_MINIFAP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
Heiko Schocher075866d2006-02-20 17:34:12 +0100305#elif defined (CONFIG_STK52XX)
306# if defined (CONFIG_STK52XX_REV100)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
Heiko Schocher075866d2006-02-20 17:34:12 +0100308# else /* STK52xx REV200 and above */
309# if defined (CONFIG_TQM5200_REV100)
310# error TQM5200 REV100 not supported on STK52XX REV200 or above
311# else/* TQM5200 REV200 and above */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500004
Heiko Schocher075866d2006-02-20 17:34:12 +0100313# endif
314# endif
315#else /* TMQ5200 Inbetriebnahme-Board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
Heiko Schocher075866d2006-02-20 17:34:12 +0100317#endif
318
319/*
320 * RTC configuration
321 */
322#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
323
324/*
325 * Miscellaneous configurable options
326 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_LONGHELP /* undef to save memory */
328#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500329#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Heiko Schocher075866d2006-02-20 17:34:12 +0100331#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Heiko Schocher075866d2006-02-20 17:34:12 +0100333#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
335#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
336#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Heiko Schocher075866d2006-02-20 17:34:12 +0100337
338/* Enable an alternate, more extensive memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_ALT_MEMTEST
Heiko Schocher075866d2006-02-20 17:34:12 +0100340
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
342#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Heiko Schocher075866d2006-02-20 17:34:12 +0100343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Heiko Schocher075866d2006-02-20 17:34:12 +0100345
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Heiko Schocher075866d2006-02-20 17:34:12 +0100347
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500349#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500351#endif
352
Heiko Schocher075866d2006-02-20 17:34:12 +0100353/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500354 * Enable loopw command.
Heiko Schocher075866d2006-02-20 17:34:12 +0100355 */
356#define CONFIG_LOOPW
357
358/*
359 * Various low-level settings
360 */
361#if defined(CONFIG_MPC5200)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
363#define CONFIG_SYS_HID0_FINAL HID0_ICE
Heiko Schocher075866d2006-02-20 17:34:12 +0100364#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_HID0_INIT 0
366#define CONFIG_SYS_HID0_FINAL 0
Heiko Schocher075866d2006-02-20 17:34:12 +0100367#endif
368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
370#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
371#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
372#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
Heiko Schocher075866d2006-02-20 17:34:12 +0100373#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
Heiko Schocher075866d2006-02-20 17:34:12 +0100375#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
377#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Heiko Schocher075866d2006-02-20 17:34:12 +0100378
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_CS_BURST 0x00000000
380#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
Heiko Schocher075866d2006-02-20 17:34:12 +0100381
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Heiko Schocher075866d2006-02-20 17:34:12 +0100383
384#endif /* __CONFIG_H */