blob: 3eb0049a04f22c9eae1996a0bf96b8a68eceec84 [file] [log] [blame]
Jon Loeligerd9b94f22005-07-25 14:05:07 -05001/*
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -05002 * Copyright 2004, 2007 Freescale Semiconductor.
Jon Loeligerd9b94f22005-07-25 14:05:07 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050014 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Jon Loeligerd9b94f22005-07-25 14:05:07 -050015 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8548cds board configuration file
25 *
26 * Please refer to doc/README.mpc85xxcds for more info.
27 *
28 */
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/* High Level Configuration Options */
33#define CONFIG_BOOKE 1 /* BOOKE */
34#define CONFIG_E500 1 /* BOOKE e500 family */
35#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
36#define CONFIG_MPC8548 1 /* MPC8548 specific */
37#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
38
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050039#define CONFIG_PCI /* enable any pci type devices */
40#define CONFIG_PCI1 /* PCI controller 1 */
41#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
42#undef CONFIG_RIO
43#undef CONFIG_PCI2
44#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Kumar Gala8ff3de62007-12-07 12:17:34 -060045#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050046#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050047
48#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050049#define CONFIG_ENV_OVERWRITE
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050050#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
Kumar Gala2cfaa1a2008-01-16 01:45:10 -060051#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050052
Jon Loeliger25eedb22008-03-19 15:02:07 -050053#define CONFIG_FSL_VIA
Jon Loeliger25eedb22008-03-19 15:02:07 -050054
Jon Loeligerd9b94f22005-07-25 14:05:07 -050055#ifndef __ASSEMBLY__
56extern unsigned long get_clock_freq(void);
57#endif
58#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
59
60/*
61 * These can be toggled for performance analysis, otherwise use default.
62 */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050063#define CONFIG_L2_CACHE /* toggle L2 cache */
64#define CONFIG_BTB /* toggle branch predition */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050065
66/*
67 * Only possible on E500 Version 2 or newer cores.
68 */
69#define CONFIG_ENABLE_36BIT_PHYS 1
70
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
72#define CONFIG_SYS_MEMTEST_END 0x00400000
Jon Loeligerd9b94f22005-07-25 14:05:07 -050073
74/*
75 * Base addresses -- Note these are effective addresses where the
76 * actual resources get mapped (not physical addresses)
77 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
79#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
80#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
81#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050082
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
84#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
85#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050086
Jon Loeligere31d2c12008-03-18 13:51:06 -050087/* DDR Setup */
88#define CONFIG_FSL_DDR2
89#undef CONFIG_FSL_DDR_INTERACTIVE
90#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
91#define CONFIG_DDR_SPD
92#define CONFIG_DDR_DLL /* possible DLL fix needed */
93
Dave Liu9b0ad1b2008-10-28 17:53:38 +080094#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Jon Loeligere31d2c12008-03-18 13:51:06 -050095#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
96
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
98#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Jon Loeligerd9b94f22005-07-25 14:05:07 -050099
Jon Loeligere31d2c12008-03-18 13:51:06 -0500100#define CONFIG_NUM_DDR_CONTROLLERS 1
101#define CONFIG_DIMM_SLOTS_PER_CTLR 1
102#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500103
Jon Loeligere31d2c12008-03-18 13:51:06 -0500104/* I2C addresses of SPD EEPROMs */
105#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
106
107/* Make sure required options are set */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500108#ifndef CONFIG_SPD_EEPROM
109#error ("CONFIG_SPD_EEPROM is required")
110#endif
111
112#undef CONFIG_CLOCKS_IN_MHZ
113
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500114/*
115 * Local Bus Definitions
116 */
117
118/*
119 * FLASH on the Local Bus
120 * Two banks, 8M each, using the CFI driver.
121 * Boot from BR0/OR0 bank at 0xff00_0000
122 * Alternate BR1/OR1 bank at 0xff80_0000
123 *
124 * BR0, BR1:
125 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
126 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
127 * Port Size = 16 bits = BRx[19:20] = 10
128 * Use GPCM = BRx[24:26] = 000
129 * Valid = BRx[31] = 1
130 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500131 * 0 4 8 12 16 20 24 28
132 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
133 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500134 *
135 * OR0, OR1:
136 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
137 * Reserved ORx[17:18] = 11, confusion here?
138 * CSNT = ORx[20] = 1
139 * ACS = half cycle delay = ORx[21:22] = 11
140 * SCY = 6 = ORx[24:27] = 0110
141 * TRLX = use relaxed timing = ORx[29] = 1
142 * EAD = use external address latch delay = OR[31] = 1
143 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500144 * 0 4 8 12 16 20 24 28
145 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500146 */
147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */
149#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_BR0_PRELIM 0xff801001
152#define CONFIG_SYS_BR1_PRELIM 0xff001001
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_OR0_PRELIM 0xff806e65
155#define CONFIG_SYS_OR1_PRELIM 0xff806e65
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
158#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
159#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
160#undef CONFIG_SYS_FLASH_CHECKSUM
161#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
162#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500165
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200166#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_FLASH_CFI
168#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500169
170
171/*
172 * SDRAM on the Local Bus
173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
175#define CONFIG_SYS_LBC_CACHE_SIZE 64
176#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */
177#define CONFIG_SYS_LBC_NONCACHE_SIZE 64
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */
180#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500181
182/*
183 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500185 *
186 * For BR2, need:
187 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
188 * port-size = 32-bits = BR2[19:20] = 11
189 * no parity checking = BR2[21:22] = 00
190 * SDRAM for MSEL = BR2[24:26] = 011
191 * Valid = BR[31] = 1
192 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500193 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500194 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
195 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500197 * FIXME: the top 17 bits of BR2.
198 */
199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_BR2_PRELIM 0xf0001861
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500201
202/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500204 *
205 * For OR2, need:
206 * 64MB mask for AM, OR2[0:7] = 1111 1100
207 * XAM, OR2[17:18] = 11
208 * 9 columns OR2[19-21] = 010
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500209 * 13 rows OR2[23-25] = 100
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500210 * EAD set for extra time OR[31] = 1
211 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500212 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500213 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
214 */
215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_OR2_PRELIM 0xfc006901
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
219#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
220#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
221#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500222
223/*
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500224 * Common settings for all Local Bus SDRAM commands.
225 * At run time, either BSMA1516 (for CPU 1.1)
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500226 * or BSMA1617 (for CPU 1.0) (old)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500227 * is OR'ed in too.
228 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500229#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
230 | LSDMR_PRETOACT7 \
231 | LSDMR_ACTTORW7 \
232 | LSDMR_BL8 \
233 | LSDMR_WRC4 \
234 | LSDMR_CL3 \
235 | LSDMR_RFEN \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500236 )
237
238/*
239 * The CADMUS registers are connected to CS3 on CDS.
240 * The new memory map places CADMUS at 0xf8000000.
241 *
242 * For BR3, need:
243 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
244 * port-size = 8-bits = BR[19:20] = 01
245 * no parity checking = BR[21:22] = 00
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500246 * GPMC for MSEL = BR[24:26] = 000
247 * Valid = BR[31] = 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500248 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500249 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500250 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
251 *
252 * For OR3, need:
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500253 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500254 * disable buffer ctrl OR[19] = 0
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500255 * CSNT OR[20] = 1
256 * ACS OR[21:22] = 11
257 * XACS OR[23] = 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500258 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500259 * SETA OR[28] = 0
260 * TRLX OR[29] = 1
261 * EHTR OR[30] = 1
262 * EAD extra time OR[31] = 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500263 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500264 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500265 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
266 */
267
Jon Loeliger25eedb22008-03-19 15:02:07 -0500268#define CONFIG_FSL_CADMUS
269
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500270#define CADMUS_BASE_ADDR 0xf8000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_BR3_PRELIM 0xf8000801
272#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500273
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_INIT_RAM_LOCK 1
275#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
276#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500277
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500279
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
281#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
282#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500283
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
285#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500286
287/* Serial Port */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500288#define CONFIG_CONS_INDEX 2
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500289#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_NS16550
291#define CONFIG_SYS_NS16550_SERIAL
292#define CONFIG_SYS_NS16550_REG_SIZE 1
293#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500294
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500296 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
297
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
299#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500300
301/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_HUSH_PARSER
303#ifdef CONFIG_SYS_HUSH_PARSER
304#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500305#endif
306
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500307/* pass open firmware flat tree */
Kumar Galab90d2542007-11-29 00:11:44 -0600308#define CONFIG_OF_LIBFDT 1
309#define CONFIG_OF_BOARD_SETUP 1
310#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500311
Jon Loeliger20476722006-10-20 15:50:15 -0500312/*
313 * I2C
314 */
315#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
316#define CONFIG_HARD_I2C /* I2C with hardware support*/
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500317#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
319#define CONFIG_SYS_I2C_SLAVE 0x7F
320#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
321#define CONFIG_SYS_I2C_OFFSET 0x3000
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500322
Timur Tabie8d18542008-07-18 16:52:23 +0200323/* EEPROM */
324#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_I2C_EEPROM_CCID
326#define CONFIG_SYS_ID_EEPROM
327#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
328#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Timur Tabie8d18542008-07-18 16:52:23 +0200329
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500330/*
331 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300332 * Memory space is mapped 1-1, but I/O space must start from 0.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500333 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600334#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500336
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600337#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600338#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600339#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600341#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600342#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
344#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500345
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500346#ifdef CONFIG_PCI2
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600347#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600348#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600349#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600351#define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600352#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
354#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500355#endif
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500356
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500357#ifdef CONFIG_PCIE1
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600358#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600359#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600360#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600362#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600363#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
365#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500366#endif
Zang Roy-r6191141fb7e02006-12-14 14:14:55 +0800367
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500368#ifdef CONFIG_RIO
Zang Roy-r6191141fb7e02006-12-14 14:14:55 +0800369/*
370 * RapidIO MMU
371 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600372#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600373#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500375#endif
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500376
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700377#ifdef CONFIG_LEGACY
378#define BRIDGE_ID 17
379#define VIA_ID 2
380#else
381#define BRIDGE_ID 28
382#define VIA_ID 4
383#endif
384
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500385#if defined(CONFIG_PCI)
386
387#define CONFIG_NET_MULTI
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500388#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500389
390#undef CONFIG_EEPRO100
391#undef CONFIG_TULIP
392
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500393#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500394
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500395#endif /* CONFIG_PCI */
396
397
398#if defined(CONFIG_TSEC_ENET)
399
400#ifndef CONFIG_NET_MULTI
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500401#define CONFIG_NET_MULTI 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500402#endif
403
404#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500405#define CONFIG_TSEC1 1
406#define CONFIG_TSEC1_NAME "eTSEC0"
407#define CONFIG_TSEC2 1
408#define CONFIG_TSEC2_NAME "eTSEC1"
409#define CONFIG_TSEC3 1
410#define CONFIG_TSEC3_NAME "eTSEC2"
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500411#define CONFIG_TSEC4
Kim Phillips255a35772007-05-16 16:52:19 -0500412#define CONFIG_TSEC4_NAME "eTSEC3"
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500413#undef CONFIG_MPC85XX_FEC
414
415#define TSEC1_PHY_ADDR 0
416#define TSEC2_PHY_ADDR 1
417#define TSEC3_PHY_ADDR 2
418#define TSEC4_PHY_ADDR 3
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500419
420#define TSEC1_PHYIDX 0
421#define TSEC2_PHYIDX 0
422#define TSEC3_PHYIDX 0
423#define TSEC4_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500424#define TSEC1_FLAGS TSEC_GIGABIT
425#define TSEC2_FLAGS TSEC_GIGABIT
426#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
427#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500428
429/* Options are: eTSEC[0-3] */
430#define CONFIG_ETHPRIME "eTSEC0"
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500431#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500432#endif /* CONFIG_TSEC_ENET */
433
434/*
435 * Environment
436 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200437#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200439#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
440#define CONFIG_ENV_SIZE 0x2000
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500441
442#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500444
Jon Loeliger2835e512007-06-13 13:22:08 -0500445/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500446 * BOOTP options
447 */
448#define CONFIG_BOOTP_BOOTFILESIZE
449#define CONFIG_BOOTP_BOOTPATH
450#define CONFIG_BOOTP_GATEWAY
451#define CONFIG_BOOTP_HOSTNAME
452
453
454/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500455 * Command line configuration.
456 */
457#include <config_cmd_default.h>
458
459#define CONFIG_CMD_PING
460#define CONFIG_CMD_I2C
461#define CONFIG_CMD_MII
Kumar Gala82ac8c92007-12-07 12:04:30 -0600462#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500463#define CONFIG_CMD_IRQ
464#define CONFIG_CMD_SETEXPR
Jon Loeliger2835e512007-06-13 13:22:08 -0500465
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500466#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500467 #define CONFIG_CMD_PCI
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500468#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500469
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500470
471#undef CONFIG_WATCHDOG /* watchdog disabled */
472
473/*
474 * Miscellaneous configurable options
475 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200476#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kumar Gala22abb2d2007-11-29 10:34:28 -0600477#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
479#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500480#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200481#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500482#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200483#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500484#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
486#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
487#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
488#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500489
490/*
491 * For booting Linux, the board info and command line data
Kumar Gala89188a62009-07-15 08:54:50 -0500492 * have to be in the first 16 MB of memory, since this is
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500493 * the maximum mapped by the Linux kernel during initialization.
494 */
Kumar Gala89188a62009-07-15 08:54:50 -0500495#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500496
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500497/*
498 * Internal Definitions
499 *
500 * Boot Flags
501 */
502#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
503#define BOOTFLAG_WARM 0x02 /* Software reboot */
504
Jon Loeliger2835e512007-06-13 13:22:08 -0500505#if defined(CONFIG_CMD_KGDB)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500506#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
507#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
508#endif
509
510/*
511 * Environment Configuration
512 */
513
514/* The mac addresses for all ethernet interface */
515#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500516#define CONFIG_HAS_ETH0
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500517#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500518#define CONFIG_HAS_ETH1
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500519#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500520#define CONFIG_HAS_ETH2
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500521#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
Andy Fleming09f3e092006-09-13 10:34:18 -0500522#define CONFIG_HAS_ETH3
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500523#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500524#endif
525
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500526#define CONFIG_IPADDR 192.168.1.253
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500527
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500528#define CONFIG_HOSTNAME unknown
529#define CONFIG_ROOTPATH /nfsroot
530#define CONFIG_BOOTFILE 8548cds/uImage.uboot
531#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500532
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500533#define CONFIG_SERVERIP 192.168.1.1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500534#define CONFIG_GATEWAYIP 192.168.1.1
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500535#define CONFIG_NETMASK 255.255.255.0
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500536
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500537#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500538
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500539#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
540#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500541
542#define CONFIG_BAUDRATE 115200
543
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500544#define CONFIG_EXTRA_ENV_SETTINGS \
545 "netdev=eth0\0" \
546 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
547 "tftpflash=tftpboot $loadaddr $uboot; " \
548 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
549 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
550 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
551 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
552 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
553 "consoledev=ttyS1\0" \
554 "ramdiskaddr=2000000\0" \
Andy Fleming6c543592007-08-13 14:38:06 -0500555 "ramdiskfile=ramdisk.uboot\0" \
Ed Swarthout4bf4abb2007-08-21 09:38:59 -0500556 "fdtaddr=c00000\0" \
Kumar Gala22abb2d2007-11-29 10:34:28 -0600557 "fdtfile=mpc8548cds.dtb\0"
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500558
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500559#define CONFIG_NFSBOOTCOMMAND \
560 "setenv bootargs root=/dev/nfs rw " \
561 "nfsroot=$serverip:$rootpath " \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500562 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500563 "console=$consoledev,$baudrate $othbootargs;" \
564 "tftp $loadaddr $bootfile;" \
Ed Swarthout4bf4abb2007-08-21 09:38:59 -0500565 "tftp $fdtaddr $fdtfile;" \
566 "bootm $loadaddr - $fdtaddr"
Andy Fleming8272dc22006-09-13 10:33:35 -0500567
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500568
569#define CONFIG_RAMBOOTCOMMAND \
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500570 "setenv bootargs root=/dev/ram rw " \
571 "console=$consoledev,$baudrate $othbootargs;" \
572 "tftp $ramdiskaddr $ramdiskfile;" \
573 "tftp $loadaddr $bootfile;" \
Ed Swarthout4bf4abb2007-08-21 09:38:59 -0500574 "tftp $fdtaddr $fdtfile;" \
575 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500576
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500577#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500578
579#endif /* __CONFIG_H */