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Jon Loeligerd9b94f22005-07-25 14:05:07 -05001/*
Kumar Gala8b47d7e2011-01-04 17:57:59 -06002 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
Jon Loeligerd9b94f22005-07-25 14:05:07 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050014 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Jon Loeligerd9b94f22005-07-25 14:05:07 -050015 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8548cds board configuration file
25 *
26 * Please refer to doc/README.mpc85xxcds for more info.
27 *
28 */
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
chenhui zhaob76aef62011-10-13 13:41:00 +080032#ifdef CONFIG_36BIT
33#define CONFIG_PHYS_64BIT
34#endif
35
Jon Loeligerd9b94f22005-07-25 14:05:07 -050036/* High Level Configuration Options */
37#define CONFIG_BOOKE 1 /* BOOKE */
38#define CONFIG_E500 1 /* BOOKE e500 family */
39#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
40#define CONFIG_MPC8548 1 /* MPC8548 specific */
41#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
42
Wolfgang Denk2ae18242010-10-06 09:05:45 +020043#ifndef CONFIG_SYS_TEXT_BASE
44#define CONFIG_SYS_TEXT_BASE 0xfff80000
45#endif
46
Kumar Gala8b47d7e2011-01-04 17:57:59 -060047#define CONFIG_SYS_SRIO
48#define CONFIG_SRIO1 /* SRIO port 1 */
49
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050050#define CONFIG_PCI /* enable any pci type devices */
51#define CONFIG_PCI1 /* PCI controller 1 */
52#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050053#undef CONFIG_PCI2
54#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Kumar Gala8ff3de62007-12-07 12:17:34 -060055#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050056#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050057
58#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050059#define CONFIG_ENV_OVERWRITE
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050060#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
Kumar Gala2cfaa1a2008-01-16 01:45:10 -060061#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050062
Jon Loeliger25eedb22008-03-19 15:02:07 -050063#define CONFIG_FSL_VIA
Jon Loeliger25eedb22008-03-19 15:02:07 -050064
Jon Loeligerd9b94f22005-07-25 14:05:07 -050065#ifndef __ASSEMBLY__
66extern unsigned long get_clock_freq(void);
67#endif
68#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
69
70/*
71 * These can be toggled for performance analysis, otherwise use default.
72 */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -050073#define CONFIG_L2_CACHE /* toggle L2 cache */
74#define CONFIG_BTB /* toggle branch predition */
Jon Loeligerd9b94f22005-07-25 14:05:07 -050075
76/*
77 * Only possible on E500 Version 2 or newer cores.
78 */
79#define CONFIG_ENABLE_36BIT_PHYS 1
80
chenhui zhaob76aef62011-10-13 13:41:00 +080081#ifdef CONFIG_PHYS_64BIT
82#define CONFIG_ADDR_MAP
83#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
84#endif
85
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
87#define CONFIG_SYS_MEMTEST_END 0x00400000
Jon Loeligerd9b94f22005-07-25 14:05:07 -050088
Timur Tabie46fedf2011-08-04 18:03:41 -050089#define CONFIG_SYS_CCSRBAR 0xe0000000
90#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Jon Loeligerd9b94f22005-07-25 14:05:07 -050091
Jon Loeligere31d2c12008-03-18 13:51:06 -050092/* DDR Setup */
93#define CONFIG_FSL_DDR2
94#undef CONFIG_FSL_DDR_INTERACTIVE
95#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
96#define CONFIG_DDR_SPD
Jon Loeligere31d2c12008-03-18 13:51:06 -050097
chenhui zhao867b06f2011-09-06 16:41:19 +000098#define CONFIG_DDR_ECC
Dave Liu9b0ad1b2008-10-28 17:53:38 +080099#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Jon Loeligere31d2c12008-03-18 13:51:06 -0500100#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
103#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500104
Jon Loeligere31d2c12008-03-18 13:51:06 -0500105#define CONFIG_NUM_DDR_CONTROLLERS 1
106#define CONFIG_DIMM_SLOTS_PER_CTLR 1
107#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500108
Jon Loeligere31d2c12008-03-18 13:51:06 -0500109/* I2C addresses of SPD EEPROMs */
110#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
111
112/* Make sure required options are set */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500113#ifndef CONFIG_SPD_EEPROM
114#error ("CONFIG_SPD_EEPROM is required")
115#endif
116
117#undef CONFIG_CLOCKS_IN_MHZ
chenhui zhaofff80972011-10-13 13:40:59 +0800118/*
119 * Physical Address Map
120 *
121 * 32bit:
122 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
123 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
124 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
125 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
126 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
127 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
128 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
129 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
130 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
131 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
132 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
133 *
chenhui zhaob76aef62011-10-13 13:41:00 +0800134 * 36bit:
135 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable
136 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
137 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
138 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
139 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
140 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
141 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
142 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
143 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
144 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
145 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
146 *
chenhui zhaofff80972011-10-13 13:40:59 +0800147 */
148
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500149
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500150/*
151 * Local Bus Definitions
152 */
153
154/*
155 * FLASH on the Local Bus
156 * Two banks, 8M each, using the CFI driver.
157 * Boot from BR0/OR0 bank at 0xff00_0000
158 * Alternate BR1/OR1 bank at 0xff80_0000
159 *
160 * BR0, BR1:
161 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
162 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
163 * Port Size = 16 bits = BRx[19:20] = 10
164 * Use GPCM = BRx[24:26] = 000
165 * Valid = BRx[31] = 1
166 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500167 * 0 4 8 12 16 20 24 28
168 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
169 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500170 *
171 * OR0, OR1:
172 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
173 * Reserved ORx[17:18] = 11, confusion here?
174 * CSNT = ORx[20] = 1
175 * ACS = half cycle delay = ORx[21:22] = 11
176 * SCY = 6 = ORx[24:27] = 0110
177 * TRLX = use relaxed timing = ORx[29] = 1
178 * EAD = use external address latch delay = OR[31] = 1
179 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500180 * 0 4 8 12 16 20 24 28
181 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500182 */
183
chenhui zhaofff80972011-10-13 13:40:59 +0800184#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
chenhui zhaob76aef62011-10-13 13:41:00 +0800185#ifdef CONFIG_PHYS_64BIT
186#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
187#else
chenhui zhaofff80972011-10-13 13:40:59 +0800188#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
chenhui zhaob76aef62011-10-13 13:41:00 +0800189#endif
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500190
chenhui zhaofff80972011-10-13 13:40:59 +0800191#define CONFIG_SYS_BR0_PRELIM \
192 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800000)) \
193 | BR_PS_16 | BR_V)
194#define CONFIG_SYS_BR1_PRELIM \
195 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_OR0_PRELIM 0xff806e65
198#define CONFIG_SYS_OR1_PRELIM 0xff806e65
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500199
chenhui zhaofff80972011-10-13 13:40:59 +0800200#define CONFIG_SYS_FLASH_BANKS_LIST \
201 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
203#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
204#undef CONFIG_SYS_FLASH_CHECKSUM
205#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
206#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500207
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200208#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500209
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200210#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_FLASH_CFI
212#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500213
chenhui zhao867b06f2011-09-06 16:41:19 +0000214#define CONFIG_HWCONFIG /* enable hwconfig */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500215
216/*
217 * SDRAM on the Local Bus
218 */
chenhui zhaofff80972011-10-13 13:40:59 +0800219#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
chenhui zhaob76aef62011-10-13 13:41:00 +0800220#ifdef CONFIG_PHYS_64BIT
221#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
222#else
chenhui zhaofff80972011-10-13 13:40:59 +0800223#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
chenhui zhaob76aef62011-10-13 13:41:00 +0800224#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500226
227/*
228 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500230 *
231 * For BR2, need:
232 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
233 * port-size = 32-bits = BR2[19:20] = 11
234 * no parity checking = BR2[21:22] = 00
235 * SDRAM for MSEL = BR2[24:26] = 011
236 * Valid = BR[31] = 1
237 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500238 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500239 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
240 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500242 * FIXME: the top 17 bits of BR2.
243 */
244
chenhui zhaofff80972011-10-13 13:40:59 +0800245#define CONFIG_SYS_BR2_PRELIM \
246 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
247 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500248
249/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500251 *
252 * For OR2, need:
253 * 64MB mask for AM, OR2[0:7] = 1111 1100
254 * XAM, OR2[17:18] = 11
255 * 9 columns OR2[19-21] = 010
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500256 * 13 rows OR2[23-25] = 100
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500257 * EAD set for extra time OR[31] = 1
258 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500259 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500260 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
261 */
262
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_OR2_PRELIM 0xfc006901
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500264
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
266#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
267#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
268#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500269
270/*
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500271 * Common settings for all Local Bus SDRAM commands.
272 * At run time, either BSMA1516 (for CPU 1.1)
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500273 * or BSMA1617 (for CPU 1.0) (old)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500274 * is OR'ed in too.
275 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500276#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
277 | LSDMR_PRETOACT7 \
278 | LSDMR_ACTTORW7 \
279 | LSDMR_BL8 \
280 | LSDMR_WRC4 \
281 | LSDMR_CL3 \
282 | LSDMR_RFEN \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500283 )
284
285/*
286 * The CADMUS registers are connected to CS3 on CDS.
287 * The new memory map places CADMUS at 0xf8000000.
288 *
289 * For BR3, need:
290 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
291 * port-size = 8-bits = BR[19:20] = 01
292 * no parity checking = BR[21:22] = 00
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500293 * GPMC for MSEL = BR[24:26] = 000
294 * Valid = BR[31] = 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500295 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500296 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500297 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
298 *
299 * For OR3, need:
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500300 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500301 * disable buffer ctrl OR[19] = 0
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500302 * CSNT OR[20] = 1
303 * ACS OR[21:22] = 11
304 * XACS OR[23] = 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500305 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500306 * SETA OR[28] = 0
307 * TRLX OR[29] = 1
308 * EHTR OR[30] = 1
309 * EAD extra time OR[31] = 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500310 *
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500311 * 0 4 8 12 16 20 24 28
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500312 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
313 */
314
Jon Loeliger25eedb22008-03-19 15:02:07 -0500315#define CONFIG_FSL_CADMUS
316
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500317#define CADMUS_BASE_ADDR 0xf8000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800318#ifdef CONFIG_PHYS_64BIT
319#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
320#else
chenhui zhaofff80972011-10-13 13:40:59 +0800321#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
chenhui zhaob76aef62011-10-13 13:41:00 +0800322#endif
chenhui zhaofff80972011-10-13 13:40:59 +0800323#define CONFIG_SYS_BR3_PRELIM \
324 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500326
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_INIT_RAM_LOCK 1
328#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200329#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500330
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200331#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500333
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
chenhui zhao867b06f2011-09-06 16:41:19 +0000335#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500336
337/* Serial Port */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500338#define CONFIG_CONS_INDEX 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_NS16550
340#define CONFIG_SYS_NS16550_SERIAL
341#define CONFIG_SYS_NS16550_REG_SIZE 1
342#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500345 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
346
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
348#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500349
350/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_HUSH_PARSER
352#ifdef CONFIG_SYS_HUSH_PARSER
353#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500354#endif
355
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500356/* pass open firmware flat tree */
Kumar Galab90d2542007-11-29 00:11:44 -0600357#define CONFIG_OF_LIBFDT 1
358#define CONFIG_OF_BOARD_SETUP 1
359#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock40d5fa32006-06-28 10:43:36 -0500360
Jon Loeliger20476722006-10-20 15:50:15 -0500361/*
362 * I2C
363 */
364#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
365#define CONFIG_HARD_I2C /* I2C with hardware support*/
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500366#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
368#define CONFIG_SYS_I2C_SLAVE 0x7F
369#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
370#define CONFIG_SYS_I2C_OFFSET 0x3000
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500371
Timur Tabie8d18542008-07-18 16:52:23 +0200372/* EEPROM */
373#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_I2C_EEPROM_CCID
375#define CONFIG_SYS_ID_EEPROM
376#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
377#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Timur Tabie8d18542008-07-18 16:52:23 +0200378
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500379/*
380 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300381 * Memory space is mapped 1-1, but I/O space must start from 0.
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500382 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600383#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800384#ifdef CONFIG_PHYS_64BIT
385#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
386#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
387#else
Kumar Gala10795f42008-12-02 16:08:36 -0600388#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600389#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800390#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600392#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600393#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800394#ifdef CONFIG_PHYS_64BIT
395#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
396#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800398#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500400
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500401#ifdef CONFIG_PCIE1
Kumar Galaf5fa8f32010-12-17 10:21:22 -0600402#define CONFIG_SYS_PCIE1_NAME "Slot"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600403#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800404#ifdef CONFIG_PHYS_64BIT
405#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
406#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
407#else
Kumar Gala10795f42008-12-02 16:08:36 -0600408#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600409#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800410#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600412#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600413#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800414#ifdef CONFIG_PHYS_64BIT
415#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
416#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800418#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500420#endif
Zang Roy-r6191141fb7e02006-12-14 14:14:55 +0800421
422/*
423 * RapidIO MMU
424 */
chenhui zhaofff80972011-10-13 13:40:59 +0800425#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800426#ifdef CONFIG_PHYS_64BIT
427#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
428#else
chenhui zhaofff80972011-10-13 13:40:59 +0800429#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
chenhui zhaob76aef62011-10-13 13:41:00 +0800430#endif
Kumar Gala8b47d7e2011-01-04 17:57:59 -0600431#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500432
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700433#ifdef CONFIG_LEGACY
434#define BRIDGE_ID 17
435#define VIA_ID 2
436#else
437#define BRIDGE_ID 28
438#define VIA_ID 4
439#endif
440
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500441#if defined(CONFIG_PCI)
442
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500443#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500444
445#undef CONFIG_EEPRO100
446#undef CONFIG_TULIP
chenhui zhao867b06f2011-09-06 16:41:19 +0000447#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500448
chenhui zhao867b06f2011-09-06 16:41:19 +0000449#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500450
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500451#endif /* CONFIG_PCI */
452
453
454#if defined(CONFIG_TSEC_ENET)
455
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500456#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500457#define CONFIG_TSEC1 1
458#define CONFIG_TSEC1_NAME "eTSEC0"
459#define CONFIG_TSEC2 1
460#define CONFIG_TSEC2_NAME "eTSEC1"
461#define CONFIG_TSEC3 1
462#define CONFIG_TSEC3_NAME "eTSEC2"
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500463#define CONFIG_TSEC4
Kim Phillips255a35772007-05-16 16:52:19 -0500464#define CONFIG_TSEC4_NAME "eTSEC3"
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500465#undef CONFIG_MPC85XX_FEC
466
chenhui zhaod3701222011-09-06 16:41:18 +0000467#define CONFIG_PHY_MARVELL
468
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500469#define TSEC1_PHY_ADDR 0
470#define TSEC2_PHY_ADDR 1
471#define TSEC3_PHY_ADDR 2
472#define TSEC4_PHY_ADDR 3
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500473
474#define TSEC1_PHYIDX 0
475#define TSEC2_PHYIDX 0
476#define TSEC3_PHYIDX 0
477#define TSEC4_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500478#define TSEC1_FLAGS TSEC_GIGABIT
479#define TSEC2_FLAGS TSEC_GIGABIT
480#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
481#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500482
483/* Options are: eTSEC[0-3] */
484#define CONFIG_ETHPRIME "eTSEC0"
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500485#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500486#endif /* CONFIG_TSEC_ENET */
487
488/*
489 * Environment
490 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200491#define CONFIG_ENV_IS_IN_FLASH 1
chenhui zhao867b06f2011-09-06 16:41:19 +0000492#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
493#define CONFIG_ENV_ADDR 0xfff80000
494#else
495#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
496#endif
497#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200498#define CONFIG_ENV_SIZE 0x2000
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500499
500#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500502
Jon Loeliger2835e512007-06-13 13:22:08 -0500503/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500504 * BOOTP options
505 */
506#define CONFIG_BOOTP_BOOTFILESIZE
507#define CONFIG_BOOTP_BOOTPATH
508#define CONFIG_BOOTP_GATEWAY
509#define CONFIG_BOOTP_HOSTNAME
510
511
512/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500513 * Command line configuration.
514 */
515#include <config_cmd_default.h>
516
517#define CONFIG_CMD_PING
518#define CONFIG_CMD_I2C
519#define CONFIG_CMD_MII
Kumar Gala82ac8c92007-12-07 12:04:30 -0600520#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500521#define CONFIG_CMD_IRQ
522#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500523#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500524
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500525#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500526 #define CONFIG_CMD_PCI
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500527#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500528
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500529
530#undef CONFIG_WATCHDOG /* watchdog disabled */
531
532/*
533 * Miscellaneous configurable options
534 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200535#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500536#define CONFIG_CMDLINE_EDITING /* Command-line editing */
537#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200538#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
539#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500540#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200541#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500542#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200543#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500544#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200545#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
546#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
547#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
548#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500549
550/*
551 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500552 * have to be in the first 64 MB of memory, since this is
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500553 * the maximum mapped by the Linux kernel during initialization.
554 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500555#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
556#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500557
Jon Loeliger2835e512007-06-13 13:22:08 -0500558#if defined(CONFIG_CMD_KGDB)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500559#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
560#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
561#endif
562
563/*
564 * Environment Configuration
565 */
566
567/* The mac addresses for all ethernet interface */
568#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500569#define CONFIG_HAS_ETH0
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500570#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500571#define CONFIG_HAS_ETH1
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500572#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500573#define CONFIG_HAS_ETH2
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500574#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
Andy Fleming09f3e092006-09-13 10:34:18 -0500575#define CONFIG_HAS_ETH3
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500576#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500577#endif
578
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500579#define CONFIG_IPADDR 192.168.1.253
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500580
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500581#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000582#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000583#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500584#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500585
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500586#define CONFIG_SERVERIP 192.168.1.1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500587#define CONFIG_GATEWAYIP 192.168.1.1
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500588#define CONFIG_NETMASK 255.255.255.0
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500589
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500590#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500591
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500592#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
593#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500594
595#define CONFIG_BAUDRATE 115200
596
chenhui zhao867b06f2011-09-06 16:41:19 +0000597#define CONFIG_EXTRA_ENV_SETTINGS \
598 "hwconfig=fsl_ddr:ecc=off\0" \
599 "netdev=eth0\0" \
600 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
601 "tftpflash=tftpboot $loadaddr $uboot; " \
602 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
603 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
604 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
605 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
606 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
607 "consoledev=ttyS1\0" \
608 "ramdiskaddr=2000000\0" \
609 "ramdiskfile=ramdisk.uboot\0" \
610 "fdtaddr=c00000\0" \
611 "fdtfile=mpc8548cds.dtb\0"
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500612
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500613#define CONFIG_NFSBOOTCOMMAND \
614 "setenv bootargs root=/dev/nfs rw " \
615 "nfsroot=$serverip:$rootpath " \
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500616 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500617 "console=$consoledev,$baudrate $othbootargs;" \
618 "tftp $loadaddr $bootfile;" \
Ed Swarthout4bf4abb2007-08-21 09:38:59 -0500619 "tftp $fdtaddr $fdtfile;" \
620 "bootm $loadaddr - $fdtaddr"
Andy Fleming8272dc22006-09-13 10:33:35 -0500621
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500622
623#define CONFIG_RAMBOOTCOMMAND \
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500624 "setenv bootargs root=/dev/ram rw " \
625 "console=$consoledev,$baudrate $othbootargs;" \
626 "tftp $ramdiskaddr $ramdiskfile;" \
627 "tftp $loadaddr $bootfile;" \
Ed Swarthout4bf4abb2007-08-21 09:38:59 -0500628 "tftp $fdtaddr $fdtfile;" \
629 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500630
Ed Swarthoutf2cff6b2007-07-27 01:50:52 -0500631#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500632
633#endif /* __CONFIG_H */