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Andre Schwarz5e0de0e2008-07-09 18:30:44 +02001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004-2008
6 * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30#include <version.h>
31
32#define CONFIG_MPC5xxx 1
33#define CONFIG_MPC5200 1
34
Wolfgang Denk2ae18242010-10-06 09:05:45 +020035#ifndef CONFIG_SYS_TEXT_BASE
36#define CONFIG_SYS_TEXT_BASE 0xFF800000
37#endif
38
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020040
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020041#define CONFIG_MISC_INIT_R 1
42
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_CACHELINE_SIZE 32
Wolfgang Denk17e900b2008-08-12 14:54:04 +020044#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_CACHELINE_SHIFT 5
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020046#endif
47
48#define CONFIG_PSC_CONSOLE 1
49#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020051
52#define CONFIG_PCI 1
53#define CONFIG_PCI_PNP 1
54#undef CONFIG_PCI_SCAN_SHOW
55#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
56
57#define CONFIG_PCI_MEM_BUS 0x40000000
58#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
59#define CONFIG_PCI_MEM_SIZE 0x10000000
60
61#define CONFIG_PCI_IO_BUS 0x50000000
62#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
63#define CONFIG_PCI_IO_SIZE 0x01000000
64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_XLB_PIPELINING 1
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020066#define CONFIG_HIGH_BATS 1
67
68#define MV_CI mvBlueCOUGAR-P
69#define MV_VCI mvBlueCOUGAR-P
70#define MV_FPGA_DATA 0xff860000
André Schwarz28887d82009-08-27 14:48:35 +020071#define MV_FPGA_SIZE 0
André Schwarze3b39f82009-07-17 14:50:24 +020072#define MV_KERNEL_ADDR 0xffd00000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020073#define MV_INITRD_ADDR 0xff900000
André Schwarze3b39f82009-07-17 14:50:24 +020074#define MV_INITRD_LENGTH 0x00400000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020075#define MV_SCRATCH_ADDR 0x00000000
76#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
Peter Tyser3202d332009-09-16 21:38:10 -050077#define MV_SCRIPT_ADDR 0xff840000
78#define MV_SCRIPT_ADDR2 0xff850000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +020079#define MV_DTB_ADDR 0xfffc0000
80
81#define CONFIG_SHOW_BOOT_PROGRESS 1
82
83#define MV_KERNEL_ADDR_RAM 0x00100000
84#define MV_DTB_ADDR_RAM 0x00600000
85#define MV_INITRD_ADDR_RAM 0x01000000
86
87/* pass open firmware flat tree */
88#define CONFIG_OF_LIBFDT 1
89#define CONFIG_OF_BOARD_SETUP 1
90
91#define OF_CPU "PowerPC,5200@0"
92#define OF_SOC "soc5200@f0000000"
93#define OF_TBCLK (bd->bi_busfreq / 4)
94#define MV_DTB_NAME mvbc-p.dtb
95#define CONFIG_OF_STDOUT_VIA_ALIAS 1
96
97/*
98 * Supported commands
99 */
100#include <config_cmd_default.h>
101
102#define CONFIG_CMD_CACHE
103#define CONFIG_CMD_NET
104#define CONFIG_CMD_PING
105#define CONFIG_CMD_DHCP
106#define CONFIG_CMD_SDRAM
107#define CONFIG_CMD_PCI
108#define CONFIG_CMD_FPGA
André Schwarze3b39f82009-07-17 14:50:24 +0200109#define CONFIG_CMD_I2C
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200110
111#undef CONFIG_WATCHDOG
112
113#define CONFIG_BOOTP_VENDOREX
114#define CONFIG_BOOTP_SUBNETMASK
115#define CONFIG_BOOTP_GATEWAY
116#define CONFIG_BOOTP_DNS
117#define CONFIG_BOOTP_DNS2
118#define CONFIG_BOOTP_HOSTNAME
119#define CONFIG_BOOTP_BOOTFILESIZE
120#define CONFIG_BOOTP_BOOTPATH
121#define CONFIG_BOOTP_NTPSERVER
122#define CONFIG_BOOTP_RANDOM_DELAY
123#define CONFIG_BOOTP_SEND_HOSTNAME
124
125/*
126 * Autoboot
127 */
128#define CONFIG_BOOTDELAY 2
129#define CONFIG_AUTOBOOT_KEYED
130#define CONFIG_AUTOBOOT_STOP_STR "s"
131#define CONFIG_ZERO_BOOTDELAY_CHECK
132#define CONFIG_RESET_TO_RETRY 1000
133
Peter Tyser3202d332009-09-16 21:38:10 -0500134#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
135 then source ${script_addr}; \
136 else source ${script_addr2}; \
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200137 fi;"
138
139#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
140#define CONFIG_ENV_OVERWRITE
141
142#define XMK_STR(x) #x
143#define MK_STR(x) XMK_STR(x)
144
145#define CONFIG_EXTRA_ENV_SETTINGS \
146 "console_nr=0\0" \
147 "console=yes\0" \
148 "stdin=serial\0" \
149 "stdout=serial\0" \
150 "stderr=serial\0" \
151 "fpga=0\0" \
152 "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
153 "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
Peter Tyser3202d332009-09-16 21:38:10 -0500154 "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
155 "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200156 "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
157 "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
158 "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
159 "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
160 "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
161 "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
162 "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
163 "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
164 "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
165 "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
166 "mv_version=" U_BOOT_VERSION "\0" \
167 "dhcp_client_id=" MK_STR(MV_CI) "\0" \
168 "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
169 "netretry=no\0" \
170 "use_static_ipaddr=no\0" \
171 "static_ipaddr=192.168.90.10\0" \
172 "static_netmask=255.255.255.0\0" \
173 "static_gateway=0.0.0.0\0" \
174 "initrd_name=uInitrd.mvbc-p-rfs\0" \
175 "zcip=no\0" \
176 "netboot=yes\0" \
177 "mvtest=Ff\0" \
178 "tried_bootfromflash=no\0" \
179 "tried_bootfromnet=no\0" \
180 "use_dhcp=yes\0" \
181 "gev_start=yes\0" \
182 "mvbcdma_debug=0\0" \
183 "mvbcia_debug=0\0" \
184 "propdev_debug=0\0" \
185 "gevss_debug=0\0" \
186 "watchdog=1\0" \
André Schwarze3b39f82009-07-17 14:50:24 +0200187 "sensor_cnt=1\0" \
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200188 ""
189
190#undef XMK_STR
191#undef MK_STR
192
193/*
194 * IPB Bus clocking configuration.
195 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
197#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200198
199/*
200 * Flash configuration
201 */
202#undef CONFIG_FLASH_16BIT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200204#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
206#define CONFIG_SYS_FLASH_EMPTY_INFO
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200207
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
209#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_MAX_FLASH_BANKS 1
212#define CONFIG_SYS_MAX_FLASH_SECT 256
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_LOWBOOT
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200215#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_FLASH_SIZE 0x00800000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200217
218/*
219 * Environment settings
220 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200221#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#undef CONFIG_SYS_FLASH_PROTECTION
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200223
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200224#define CONFIG_ENV_ADDR 0xFFFE0000
225#define CONFIG_ENV_SIZE 0x10000
226#define CONFIG_ENV_SECT_SIZE 0x10000
227#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
228#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200229
230/*
231 * Memory map
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_MBAR 0xF0000000
234#define CONFIG_SYS_SDRAM_BASE 0x00000000
235#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200238#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200239
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200240#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200242
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200243#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
245#define CONFIG_SYS_RAMBOOT 1
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200246#endif
247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
249#define CONFIG_SYS_MONITOR_LEN (512 << 10)
250#define CONFIG_SYS_MALLOC_LEN (512 << 10)
251#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200252
253/*
André Schwarze3b39f82009-07-17 14:50:24 +0200254 * I2C configuration
255 */
256#define CONFIG_HARD_I2C 1
257#define CONFIG_SYS_I2C_MODULE 1
258#define CONFIG_SYS_I2C_SPEED 86000
259#define CONFIG_SYS_I2C_SLAVE 0x7F
260
261/*
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200262 * Ethernet configuration
263 */
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200264#define CONFIG_NET_RETRY_COUNT 5
265
266#define CONFIG_E1000
Wolfgang Denkc4ec6db2008-07-31 13:57:20 +0200267#define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200268#undef CONFIG_MPC5xxx_FEC
269#undef CONFIG_PHY_ADDR
270#define CONFIG_NETDEV eth0
271
272/*
273 * Miscellaneous configurable options
274 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_HUSH_PARSER
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200276#define CONFIG_CMDLINE_EDITING
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
278#undef CONFIG_SYS_LONGHELP
279#define CONFIG_SYS_PROMPT "=> "
Wolfgang Denk17e900b2008-08-12 14:54:04 +0200280#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_CBSIZE 1024
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200282#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_CBSIZE 256
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200284#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
286#define CONFIG_SYS_MAXARGS 16
287#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_MEMTEST_START 0x00800000
290#define CONFIG_SYS_MEMTEST_END 0x02f00000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200291
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_HZ 1000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200293
294/* default load address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_LOAD_ADDR 0x02000000
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200296/* default location for tftp and bootm */
297#define CONFIG_LOADADDR 0x00200000
298
299/*
300 * Various low-level settings
301 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
305#define CONFIG_SYS_HID0_FINAL HID0_ICE
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200306
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
308#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
309#define CONFIG_SYS_BOOTCS_CFG 0x00047800
310#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
311#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_CS_BURST 0x000000f0
314#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200315
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_RESET_ADDRESS 0x00000100
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200317
318#undef FPGA_DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
320#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
Andre Schwarz5e0de0e2008-07-09 18:30:44 +0200321#define CONFIG_FPGA_ALTERA 1
322#define CONFIG_FPGA_CYCLON2 1
323#define CONFIG_FPGA_COUNT 1
324
325#endif