blob: 7b7b8675215e60c893f93eff8c8ec623cb23d529 [file] [log] [blame]
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +02001#ifndef __ASM_ARM_SYSTEM_H
2#define __ASM_ARM_SYSTEM_H
3
Sergey Temerkhanova5b9fa32015-10-14 09:55:46 -07004#include <common.h>
5#include <linux/compiler.h>
Tom Rinia78cd862016-08-01 18:54:53 -04006#include <asm/barriers.h>
Sergey Temerkhanova5b9fa32015-10-14 09:55:46 -07007
David Feng0ae76532013-12-14 11:47:35 +08008#ifdef CONFIG_ARM64
9
10/*
11 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
12 */
13#define CR_M (1 << 0) /* MMU enable */
14#define CR_A (1 << 1) /* Alignment abort enable */
15#define CR_C (1 << 2) /* Dcache enable */
16#define CR_SA (1 << 3) /* Stack Alignment Check Enable */
17#define CR_I (1 << 12) /* Icache enable */
18#define CR_WXN (1 << 19) /* Write Permision Imply XN */
19#define CR_EE (1 << 25) /* Exception (Big) Endian */
20
Alexander Graf7985cdf2016-03-04 01:09:54 +010021#ifndef __ASSEMBLY__
22
23u64 get_page_table_size(void);
24#define PGTABLE_SIZE get_page_table_size()
25
Siva Durga Prasad Paladugudad17fd2015-06-26 18:05:07 +053026/* 2MB granularity */
27#define MMU_SECTION_SHIFT 21
Stephen Warren88f965d2015-10-05 12:08:59 -060028#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
David Feng0ae76532013-12-14 11:47:35 +080029
Alexander Graf53eb45e2016-03-16 15:41:20 +010030/* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */
Siva Durga Prasad Paladugudad17fd2015-06-26 18:05:07 +053031enum dcache_option {
Alexander Graf53eb45e2016-03-16 15:41:20 +010032 DCACHE_OFF = 0 << 2,
33 DCACHE_WRITETHROUGH = 3 << 2,
34 DCACHE_WRITEBACK = 4 << 2,
35 DCACHE_WRITEALLOC = 4 << 2,
Siva Durga Prasad Paladugudad17fd2015-06-26 18:05:07 +053036};
37
David Feng0ae76532013-12-14 11:47:35 +080038#define wfi() \
39 ({asm volatile( \
40 "wfi" : : : "memory"); \
41 })
42
43static inline unsigned int current_el(void)
44{
45 unsigned int el;
46 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
47 return el >> 2;
48}
49
50static inline unsigned int get_sctlr(void)
51{
52 unsigned int el, val;
53
54 el = current_el();
55 if (el == 1)
56 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
57 else if (el == 2)
58 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
59 else
60 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
61
62 return val;
63}
64
65static inline void set_sctlr(unsigned int val)
66{
67 unsigned int el;
68
69 el = current_el();
70 if (el == 1)
71 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
72 else if (el == 2)
73 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
74 else
75 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
76
77 asm volatile("isb");
78}
79
Sergey Temerkhanovba5648c2015-10-14 09:55:44 -070080static inline unsigned long read_mpidr(void)
81{
82 unsigned long val;
83
84 asm volatile("mrs %0, mpidr_el1" : "=r" (val));
85
86 return val;
87}
88
89#define BSP_COREID 0
90
David Feng0ae76532013-12-14 11:47:35 +080091void __asm_flush_dcache_all(void);
York Sun1e6ad552014-02-26 13:26:04 -080092void __asm_invalidate_dcache_all(void);
David Feng0ae76532013-12-14 11:47:35 +080093void __asm_flush_dcache_range(u64 start, u64 end);
94void __asm_invalidate_tlb_all(void);
95void __asm_invalidate_icache_all(void);
York Sundcd468b2015-01-06 13:18:42 -080096int __asm_flush_l3_cache(void);
Alexander Graf5e2ec772016-03-04 01:09:47 +010097void __asm_switch_ttbr(u64 new_ttbr);
David Feng0ae76532013-12-14 11:47:35 +080098
99void armv8_switch_to_el2(void);
100void armv8_switch_to_el1(void);
101void gic_init(void);
102void gic_send_sgi(unsigned long sgino);
103void wait_for_wakeup(void);
Ian Campbell73169872015-04-21 07:18:36 +0200104void protect_secure_region(void);
David Feng0ae76532013-12-14 11:47:35 +0800105void smp_kick_all_cpus(void);
106
York Sun2f78eae2014-06-23 15:15:54 -0700107void flush_l3_cache(void);
108
Sergey Temerkhanova5b9fa32015-10-14 09:55:46 -0700109/*
110 *Issue a hypervisor call in accordance with ARM "SMC Calling convention",
111 * DEN0028A
112 *
113 * @args: input and output arguments
114 *
115 */
116void hvc_call(struct pt_regs *args);
117
118/*
119 *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
120 * DEN0028A
121 *
122 * @args: input and output arguments
123 *
124 */
125void smc_call(struct pt_regs *args);
126
Beniamino Galvani5a07abb2016-05-08 08:30:14 +0200127void __noreturn psci_system_reset(bool smc);
128
David Feng0ae76532013-12-14 11:47:35 +0800129#endif /* __ASSEMBLY__ */
130
131#else /* CONFIG_ARM64 */
132
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +0200133#ifdef __KERNEL__
134
135#define CPU_ARCH_UNKNOWN 0
136#define CPU_ARCH_ARMv3 1
137#define CPU_ARCH_ARMv4 2
138#define CPU_ARCH_ARMv4T 3
139#define CPU_ARCH_ARMv5 4
140#define CPU_ARCH_ARMv5T 5
141#define CPU_ARCH_ARMv5TE 6
142#define CPU_ARCH_ARMv5TEJ 7
143#define CPU_ARCH_ARMv6 8
144#define CPU_ARCH_ARMv7 9
145
146/*
147 * CR1 bits (CP#15 CR1)
148 */
149#define CR_M (1 << 0) /* MMU enable */
150#define CR_A (1 << 1) /* Alignment abort enable */
151#define CR_C (1 << 2) /* Dcache enable */
152#define CR_W (1 << 3) /* Write buffer enable */
153#define CR_P (1 << 4) /* 32-bit exception handler */
154#define CR_D (1 << 5) /* 32-bit data address range */
155#define CR_L (1 << 6) /* Implementation defined */
156#define CR_B (1 << 7) /* Big endian */
157#define CR_S (1 << 8) /* System MMU protection */
158#define CR_R (1 << 9) /* ROM MMU protection */
159#define CR_F (1 << 10) /* Implementation defined */
160#define CR_Z (1 << 11) /* Implementation defined */
161#define CR_I (1 << 12) /* Icache enable */
162#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
163#define CR_RR (1 << 14) /* Round Robin cache replacement */
164#define CR_L4 (1 << 15) /* LDR pc can set T bit */
165#define CR_DT (1 << 16)
166#define CR_IT (1 << 18)
167#define CR_ST (1 << 19)
168#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
169#define CR_U (1 << 22) /* Unaligned access operation */
170#define CR_XP (1 << 23) /* Extended page tables */
171#define CR_VE (1 << 24) /* Vectored interrupts */
172#define CR_EE (1 << 25) /* Exception (Big) Endian */
173#define CR_TRE (1 << 28) /* TEX remap enable */
174#define CR_AFE (1 << 29) /* Access flag enable */
175#define CR_TE (1 << 30) /* Thumb exception enable */
176
Alexander Grafd990f5c2016-03-16 15:41:21 +0100177#if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
178#define PGTABLE_SIZE (4096 * 5)
179#elif !defined(PGTABLE_SIZE)
David Feng0ae76532013-12-14 11:47:35 +0800180#define PGTABLE_SIZE (4096 * 4)
Sergey Temerkhanov94f7ff32015-10-14 09:55:45 -0700181#endif
David Feng0ae76532013-12-14 11:47:35 +0800182
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +0200183/*
184 * This is used to ensure the compiler did actually allocate the register we
185 * asked it for some inline assembly sequences. Apparently we can't trust
186 * the compiler from one version to another so a bit of paranoia won't hurt.
187 * This string is meant to be concatenated with the inline asm string and
188 * will cause compilation to stop on mismatch.
189 * (for details, see gcc PR 15089)
190 */
191#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
192
193#ifndef __ASSEMBLY__
194
Simon Glasse11c6c22015-02-07 10:47:28 -0700195/**
196 * save_boot_params() - Save boot parameters before starting reset sequence
197 *
198 * If you provide this function it will be called immediately U-Boot starts,
199 * both for SPL and U-Boot proper.
200 *
201 * All registers are unchanged from U-Boot entry. No registers need be
202 * preserved.
203 *
204 * This is not a normal C function. There is no stack. Return by branching to
205 * save_boot_params_ret.
206 *
207 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
208 */
209
Simon Glass55199122015-05-04 11:31:03 -0600210/**
211 * save_boot_params_ret() - Return from save_boot_params()
212 *
213 * If you provide save_boot_params(), then you should jump back to this
214 * function when done. Try to preserve all registers.
215 *
216 * If your implementation of save_boot_params() is in C then it is acceptable
217 * to simply call save_boot_params_ret() at the end of your function. Since
218 * there is no link register set up, you cannot just exit the function. U-Boot
219 * will return to the (initialised) value of lr, and likely crash/hang.
220 *
221 * If your implementation of save_boot_params() is in assembler then you
222 * should use 'b' or 'bx' to return to save_boot_params_ret.
223 */
224void save_boot_params_ret(void);
225
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +0200226#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
227
Rob Herring2ff467c2012-12-02 17:06:21 +0000228#ifdef __ARM_ARCH_7A__
229#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
230#else
231#define wfi()
232#endif
233
Alexander Grafd990f5c2016-03-16 15:41:21 +0100234static inline unsigned long get_cpsr(void)
235{
236 unsigned long cpsr;
237
238 asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
239 return cpsr;
240}
241
242static inline int is_hyp(void)
243{
244#ifdef CONFIG_ARMV7_LPAE
245 /* HYP mode requires LPAE ... */
246 return ((get_cpsr() & 0x1f) == 0x1a);
247#else
248 /* ... so without LPAE support we can optimize all hyp code away */
249 return 0;
250#endif
251}
252
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +0200253static inline unsigned int get_cr(void)
254{
255 unsigned int val;
Alexander Grafd990f5c2016-03-16 15:41:21 +0100256
257 if (is_hyp())
258 asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
259 :
260 : "cc");
261 else
262 asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
263 :
264 : "cc");
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +0200265 return val;
266}
267
268static inline void set_cr(unsigned int val)
269{
Alexander Grafd990f5c2016-03-16 15:41:21 +0100270 if (is_hyp())
271 asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
272 : "r" (val)
273 : "cc");
274 else
275 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
276 : "r" (val)
277 : "cc");
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +0200278 isb();
279}
280
R Sricharande63ac22013-03-04 20:04:45 +0000281static inline unsigned int get_dacr(void)
282{
283 unsigned int val;
284 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
285 return val;
286}
287
288static inline void set_dacr(unsigned int val)
289{
290 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
291 : : "r" (val) : "cc");
292 isb();
293}
294
Alexander Grafd990f5c2016-03-16 15:41:21 +0100295#ifdef CONFIG_ARMV7_LPAE
296/* Long-Descriptor Translation Table Level 1/2 Bits */
297#define TTB_SECT_XN_MASK (1ULL << 54)
298#define TTB_SECT_NG_MASK (1 << 11)
299#define TTB_SECT_AF (1 << 10)
300#define TTB_SECT_SH_MASK (3 << 8)
301#define TTB_SECT_NS_MASK (1 << 5)
302#define TTB_SECT_AP (1 << 6)
303/* Note: TTB AP bits are set elsewhere */
304#define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */
305#define TTB_SECT (1 << 0)
306#define TTB_PAGETABLE (3 << 0)
307
308/* TTBCR flags */
309#define TTBCR_EAE (1 << 31)
310#define TTBCR_T0SZ(x) ((x) << 0)
311#define TTBCR_T1SZ(x) ((x) << 16)
312#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
313#define TTBCR_IRGN0_NC (0 << 8)
314#define TTBCR_IRGN0_WBWA (1 << 8)
315#define TTBCR_IRGN0_WT (2 << 8)
316#define TTBCR_IRGN0_WBNWA (3 << 8)
317#define TTBCR_IRGN0_MASK (3 << 8)
318#define TTBCR_ORGN0_NC (0 << 10)
319#define TTBCR_ORGN0_WBWA (1 << 10)
320#define TTBCR_ORGN0_WT (2 << 10)
321#define TTBCR_ORGN0_WBNWA (3 << 10)
322#define TTBCR_ORGN0_MASK (3 << 10)
323#define TTBCR_SHARED_NON (0 << 12)
324#define TTBCR_SHARED_OUTER (2 << 12)
325#define TTBCR_SHARED_INNER (3 << 12)
326#define TTBCR_EPD0 (0 << 7)
327
328/*
329 * Memory types
330 */
331#define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \
332 (0xcc << (2 * 8)) | (0xff << (3 * 8)))
333
334/* options available for data cache on each page */
335enum dcache_option {
336 DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0),
337 DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
338 DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
339 DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
340};
341#elif defined(CONFIG_CPU_V7)
Bryan Brinsko97840b52015-03-24 11:25:12 -0500342/* Short-Descriptor Translation Table Level 1 Bits */
343#define TTB_SECT_NS_MASK (1 << 19)
344#define TTB_SECT_NG_MASK (1 << 17)
345#define TTB_SECT_S_MASK (1 << 16)
346/* Note: TTB AP bits are set elsewhere */
Alexander Grafd990f5c2016-03-16 15:41:21 +0100347#define TTB_SECT_AP (3 << 10)
Bryan Brinsko97840b52015-03-24 11:25:12 -0500348#define TTB_SECT_TEX(x) ((x & 0x7) << 12)
349#define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
350#define TTB_SECT_XN_MASK (1 << 4)
351#define TTB_SECT_C_MASK (1 << 3)
352#define TTB_SECT_B_MASK (1 << 2)
353#define TTB_SECT (2 << 0)
354
355/* options available for data cache on each page */
356enum dcache_option {
Marek Vasut8890c2f2015-12-29 19:44:02 +0100357 DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
Bryan Brinsko97840b52015-03-24 11:25:12 -0500358 DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
359 DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
360 DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
361};
362#else
Alexander Grafd990f5c2016-03-16 15:41:21 +0100363#define TTB_SECT_AP (3 << 10)
Simon Glass0dde7f52012-10-17 13:24:53 +0000364/* options available for data cache on each page */
365enum dcache_option {
366 DCACHE_OFF = 0x12,
367 DCACHE_WRITETHROUGH = 0x1a,
368 DCACHE_WRITEBACK = 0x1e,
Marek Vasutff7e9702014-09-15 02:44:36 +0200369 DCACHE_WRITEALLOC = 0x16,
Simon Glass0dde7f52012-10-17 13:24:53 +0000370};
Bryan Brinsko97840b52015-03-24 11:25:12 -0500371#endif
Simon Glass0dde7f52012-10-17 13:24:53 +0000372
373/* Size of an MMU section */
374enum {
Alexander Grafd990f5c2016-03-16 15:41:21 +0100375#ifdef CONFIG_ARMV7_LPAE
376 MMU_SECTION_SHIFT = 21, /* 2MB */
377#else
378 MMU_SECTION_SHIFT = 20, /* 1MB */
379#endif
Simon Glass0dde7f52012-10-17 13:24:53 +0000380 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
381};
382
Marek Vasuta592e6f2015-12-29 19:44:01 +0100383#ifdef CONFIG_CPU_V7
Bryan Brinsko97840b52015-03-24 11:25:12 -0500384/* TTBR0 bits */
385#define TTBR0_BASE_ADDR_MASK 0xFFFFC000
386#define TTBR0_RGN_NC (0 << 3)
387#define TTBR0_RGN_WBWA (1 << 3)
388#define TTBR0_RGN_WT (2 << 3)
389#define TTBR0_RGN_WB (3 << 3)
390/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
391#define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
392#define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
393#define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
394#define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
395#endif
396
Simon Glass0dde7f52012-10-17 13:24:53 +0000397/**
Simon Glass0dde7f52012-10-17 13:24:53 +0000398 * Register an update to the page tables, and flush the TLB
399 *
400 * \param start start address of update in page table
401 * \param stop stop address of update in page table
402 */
403void mmu_page_table_flush(unsigned long start, unsigned long stop);
404
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +0200405#endif /* __ASSEMBLY__ */
406
407#define arch_align_stack(x) (x)
408
409#endif /* __KERNEL__ */
410
David Feng0ae76532013-12-14 11:47:35 +0800411#endif /* CONFIG_ARM64 */
412
Siva Durga Prasad Paladugudad17fd2015-06-26 18:05:07 +0530413#ifndef __ASSEMBLY__
414/**
415 * Change the cache settings for a region.
416 *
417 * \param start start address of memory region to change
418 * \param size size of memory region to change
419 * \param option dcache option to select
420 */
421void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
422 enum dcache_option option);
423
Stephen Warren88f965d2015-10-05 12:08:59 -0600424#ifdef CONFIG_SYS_NONCACHED_MEMORY
425void noncached_init(void);
426phys_addr_t noncached_alloc(size_t size, size_t align);
427#endif /* CONFIG_SYS_NONCACHED_MEMORY */
428
Siva Durga Prasad Paladugudad17fd2015-06-26 18:05:07 +0530429#endif /* __ASSEMBLY__ */
430
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +0200431#endif