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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ilya Yanok5fb17032010-07-07 20:16:13 +04002/*
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
Ilya Yanok5fb17032010-07-07 20:16:13 +04005 */
6
7#include <common.h>
8#include <hwconfig.h>
9#include <i2c.h>
Simon Glass2cf431c2019-11-14 12:57:47 -070010#include <init.h>
Ira W. Snyderea1ea542012-09-12 14:17:32 -070011#include <spi.h>
Masahiro Yamadab08c8c42018-03-05 01:20:11 +090012#include <linux/libfdt.h>
Ilya Yanok5fb17032010-07-07 20:16:13 +040013#include <fdt_support.h>
14#include <pci.h>
15#include <mpc83xx.h>
16#include <vsc7385.h>
17#include <netdev.h>
Ira W. Snyderdb1fc7d2012-09-12 14:17:35 -070018#include <fsl_esdhc.h>
Ilya Yanok5fb17032010-07-07 20:16:13 +040019#include <asm/io.h>
20#include <asm/fsl_serdes.h>
21#include <asm/fsl_mpc83xx_serdes.h>
22
Ira W. Snyderea1ea542012-09-12 14:17:32 -070023/*
24 * The following are used to control the SPI chip selects for the SPI command.
25 */
26#ifdef CONFIG_MPC8XXX_SPI
27
28#define SPI_CS_MASK 0x00400000
29
30int spi_cs_is_valid(unsigned int bus, unsigned int cs)
31{
32 return bus == 0 && cs == 0;
33}
34
35void spi_cs_activate(struct spi_slave *slave)
36{
37 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
38
39 /* active low */
40 clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
41}
42
43void spi_cs_deactivate(struct spi_slave *slave)
44{
45 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
46
47 /* inactive high */
48 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
49}
50#endif /* CONFIG_MPC8XXX_SPI */
51
Ira W. Snyderdb1fc7d2012-09-12 14:17:35 -070052#ifdef CONFIG_FSL_ESDHC
53int board_mmc_init(bd_t *bd)
54{
55 return fsl_esdhc_mmc_init(bd);
56}
57#endif
58
Ilya Yanok5fb17032010-07-07 20:16:13 +040059static u8 read_board_info(void)
60{
61 u8 val8;
62 i2c_set_bus_num(0);
63
64 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
65 return val8;
66 else
67 return 0;
68}
69
70int checkboard(void)
71{
72 static const char * const rev_str[] = {
73 "1.0",
74 "<reserved>",
75 "<reserved>",
76 "<reserved>",
77 "<unknown>",
78 };
79 u8 info;
80 int i;
81
82 info = read_board_info();
83 i = (!info) ? 4 : info & 0x03;
84
85 printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
86
87 return 0;
88}
89
90static struct pci_region pcie_regions_0[] = {
91 {
92 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
93 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
94 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
95 .flags = PCI_REGION_MEM,
96 },
97 {
98 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
99 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
100 .size = CONFIG_SYS_PCIE1_IO_SIZE,
101 .flags = PCI_REGION_IO,
102 },
103};
104
105void pci_init_board(void)
106{
107 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
108 sysconf83xx_t *sysconf = &immr->sysconf;
Ilya Yanok5fb17032010-07-07 20:16:13 +0400109 law83xx_t *pcie_law = sysconf->pcielaw;
110 struct pci_region *pcie_reg[] = { pcie_regions_0 };
111
112 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
113 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
114
Ilya Yanok5fb17032010-07-07 20:16:13 +0400115 /* Deassert the resets in the control register */
116 out_be32(&sysconf->pecr1, 0xE0008000);
117 udelay(2000);
118
119 /* Configure PCI Express Local Access Windows */
120 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
121 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
122
Peter Tyser6aa3d3b2010-09-14 19:13:50 -0500123 mpc83xx_pcie_init(1, pcie_reg);
Ilya Yanok5fb17032010-07-07 20:16:13 +0400124}
125/*
126 * Miscellaneous late-boot configurations
127 *
128 * If a VSC7385 microcode image is present, then upload it.
129*/
130int misc_init_r(void)
131{
Ira W. Snyderea1ea542012-09-12 14:17:32 -0700132#ifdef CONFIG_MPC8XXX_SPI
133 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
134 sysconf83xx_t *sysconf = &immr->sysconf;
135
136 /*
137 * Set proper bits in SICRH to allow SPI on header J8
138 *
139 * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
140 * switch. The pinmux configuration does not have a fine enough
141 * granularity to support both simultaneously.
142 */
143 clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
144 puts("WARNING: SPI enabled, TSEC2 support is broken\n");
145
146 /* Set header J8 SPI chip select output, disabled */
147 setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
148 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
149#endif
150
Ilya Yanok5fb17032010-07-07 20:16:13 +0400151#ifdef CONFIG_VSC7385_IMAGE
152 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
153 CONFIG_VSC7385_IMAGE_SIZE)) {
154 puts("Failure uploading VSC7385 microcode.\n");
155 return 1;
156 }
157#endif
158
159 return 0;
160}
161#if defined(CONFIG_OF_BOARD_SETUP)
Simon Glasse895a4b2014-10-23 18:58:47 -0600162int ft_board_setup(void *blob, bd_t *bd)
Ilya Yanok5fb17032010-07-07 20:16:13 +0400163{
164 ft_cpu_setup(blob, bd);
Sriram Dasha5c289b2016-09-16 17:12:15 +0530165 fsl_fdt_fixup_dr_usb(blob, bd);
Ira W. Snyderdb1fc7d2012-09-12 14:17:35 -0700166 fdt_fixup_esdhc(blob, bd);
Simon Glasse895a4b2014-10-23 18:58:47 -0600167
168 return 0;
Ilya Yanok5fb17032010-07-07 20:16:13 +0400169}
170#endif
171
172int board_eth_init(bd_t *bis)
173{
174 int rv, num_if = 0;
175
176 /* Initialize TSECs first */
Ilya Yanok65ea7582010-09-17 23:41:49 +0200177 rv = cpu_eth_init(bis);
178 if (rv >= 0)
Ilya Yanok5fb17032010-07-07 20:16:13 +0400179 num_if += rv;
180 else
181 printf("ERROR: failed to initialize TSECs.\n");
182
Ilya Yanok65ea7582010-09-17 23:41:49 +0200183 rv = pci_eth_init(bis);
184 if (rv >= 0)
Ilya Yanok5fb17032010-07-07 20:16:13 +0400185 num_if += rv;
186 else
187 printf("ERROR: failed to initialize PCI Ethernet.\n");
188
189 return num_if;
190}