blob: 50354fdde1a40cbf0b25d4f3a35327c9b392ec36 [file] [log] [blame]
Simon Glass18530302013-03-19 04:58:56 +00001/*
2 * Copyright (c) 2011-12 The Chromium OS Authors.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Simon Glass18530302013-03-19 04:58:56 +00005 *
6 * This file is derived from the flashrom project.
7 */
8
9#include <common.h>
Simon Glassba457562015-03-26 09:29:26 -060010#include <dm.h>
Simon Glass5093bad2015-01-27 22:13:43 -070011#include <errno.h>
Simon Glass18530302013-03-19 04:58:56 +000012#include <malloc.h>
13#include <spi.h>
14#include <pci.h>
15#include <pci_ids.h>
16#include <asm/io.h>
17
18#include "ich.h"
19
20#define SPI_OPCODE_WREN 0x06
21#define SPI_OPCODE_FAST_READ 0x0b
22
Simon Glassba457562015-03-26 09:29:26 -060023struct ich_spi_platdata {
Simon Glass18530302013-03-19 04:58:56 +000024 pci_dev_t dev; /* PCI device number */
25 int ich_version; /* Controller version, 7 or 9 */
Simon Glass5093bad2015-01-27 22:13:43 -070026 bool use_sbase; /* Use SBASE instead of RCB */
Simon Glass18530302013-03-19 04:58:56 +000027};
28
Simon Glassba457562015-03-26 09:29:26 -060029struct ich_spi_priv {
30 int ichspi_lock;
31 int locked;
32 int opmenu;
33 int menubytes;
34 void *base; /* Base of register set */
35 int preop;
36 int optype;
37 int addr;
38 int data;
39 unsigned databytes;
40 int status;
41 int control;
42 int bbar;
43 uint32_t *pr; /* only for ich9 */
44 int speed; /* pointer to speed control */
45 ulong max_speed; /* Maximum bus speed in MHz */
46 ulong cur_speed; /* Current bus speed */
47 struct spi_trans trans; /* current transaction in progress */
48};
Simon Glass18530302013-03-19 04:58:56 +000049
Simon Glassba457562015-03-26 09:29:26 -060050static u8 ich_readb(struct ich_spi_priv *priv, int reg)
Simon Glass18530302013-03-19 04:58:56 +000051{
Simon Glassba457562015-03-26 09:29:26 -060052 u8 value = readb(priv->base + reg);
Simon Glass18530302013-03-19 04:58:56 +000053
Simon Glassba457562015-03-26 09:29:26 -060054 debug("read %2.2x from %4.4x\n", value, reg);
Simon Glass18530302013-03-19 04:58:56 +000055
56 return value;
57}
58
Simon Glassba457562015-03-26 09:29:26 -060059static u16 ich_readw(struct ich_spi_priv *priv, int reg)
Simon Glass18530302013-03-19 04:58:56 +000060{
Simon Glassba457562015-03-26 09:29:26 -060061 u16 value = readw(priv->base + reg);
Simon Glass18530302013-03-19 04:58:56 +000062
Simon Glassba457562015-03-26 09:29:26 -060063 debug("read %4.4x from %4.4x\n", value, reg);
Simon Glass18530302013-03-19 04:58:56 +000064
65 return value;
66}
67
Simon Glassba457562015-03-26 09:29:26 -060068static u32 ich_readl(struct ich_spi_priv *priv, int reg)
Simon Glass18530302013-03-19 04:58:56 +000069{
Simon Glassba457562015-03-26 09:29:26 -060070 u32 value = readl(priv->base + reg);
Simon Glass18530302013-03-19 04:58:56 +000071
Simon Glassba457562015-03-26 09:29:26 -060072 debug("read %8.8x from %4.4x\n", value, reg);
Simon Glass18530302013-03-19 04:58:56 +000073
74 return value;
75}
76
Simon Glassba457562015-03-26 09:29:26 -060077static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
Simon Glass18530302013-03-19 04:58:56 +000078{
Simon Glassba457562015-03-26 09:29:26 -060079 writeb(value, priv->base + reg);
80 debug("wrote %2.2x to %4.4x\n", value, reg);
Simon Glass18530302013-03-19 04:58:56 +000081}
82
Simon Glassba457562015-03-26 09:29:26 -060083static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
Simon Glass18530302013-03-19 04:58:56 +000084{
Simon Glassba457562015-03-26 09:29:26 -060085 writew(value, priv->base + reg);
86 debug("wrote %4.4x to %4.4x\n", value, reg);
Simon Glass18530302013-03-19 04:58:56 +000087}
88
Simon Glassba457562015-03-26 09:29:26 -060089static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
Simon Glass18530302013-03-19 04:58:56 +000090{
Simon Glassba457562015-03-26 09:29:26 -060091 writel(value, priv->base + reg);
92 debug("wrote %8.8x to %4.4x\n", value, reg);
Simon Glass18530302013-03-19 04:58:56 +000093}
94
Simon Glassba457562015-03-26 09:29:26 -060095static void write_reg(struct ich_spi_priv *priv, const void *value,
96 int dest_reg, uint32_t size)
Simon Glass18530302013-03-19 04:58:56 +000097{
Simon Glassba457562015-03-26 09:29:26 -060098 memcpy_toio(priv->base + dest_reg, value, size);
Simon Glass18530302013-03-19 04:58:56 +000099}
100
Simon Glassba457562015-03-26 09:29:26 -0600101static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
102 uint32_t size)
Simon Glass18530302013-03-19 04:58:56 +0000103{
Simon Glassba457562015-03-26 09:29:26 -0600104 memcpy_fromio(value, priv->base + src_reg, size);
Simon Glass18530302013-03-19 04:58:56 +0000105}
106
Simon Glassba457562015-03-26 09:29:26 -0600107static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
Simon Glass18530302013-03-19 04:58:56 +0000108{
109 const uint32_t bbar_mask = 0x00ffff00;
110 uint32_t ichspi_bbar;
111
112 minaddr &= bbar_mask;
Simon Glassba457562015-03-26 09:29:26 -0600113 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
Simon Glass18530302013-03-19 04:58:56 +0000114 ichspi_bbar |= minaddr;
Simon Glassba457562015-03-26 09:29:26 -0600115 ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
Simon Glass18530302013-03-19 04:58:56 +0000116}
117
118/*
119 * Check if this device ID matches one of supported Intel PCH devices.
120 *
121 * Return the ICH version if there is a match, or zero otherwise.
122 */
123static int get_ich_version(uint16_t device_id)
124{
Bin Meng7e774032014-12-12 21:05:27 +0800125 if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC ||
Bin Meng728b3932015-02-04 16:26:12 +0800126 device_id == PCI_DEVICE_ID_INTEL_ITC_LPC ||
127 device_id == PCI_DEVICE_ID_INTEL_QRK_ILB)
Simon Glass18530302013-03-19 04:58:56 +0000128 return 7;
129
130 if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
131 device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
132 (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
Simon Glass5093bad2015-01-27 22:13:43 -0700133 device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
Simon Glass87108cf2015-03-02 12:40:52 -0700134 device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC ||
135 device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC)
Simon Glass18530302013-03-19 04:58:56 +0000136 return 9;
137
138 return 0;
139}
140
141/* @return 1 if the SPI flash supports the 33MHz speed */
142static int ich9_can_do_33mhz(pci_dev_t dev)
143{
144 u32 fdod, speed;
145
146 /* Observe SPI Descriptor Component Section 0 */
147 pci_write_config_dword(dev, 0xb0, 0x1000);
148
149 /* Extract the Write/Erase SPI Frequency from descriptor */
150 pci_read_config_dword(dev, 0xb4, &fdod);
151
152 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
153 speed = (fdod >> 21) & 7;
154
155 return speed == 1;
156}
157
Simon Glassba457562015-03-26 09:29:26 -0600158static int ich_find_spi_controller(struct ich_spi_platdata *ich)
Simon Glass18530302013-03-19 04:58:56 +0000159{
160 int last_bus = pci_last_busno();
161 int bus;
162
163 if (last_bus == -1) {
164 debug("No PCI busses?\n");
Simon Glass5093bad2015-01-27 22:13:43 -0700165 return -ENODEV;
Simon Glass18530302013-03-19 04:58:56 +0000166 }
167
168 for (bus = 0; bus <= last_bus; bus++) {
169 uint16_t vendor_id, device_id;
170 uint32_t ids;
171 pci_dev_t dev;
172
173 dev = PCI_BDF(bus, 31, 0);
174 pci_read_config_dword(dev, 0, &ids);
175 vendor_id = ids;
176 device_id = ids >> 16;
177
178 if (vendor_id == PCI_VENDOR_ID_INTEL) {
Simon Glass5093bad2015-01-27 22:13:43 -0700179 ich->dev = dev;
180 ich->ich_version = get_ich_version(device_id);
181 if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
182 ich->use_sbase = true;
183 return ich->ich_version == 0 ? -ENODEV : 0;
Simon Glass18530302013-03-19 04:58:56 +0000184 }
185 }
186
187 debug("ICH SPI: No ICH found.\n");
Simon Glass5093bad2015-01-27 22:13:43 -0700188 return -ENODEV;
Simon Glass18530302013-03-19 04:58:56 +0000189}
190
Simon Glassba457562015-03-26 09:29:26 -0600191static int ich_init_controller(struct ich_spi_platdata *plat,
192 struct ich_spi_priv *ctlr)
Simon Glass18530302013-03-19 04:58:56 +0000193{
194 uint8_t *rcrb; /* Root Complex Register Block */
195 uint32_t rcba; /* Root Complex Base Address */
Simon Glass5093bad2015-01-27 22:13:43 -0700196 uint32_t sbase_addr;
197 uint8_t *sbase;
Simon Glass18530302013-03-19 04:58:56 +0000198
Simon Glassba457562015-03-26 09:29:26 -0600199 pci_read_config_dword(plat->dev, 0xf0, &rcba);
Simon Glass18530302013-03-19 04:58:56 +0000200 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
201 rcrb = (uint8_t *)(rcba & 0xffffc000);
Simon Glass5093bad2015-01-27 22:13:43 -0700202
203 /* SBASE is similar */
Simon Glassba457562015-03-26 09:29:26 -0600204 pci_read_config_dword(plat->dev, 0x54, &sbase_addr);
Simon Glass5093bad2015-01-27 22:13:43 -0700205 sbase = (uint8_t *)(sbase_addr & 0xfffffe00);
206
Simon Glassba457562015-03-26 09:29:26 -0600207 if (plat->ich_version == 7) {
Simon Glass18530302013-03-19 04:58:56 +0000208 struct ich7_spi_regs *ich7_spi;
209
210 ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
Simon Glassba457562015-03-26 09:29:26 -0600211 ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK;
212 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
Simon Glass18530302013-03-19 04:58:56 +0000213 ctlr->menubytes = sizeof(ich7_spi->opmenu);
Simon Glassba457562015-03-26 09:29:26 -0600214 ctlr->optype = offsetof(struct ich7_spi_regs, optype);
215 ctlr->addr = offsetof(struct ich7_spi_regs, spia);
216 ctlr->data = offsetof(struct ich7_spi_regs, spid);
Simon Glass18530302013-03-19 04:58:56 +0000217 ctlr->databytes = sizeof(ich7_spi->spid);
Simon Glassba457562015-03-26 09:29:26 -0600218 ctlr->status = offsetof(struct ich7_spi_regs, spis);
219 ctlr->control = offsetof(struct ich7_spi_regs, spic);
220 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
221 ctlr->preop = offsetof(struct ich7_spi_regs, preop);
Simon Glass18530302013-03-19 04:58:56 +0000222 ctlr->base = ich7_spi;
Simon Glassba457562015-03-26 09:29:26 -0600223 } else if (plat->ich_version == 9) {
Simon Glass18530302013-03-19 04:58:56 +0000224 struct ich9_spi_regs *ich9_spi;
225
Simon Glassba457562015-03-26 09:29:26 -0600226 if (plat->use_sbase)
Simon Glass5093bad2015-01-27 22:13:43 -0700227 ich9_spi = (struct ich9_spi_regs *)sbase;
228 else
229 ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
Simon Glassba457562015-03-26 09:29:26 -0600230 ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
231 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
Simon Glass18530302013-03-19 04:58:56 +0000232 ctlr->menubytes = sizeof(ich9_spi->opmenu);
Simon Glassba457562015-03-26 09:29:26 -0600233 ctlr->optype = offsetof(struct ich9_spi_regs, optype);
234 ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
235 ctlr->data = offsetof(struct ich9_spi_regs, fdata);
Simon Glass18530302013-03-19 04:58:56 +0000236 ctlr->databytes = sizeof(ich9_spi->fdata);
Simon Glassba457562015-03-26 09:29:26 -0600237 ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
238 ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
239 ctlr->speed = ctlr->control + 2;
240 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
241 ctlr->preop = offsetof(struct ich9_spi_regs, preop);
Simon Glass18530302013-03-19 04:58:56 +0000242 ctlr->pr = &ich9_spi->pr[0];
243 ctlr->base = ich9_spi;
244 } else {
Simon Glassba457562015-03-26 09:29:26 -0600245 debug("ICH SPI: Unrecognised ICH version %d\n",
246 plat->ich_version);
247 return -EINVAL;
Simon Glass18530302013-03-19 04:58:56 +0000248 }
Simon Glass18530302013-03-19 04:58:56 +0000249
250 /* Work out the maximum speed we can support */
251 ctlr->max_speed = 20000000;
Simon Glassba457562015-03-26 09:29:26 -0600252 if (plat->ich_version == 9 && ich9_can_do_33mhz(plat->dev))
Simon Glass18530302013-03-19 04:58:56 +0000253 ctlr->max_speed = 33000000;
Simon Glass5093bad2015-01-27 22:13:43 -0700254 debug("ICH SPI: Version %d detected at %p, speed %ld\n",
Simon Glassba457562015-03-26 09:29:26 -0600255 plat->ich_version, ctlr->base, ctlr->max_speed);
Simon Glass18530302013-03-19 04:58:56 +0000256
257 ich_set_bbar(ctlr, 0);
258
259 return 0;
260}
261
Simon Glass18530302013-03-19 04:58:56 +0000262static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
263{
264 trans->out += bytes;
265 trans->bytesout -= bytes;
266}
267
268static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
269{
270 trans->in += bytes;
271 trans->bytesin -= bytes;
272}
273
274static void spi_setup_type(struct spi_trans *trans, int data_bytes)
275{
276 trans->type = 0xFF;
277
278 /* Try to guess spi type from read/write sizes. */
279 if (trans->bytesin == 0) {
280 if (trans->bytesout + data_bytes > 4)
281 /*
282 * If bytesin = 0 and bytesout > 4, we presume this is
283 * a write data operation, which is accompanied by an
284 * address.
285 */
286 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
287 else
288 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
289 return;
290 }
291
292 if (trans->bytesout == 1) { /* and bytesin is > 0 */
293 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
294 return;
295 }
296
297 if (trans->bytesout == 4) /* and bytesin is > 0 */
298 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
299
300 /* Fast read command is called with 5 bytes instead of 4 */
301 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
302 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
303 --trans->bytesout;
304 }
305}
306
Simon Glassba457562015-03-26 09:29:26 -0600307static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans)
Simon Glass18530302013-03-19 04:58:56 +0000308{
309 uint16_t optypes;
Simon Glassba457562015-03-26 09:29:26 -0600310 uint8_t opmenu[ctlr->menubytes];
Simon Glass18530302013-03-19 04:58:56 +0000311
312 trans->opcode = trans->out[0];
313 spi_use_out(trans, 1);
Simon Glassba457562015-03-26 09:29:26 -0600314 if (!ctlr->ichspi_lock) {
Simon Glass18530302013-03-19 04:58:56 +0000315 /* The lock is off, so just use index 0. */
Simon Glassba457562015-03-26 09:29:26 -0600316 ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
317 optypes = ich_readw(ctlr, ctlr->optype);
Simon Glass18530302013-03-19 04:58:56 +0000318 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
Simon Glassba457562015-03-26 09:29:26 -0600319 ich_writew(ctlr, optypes, ctlr->optype);
Simon Glass18530302013-03-19 04:58:56 +0000320 return 0;
321 } else {
322 /* The lock is on. See if what we need is on the menu. */
323 uint8_t optype;
324 uint16_t opcode_index;
325
326 /* Write Enable is handled as atomic prefix */
327 if (trans->opcode == SPI_OPCODE_WREN)
328 return 0;
329
Simon Glassba457562015-03-26 09:29:26 -0600330 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
331 for (opcode_index = 0; opcode_index < ctlr->menubytes;
Simon Glass18530302013-03-19 04:58:56 +0000332 opcode_index++) {
333 if (opmenu[opcode_index] == trans->opcode)
334 break;
335 }
336
Simon Glassba457562015-03-26 09:29:26 -0600337 if (opcode_index == ctlr->menubytes) {
Simon Glass18530302013-03-19 04:58:56 +0000338 printf("ICH SPI: Opcode %x not found\n",
339 trans->opcode);
Simon Glassba457562015-03-26 09:29:26 -0600340 return -EINVAL;
Simon Glass18530302013-03-19 04:58:56 +0000341 }
342
Simon Glassba457562015-03-26 09:29:26 -0600343 optypes = ich_readw(ctlr, ctlr->optype);
Simon Glass18530302013-03-19 04:58:56 +0000344 optype = (optypes >> (opcode_index * 2)) & 0x3;
345 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
346 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
347 trans->bytesout >= 3) {
348 /* We guessed wrong earlier. Fix it up. */
349 trans->type = optype;
350 }
351 if (optype != trans->type) {
352 printf("ICH SPI: Transaction doesn't fit type %d\n",
353 optype);
Simon Glassba457562015-03-26 09:29:26 -0600354 return -ENOSPC;
Simon Glass18530302013-03-19 04:58:56 +0000355 }
356 return opcode_index;
357 }
358}
359
360static int spi_setup_offset(struct spi_trans *trans)
361{
362 /* Separate the SPI address and data. */
363 switch (trans->type) {
364 case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
365 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
366 return 0;
367 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
368 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
369 trans->offset = ((uint32_t)trans->out[0] << 16) |
370 ((uint32_t)trans->out[1] << 8) |
371 ((uint32_t)trans->out[2] << 0);
372 spi_use_out(trans, 3);
373 return 1;
374 default:
375 printf("Unrecognized SPI transaction type %#x\n", trans->type);
Simon Glassba457562015-03-26 09:29:26 -0600376 return -EPROTO;
Simon Glass18530302013-03-19 04:58:56 +0000377 }
378}
379
380/*
381 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
York Sun472d5462013-04-01 11:29:11 -0700382 * below is true) or 0. In case the wait was for the bit(s) to set - write
Simon Glass18530302013-03-19 04:58:56 +0000383 * those bits back, which would cause resetting them.
384 *
385 * Return the last read status value on success or -1 on failure.
386 */
Simon Glassba457562015-03-26 09:29:26 -0600387static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
388 int wait_til_set)
Simon Glass18530302013-03-19 04:58:56 +0000389{
390 int timeout = 600000; /* This will result in 6s */
391 u16 status = 0;
392
393 while (timeout--) {
Simon Glassba457562015-03-26 09:29:26 -0600394 status = ich_readw(ctlr, ctlr->status);
Simon Glass18530302013-03-19 04:58:56 +0000395 if (wait_til_set ^ ((status & bitmask) == 0)) {
Simon Glassba457562015-03-26 09:29:26 -0600396 if (wait_til_set) {
397 ich_writew(ctlr, status & bitmask,
398 ctlr->status);
399 }
Simon Glass18530302013-03-19 04:58:56 +0000400 return status;
401 }
402 udelay(10);
403 }
404
405 printf("ICH SPI: SCIP timeout, read %x, expected %x\n",
406 status, bitmask);
Simon Glassba457562015-03-26 09:29:26 -0600407 return -ETIMEDOUT;
Simon Glass18530302013-03-19 04:58:56 +0000408}
409
Simon Glassba457562015-03-26 09:29:26 -0600410static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
411 const void *dout, void *din, unsigned long flags)
Simon Glass18530302013-03-19 04:58:56 +0000412{
Simon Glassba457562015-03-26 09:29:26 -0600413 struct udevice *bus = dev_get_parent(dev);
414 struct ich_spi_priv *ctlr = dev_get_priv(bus);
Simon Glass18530302013-03-19 04:58:56 +0000415 uint16_t control;
416 int16_t opcode_index;
417 int with_address;
418 int status;
419 int bytes = bitlen / 8;
Simon Glassba457562015-03-26 09:29:26 -0600420 struct spi_trans *trans = &ctlr->trans;
Simon Glass18530302013-03-19 04:58:56 +0000421 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
422 int using_cmd = 0;
Simon Glassba457562015-03-26 09:29:26 -0600423 int ret;
Simon Glass18530302013-03-19 04:58:56 +0000424
425 /* Ee don't support writing partial bytes. */
426 if (bitlen % 8) {
427 debug("ICH SPI: Accessing partial bytes not supported\n");
Simon Glassba457562015-03-26 09:29:26 -0600428 return -EPROTONOSUPPORT;
Simon Glass18530302013-03-19 04:58:56 +0000429 }
430
431 /* An empty end transaction can be ignored */
432 if (type == SPI_XFER_END && !dout && !din)
433 return 0;
434
435 if (type & SPI_XFER_BEGIN)
436 memset(trans, '\0', sizeof(*trans));
437
438 /* Dp we need to come back later to finish it? */
439 if (dout && type == SPI_XFER_BEGIN) {
440 if (bytes > ICH_MAX_CMD_LEN) {
441 debug("ICH SPI: Command length limit exceeded\n");
Simon Glassba457562015-03-26 09:29:26 -0600442 return -ENOSPC;
Simon Glass18530302013-03-19 04:58:56 +0000443 }
444 memcpy(trans->cmd, dout, bytes);
445 trans->cmd_len = bytes;
446 debug("ICH SPI: Saved %d bytes\n", bytes);
447 return 0;
448 }
449
450 /*
451 * We process a 'middle' spi_xfer() call, which has no
452 * SPI_XFER_BEGIN/END, as an independent transaction as if it had
453 * an end. We therefore repeat the command. This is because ICH
454 * seems to have no support for this, or because interest (in digging
455 * out the details and creating a special case in the code) is low.
456 */
457 if (trans->cmd_len) {
458 trans->out = trans->cmd;
459 trans->bytesout = trans->cmd_len;
460 using_cmd = 1;
461 debug("ICH SPI: Using %d bytes\n", trans->cmd_len);
462 } else {
463 trans->out = dout;
464 trans->bytesout = dout ? bytes : 0;
465 }
466
467 trans->in = din;
468 trans->bytesin = din ? bytes : 0;
469
470 /* There has to always at least be an opcode. */
471 if (!trans->bytesout) {
472 debug("ICH SPI: No opcode for transfer\n");
Simon Glassba457562015-03-26 09:29:26 -0600473 return -EPROTO;
Simon Glass18530302013-03-19 04:58:56 +0000474 }
475
Simon Glassba457562015-03-26 09:29:26 -0600476 ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
477 if (ret < 0)
478 return ret;
Simon Glass18530302013-03-19 04:58:56 +0000479
Simon Glassba457562015-03-26 09:29:26 -0600480 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
Simon Glass18530302013-03-19 04:58:56 +0000481
482 spi_setup_type(trans, using_cmd ? bytes : 0);
Simon Glassba457562015-03-26 09:29:26 -0600483 opcode_index = spi_setup_opcode(ctlr, trans);
Simon Glass18530302013-03-19 04:58:56 +0000484 if (opcode_index < 0)
Simon Glassba457562015-03-26 09:29:26 -0600485 return -EINVAL;
Simon Glass18530302013-03-19 04:58:56 +0000486 with_address = spi_setup_offset(trans);
487 if (with_address < 0)
Simon Glassba457562015-03-26 09:29:26 -0600488 return -EINVAL;
Simon Glass18530302013-03-19 04:58:56 +0000489
490 if (trans->opcode == SPI_OPCODE_WREN) {
491 /*
492 * Treat Write Enable as Atomic Pre-Op if possible
493 * in order to prevent the Management Engine from
494 * issuing a transaction between WREN and DATA.
495 */
Simon Glassba457562015-03-26 09:29:26 -0600496 if (!ctlr->ichspi_lock)
497 ich_writew(ctlr, trans->opcode, ctlr->preop);
Simon Glass18530302013-03-19 04:58:56 +0000498 return 0;
499 }
500
Simon Glassba457562015-03-26 09:29:26 -0600501 if (ctlr->speed && ctlr->max_speed >= 33000000) {
Simon Glass18530302013-03-19 04:58:56 +0000502 int byte;
503
Simon Glassba457562015-03-26 09:29:26 -0600504 byte = ich_readb(ctlr, ctlr->speed);
505 if (ctlr->cur_speed >= 33000000)
Simon Glass18530302013-03-19 04:58:56 +0000506 byte |= SSFC_SCF_33MHZ;
507 else
508 byte &= ~SSFC_SCF_33MHZ;
Simon Glassba457562015-03-26 09:29:26 -0600509 ich_writeb(ctlr, byte, ctlr->speed);
Simon Glass18530302013-03-19 04:58:56 +0000510 }
511
512 /* See if we have used up the command data */
513 if (using_cmd && dout && bytes) {
514 trans->out = dout;
515 trans->bytesout = bytes;
516 debug("ICH SPI: Moving to data, %d bytes\n", bytes);
517 }
518
519 /* Preset control fields */
Simon Glassba457562015-03-26 09:29:26 -0600520 control = ich_readw(ctlr, ctlr->control);
Simon Glass18530302013-03-19 04:58:56 +0000521 control &= ~SSFC_RESERVED;
522 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
523
524 /* Issue atomic preop cycle if needed */
Simon Glassba457562015-03-26 09:29:26 -0600525 if (ich_readw(ctlr, ctlr->preop))
Simon Glass18530302013-03-19 04:58:56 +0000526 control |= SPIC_ACS;
527
528 if (!trans->bytesout && !trans->bytesin) {
529 /* SPI addresses are 24 bit only */
Simon Glassba457562015-03-26 09:29:26 -0600530 if (with_address) {
531 ich_writel(ctlr, trans->offset & 0x00FFFFFF,
532 ctlr->addr);
533 }
Simon Glass18530302013-03-19 04:58:56 +0000534 /*
535 * This is a 'no data' command (like Write Enable), its
536 * bitesout size was 1, decremented to zero while executing
537 * spi_setup_opcode() above. Tell the chip to send the
538 * command.
539 */
Simon Glassba457562015-03-26 09:29:26 -0600540 ich_writew(ctlr, control, ctlr->control);
Simon Glass18530302013-03-19 04:58:56 +0000541
542 /* wait for the result */
Simon Glassba457562015-03-26 09:29:26 -0600543 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
544 if (status < 0)
545 return status;
Simon Glass18530302013-03-19 04:58:56 +0000546
547 if (status & SPIS_FCERR) {
548 debug("ICH SPI: Command transaction error\n");
Simon Glassba457562015-03-26 09:29:26 -0600549 return -EIO;
Simon Glass18530302013-03-19 04:58:56 +0000550 }
551
552 return 0;
553 }
554
555 /*
556 * Check if this is a write command atempting to transfer more bytes
557 * than the controller can handle. Iterations for writes are not
558 * supported here because each SPI write command needs to be preceded
559 * and followed by other SPI commands, and this sequence is controlled
560 * by the SPI chip driver.
561 */
Simon Glassba457562015-03-26 09:29:26 -0600562 if (trans->bytesout > ctlr->databytes) {
Simon Glass18530302013-03-19 04:58:56 +0000563 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n");
Simon Glassba457562015-03-26 09:29:26 -0600564 return -EPROTO;
Simon Glass18530302013-03-19 04:58:56 +0000565 }
566
567 /*
568 * Read or write up to databytes bytes at a time until everything has
569 * been sent.
570 */
571 while (trans->bytesout || trans->bytesin) {
572 uint32_t data_length;
Simon Glass18530302013-03-19 04:58:56 +0000573
574 /* SPI addresses are 24 bit only */
Simon Glassba457562015-03-26 09:29:26 -0600575 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
Simon Glass18530302013-03-19 04:58:56 +0000576
577 if (trans->bytesout)
Simon Glassba457562015-03-26 09:29:26 -0600578 data_length = min(trans->bytesout, ctlr->databytes);
Simon Glass18530302013-03-19 04:58:56 +0000579 else
Simon Glassba457562015-03-26 09:29:26 -0600580 data_length = min(trans->bytesin, ctlr->databytes);
Simon Glass18530302013-03-19 04:58:56 +0000581
582 /* Program data into FDATA0 to N */
583 if (trans->bytesout) {
Simon Glassba457562015-03-26 09:29:26 -0600584 write_reg(ctlr, trans->out, ctlr->data, data_length);
Simon Glass18530302013-03-19 04:58:56 +0000585 spi_use_out(trans, data_length);
586 if (with_address)
587 trans->offset += data_length;
588 }
589
590 /* Add proper control fields' values */
Simon Glassba457562015-03-26 09:29:26 -0600591 control &= ~((ctlr->databytes - 1) << 8);
Simon Glass18530302013-03-19 04:58:56 +0000592 control |= SPIC_DS;
593 control |= (data_length - 1) << 8;
594
595 /* write it */
Simon Glassba457562015-03-26 09:29:26 -0600596 ich_writew(ctlr, control, ctlr->control);
Simon Glass18530302013-03-19 04:58:56 +0000597
598 /* Wait for Cycle Done Status or Flash Cycle Error. */
Simon Glassba457562015-03-26 09:29:26 -0600599 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
600 if (status < 0)
601 return status;
Simon Glass18530302013-03-19 04:58:56 +0000602
603 if (status & SPIS_FCERR) {
604 debug("ICH SPI: Data transaction error\n");
Simon Glassba457562015-03-26 09:29:26 -0600605 return -EIO;
Simon Glass18530302013-03-19 04:58:56 +0000606 }
607
608 if (trans->bytesin) {
Simon Glassba457562015-03-26 09:29:26 -0600609 read_reg(ctlr, ctlr->data, trans->in, data_length);
Simon Glass18530302013-03-19 04:58:56 +0000610 spi_use_in(trans, data_length);
611 if (with_address)
612 trans->offset += data_length;
613 }
614 }
615
616 /* Clear atomic preop now that xfer is done */
Simon Glassba457562015-03-26 09:29:26 -0600617 ich_writew(ctlr, 0, ctlr->preop);
Simon Glass18530302013-03-19 04:58:56 +0000618
619 return 0;
620}
621
622
623/*
624 * This uses the SPI controller from the Intel Cougar Point and Panther Point
625 * PCH to write-protect portions of the SPI flash until reboot. The changes
626 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's
627 * done elsewhere.
628 */
Simon Glassba457562015-03-26 09:29:26 -0600629int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit,
630 uint32_t length, int hint)
Simon Glass18530302013-03-19 04:58:56 +0000631{
Simon Glassba457562015-03-26 09:29:26 -0600632 struct udevice *bus = dev->parent;
633 struct ich_spi_priv *ctlr = dev_get_priv(bus);
Simon Glass18530302013-03-19 04:58:56 +0000634 uint32_t tmplong;
635 uint32_t upper_limit;
636
Simon Glassba457562015-03-26 09:29:26 -0600637 if (!ctlr->pr) {
Simon Glass18530302013-03-19 04:58:56 +0000638 printf("%s: operation not supported on this chipset\n",
639 __func__);
Simon Glassba457562015-03-26 09:29:26 -0600640 return -ENOSYS;
Simon Glass18530302013-03-19 04:58:56 +0000641 }
642
643 if (length == 0 ||
644 lower_limit > (0xFFFFFFFFUL - length) + 1 ||
645 hint < 0 || hint > 4) {
646 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__,
647 lower_limit, length, hint);
Simon Glassba457562015-03-26 09:29:26 -0600648 return -EPERM;
Simon Glass18530302013-03-19 04:58:56 +0000649 }
650
651 upper_limit = lower_limit + length - 1;
652
653 /*
654 * Determine bits to write, as follows:
655 * 31 Write-protection enable (includes erase operation)
656 * 30:29 reserved
657 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff)
658 * 15 Read-protection enable
659 * 14:13 reserved
660 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000)
661 */
662 tmplong = 0x80000000 |
663 ((upper_limit & 0x01fff000) << 4) |
664 ((lower_limit & 0x01fff000) >> 12);
665
666 printf("%s: writing 0x%08x to %p\n", __func__, tmplong,
Simon Glassba457562015-03-26 09:29:26 -0600667 &ctlr->pr[hint]);
668 ctlr->pr[hint] = tmplong;
Simon Glass18530302013-03-19 04:58:56 +0000669
670 return 0;
671}
Simon Glassba457562015-03-26 09:29:26 -0600672
673static int ich_spi_probe(struct udevice *bus)
674{
675 struct ich_spi_platdata *plat = dev_get_platdata(bus);
676 struct ich_spi_priv *priv = dev_get_priv(bus);
677 uint8_t bios_cntl;
678 int ret;
679
680 ret = ich_init_controller(plat, priv);
681 if (ret)
682 return ret;
683 /*
684 * Disable the BIOS write protect so write commands are allowed. On
685 * v9, deassert SMM BIOS Write Protect Disable.
686 */
687 if (plat->use_sbase) {
688 struct ich9_spi_regs *ich9_spi;
689
690 ich9_spi = priv->base;
691 bios_cntl = ich_readb(priv, ich9_spi->bcr);
692 bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */
693 bios_cntl |= 1; /* Write Protect Disable (WPD) */
694 ich_writeb(priv, bios_cntl, ich9_spi->bcr);
695 } else {
696 pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
697 if (plat->ich_version == 9)
698 bios_cntl &= ~(1 << 5);
699 pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1);
700 }
701
702 priv->cur_speed = priv->max_speed;
703
704 return 0;
705}
706
707static int ich_spi_ofdata_to_platdata(struct udevice *bus)
708{
709 struct ich_spi_platdata *plat = dev_get_platdata(bus);
710 int ret;
711
712 ret = ich_find_spi_controller(plat);
713 if (ret)
714 return ret;
715
716 return 0;
717}
718
719static int ich_spi_set_speed(struct udevice *bus, uint speed)
720{
721 struct ich_spi_priv *priv = dev_get_priv(bus);
722
723 priv->cur_speed = speed;
724
725 return 0;
726}
727
728static int ich_spi_set_mode(struct udevice *bus, uint mode)
729{
730 debug("%s: mode=%d\n", __func__, mode);
731
732 return 0;
733}
734
735static int ich_spi_child_pre_probe(struct udevice *dev)
736{
737 struct udevice *bus = dev_get_parent(dev);
738 struct ich_spi_platdata *plat = dev_get_platdata(bus);
739 struct ich_spi_priv *priv = dev_get_priv(bus);
740 struct spi_slave *slave = dev_get_parentdata(dev);
741
742 /*
743 * Yes this controller can only write a small number of bytes at
744 * once! The limit is typically 64 bytes.
745 */
746 slave->max_write_size = priv->databytes;
747 /*
748 * ICH 7 SPI controller only supports array read command
749 * and byte program command for SST flash
750 */
751 if (plat->ich_version == 7) {
752 slave->op_mode_rx = SPI_OPM_RX_AS;
753 slave->op_mode_tx = SPI_OPM_TX_BP;
754 }
755
756 return 0;
757}
758
759static const struct dm_spi_ops ich_spi_ops = {
760 .xfer = ich_spi_xfer,
761 .set_speed = ich_spi_set_speed,
762 .set_mode = ich_spi_set_mode,
763 /*
764 * cs_info is not needed, since we require all chip selects to be
765 * in the device tree explicitly
766 */
767};
768
769static const struct udevice_id ich_spi_ids[] = {
770 { .compatible = "intel,ich-spi" },
771 { }
772};
773
774U_BOOT_DRIVER(ich_spi) = {
775 .name = "ich_spi",
776 .id = UCLASS_SPI,
777 .of_match = ich_spi_ids,
778 .ops = &ich_spi_ops,
779 .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
780 .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
781 .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
782 .child_pre_probe = ich_spi_child_pre_probe,
783 .probe = ich_spi_probe,
784};