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Timur Tabi2ad6b512006-10-31 18:44:42 -06001/*
Kumar Gala4c2e3da2009-07-28 21:49:52 -05002 * Copyright (C) Freescale Semiconductor, Inc. 2006.
Timur Tabi2ad6b512006-10-31 18:44:42 -06003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Timur Tabi2ad6b512006-10-31 18:44:42 -06005 */
6
7/*
Timur Tabi7a78f142007-01-31 15:54:29 -06008 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
Timur Tabi2ad6b512006-10-31 18:44:42 -06009
10 Memory map:
11
12 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
13 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
14 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
15 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
16 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
17 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
Timur Tabi7a78f142007-01-31 15:54:29 -060018 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
Timur Tabi2ad6b512006-10-31 18:44:42 -060019 0xF001_0000-0xF001_FFFF Local bus expansion slot
Timur Tabi7a78f142007-01-31 15:54:29 -060020 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
21 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
22 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
Timur Tabi2ad6b512006-10-31 18:44:42 -060023
24 I2C address list:
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010025 Align. Board
26 Bus Addr Part No. Description Length Location
Timur Tabi2ad6b512006-10-31 18:44:42 -060027 ----------------------------------------------------------------
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010028 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
Timur Tabi2ad6b512006-10-31 18:44:42 -060029
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010030 I2C1 0x20 PCF8574 I2C Expander 0 U8
31 I2C1 0x21 PCF8574 I2C Expander 0 U10
32 I2C1 0x38 PCF8574A I2C Expander 0 U8
33 I2C1 0x39 PCF8574A I2C Expander 0 U10
34 I2C1 0x51 (DDR) DDR EEPROM 1 U1
35 I2C1 0x68 DS1339 RTC 1 U68
Timur Tabi2ad6b512006-10-31 18:44:42 -060036
37 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
38*/
39
40#ifndef __CONFIG_H
41#define __CONFIG_H
42
Kim Phillipsfdfaa292015-03-17 12:00:45 -050043#define CONFIG_SYS_GENERIC_BOARD
44#define CONFIG_DISPLAY_BOARDINFO
45
Wolfgang Denk14d0a022010-10-07 21:51:12 +020046#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_LOWBOOT
Timur Tabi7a78f142007-01-31 15:54:29 -060048#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -060049
50/*
51 * High Level Configuration Options
52 */
Peter Tyser2c7920a2009-05-22 17:23:25 -050053#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
Timur Tabi2ad6b512006-10-31 18:44:42 -060054#define CONFIG_MPC8349 /* MPC8349 specific */
55
Wolfgang Denk2ae18242010-10-06 09:05:45 +020056#ifndef CONFIG_SYS_TEXT_BASE
57#define CONFIG_SYS_TEXT_BASE 0xFEF00000
58#endif
59
Joe Hershberger396abba2011-10-11 23:57:15 -050060#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
Timur Tabi2ad6b512006-10-31 18:44:42 -060061
Timur Tabi89c77842008-02-08 13:15:55 -060062#define CONFIG_MISC_INIT_F
63#define CONFIG_MISC_INIT_R
Timur Tabi7a78f142007-01-31 15:54:29 -060064
Timur Tabi89c77842008-02-08 13:15:55 -060065/*
66 * On-board devices
67 */
Timur Tabi7a78f142007-01-31 15:54:29 -060068
69#ifdef CONFIG_MPC8349ITX
Joe Hershberger396abba2011-10-11 23:57:15 -050070/* The CF card interface on the back of the board */
71#define CONFIG_COMPACT_FLASH
Timur Tabi89c77842008-02-08 13:15:55 -060072#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +020073#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
Valeriy Glushkovc31e1322009-06-30 15:48:41 +030074#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
Timur Tabi7a78f142007-01-31 15:54:29 -060075#endif
76
77#define CONFIG_PCI
Timur Tabi2ad6b512006-10-31 18:44:42 -060078#define CONFIG_RTC_DS1337
Heiko Schocher00f792e2012-10-24 13:48:22 +020079#define CONFIG_SYS_I2C
Timur Tabi7a78f142007-01-31 15:54:29 -060080#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
81
82/*
83 * Device configurations
84 */
Timur Tabi2ad6b512006-10-31 18:44:42 -060085
86/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +020087#ifdef CONFIG_SYS_I2C
88#define CONFIG_SYS_I2C_FSL
89#define CONFIG_SYS_FSL_I2C_SPEED 400000
90#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
91#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
92#define CONFIG_SYS_FSL_I2C2_SPEED 400000
93#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
94#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Timur Tabi2ad6b512006-10-31 18:44:42 -060095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +020097#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
Timur Tabi2ad6b512006-10-31 18:44:42 -060098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
100#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
101#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
102#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
103#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
Joe Hershberger396abba2011-10-11 23:57:15 -0500104#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
105#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600106
Timur Tabi2ad6b512006-10-31 18:44:42 -0600107/* Don't probe these addresses: */
Joe Hershberger396abba2011-10-11 23:57:15 -0500108#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
110 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
Joe Hershberger396abba2011-10-11 23:57:15 -0500111 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
Timur Tabi2ad6b512006-10-31 18:44:42 -0600112/* Bit definitions for the 8574[A] I2C expander */
Joe Hershberger396abba2011-10-11 23:57:15 -0500113 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
114#define I2C_8574_REVISION 0x03
Timur Tabi2ad6b512006-10-31 18:44:42 -0600115#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
116#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
117#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
118#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
119
Timur Tabi2ad6b512006-10-31 18:44:42 -0600120#endif
121
Timur Tabi7a78f142007-01-31 15:54:29 -0600122/* Compact Flash */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600123#ifdef CONFIG_COMPACT_FLASH
124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_IDE_MAXBUS 1
126#define CONFIG_SYS_IDE_MAXDEVICE 1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
129#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
130#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
131#define CONFIG_SYS_ATA_REG_OFFSET 0
132#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
133#define CONFIG_SYS_ATA_STRIDE 2
Timur Tabi2ad6b512006-10-31 18:44:42 -0600134
Joe Hershberger396abba2011-10-11 23:57:15 -0500135/* If a CF card is not inserted, time out quickly */
136#define ATA_RESET_TIME 1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600137
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200138#endif
139
140/*
141 * SATA
142 */
143#ifdef CONFIG_SATA_SIL3114
144
145#define CONFIG_SYS_SATA_MAX_DEVICE 4
146#define CONFIG_LIBATA
147#define CONFIG_LBA48
Timur Tabi2ad6b512006-10-31 18:44:42 -0600148
Timur Tabi7a78f142007-01-31 15:54:29 -0600149#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -0600150
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300151#ifdef CONFIG_SYS_USB_HOST
152/*
153 * Support USB
154 */
155#define CONFIG_CMD_USB
156#define CONFIG_USB_STORAGE
157#define CONFIG_USB_EHCI
158#define CONFIG_USB_EHCI_FSL
159
160/* Current USB implementation supports the only USB controller,
161 * so we have to choose between the MPH or the DR ones */
162#if 1
163#define CONFIG_HAS_FSL_MPH_USB
164#else
165#define CONFIG_HAS_FSL_DR_USB
166#endif
167
168#endif
169
Timur Tabi7a78f142007-01-31 15:54:29 -0600170/*
171 * DDR Setup
172 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500173#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
175#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
176#define CONFIG_SYS_83XX_DDR_USES_CS0
Joe Hershberger396abba2011-10-11 23:57:15 -0500177#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_MEMTEST_END 0x2000
Timur Tabi7a78f142007-01-31 15:54:29 -0600179
Joe Hershberger396abba2011-10-11 23:57:15 -0500180#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
181 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
Timur Tabif64702b2007-04-30 13:59:50 -0500182
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +0200183#define CONFIG_VERY_BIG_RAM
184#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
185
Heiko Schocher00f792e2012-10-24 13:48:22 +0200186#ifdef CONFIG_SYS_I2C
Timur Tabi7a78f142007-01-31 15:54:29 -0600187#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
188#endif
189
Joe Hershberger396abba2011-10-11 23:57:15 -0500190/* No SPD? Then manually set up DDR parameters */
191#ifndef CONFIG_SPD_EEPROM
192 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
Joe Hershberger2e651b22011-10-11 23:57:31 -0500193 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger396abba2011-10-11 23:57:15 -0500194 | CSCONFIG_ROW_BIT_13 \
195 | CSCONFIG_COL_BIT_10)
Timur Tabi7a78f142007-01-31 15:54:29 -0600196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
198 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
Timur Tabi7a78f142007-01-31 15:54:29 -0600199#endif
200
201/*
202 *Flash on the Local Bus
203 */
204
Joe Hershberger396abba2011-10-11 23:57:15 -0500205#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
206#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
208#define CONFIG_SYS_FLASH_EMPTY_INFO
Joe Hershberger396abba2011-10-11 23:57:15 -0500209/* 127 64KB sectors + 8 8KB sectors per device */
210#define CONFIG_SYS_MAX_FLASH_SECT 135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
212#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
213#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Timur Tabi7a78f142007-01-31 15:54:29 -0600214
215/* The ITX has two flash chips, but the ITX-GP has only one. To support both
216boards, we say we have two, but don't display a message if we find only one. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_FLASH_QUIET_TEST
Joe Hershberger396abba2011-10-11 23:57:15 -0500218#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
219#define CONFIG_SYS_FLASH_BANKS_LIST \
220 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
221#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
Joe Hershberger396abba2011-10-11 23:57:15 -0500222#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Timur Tabi7a78f142007-01-31 15:54:29 -0600223
Timur Tabi89c77842008-02-08 13:15:55 -0600224/* Vitesse 7385 */
225
226#ifdef CONFIG_VSC7385_ENET
227
228#define CONFIG_TSEC2
229
230/* The flash address and size of the VSC7385 firmware image */
231#define CONFIG_VSC7385_IMAGE 0xFEFFE000
232#define CONFIG_VSC7385_IMAGE_SIZE 8192
233
234#endif
235
Timur Tabi7a78f142007-01-31 15:54:29 -0600236/*
237 * BRx, ORx, LBLAWBARx, and LBLAWARx
238 */
239
240/* Flash */
241
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500242#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
243 | BR_PS_16 \
244 | BR_MS_GPCM \
245 | BR_V)
246#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Joe Hershberger396abba2011-10-11 23:57:15 -0500247 | OR_UPM_XAM \
248 | OR_GPCM_CSNT \
249 | OR_GPCM_ACS_DIV2 \
250 | OR_GPCM_XACS \
251 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500252 | OR_GPCM_TRLX_SET \
253 | OR_GPCM_EHTR_SET \
Joe Hershberger396abba2011-10-11 23:57:15 -0500254 | OR_GPCM_EAD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500256#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
Timur Tabi7a78f142007-01-31 15:54:29 -0600257
258/* Vitesse 7385 */
259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_VSC7385_BASE 0xF8000000
Timur Tabi7a78f142007-01-31 15:54:29 -0600261
Timur Tabi89c77842008-02-08 13:15:55 -0600262#ifdef CONFIG_VSC7385_ENET
263
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500264#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
265 | BR_PS_8 \
266 | BR_MS_GPCM \
267 | BR_V)
Joe Hershberger396abba2011-10-11 23:57:15 -0500268#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
269 | OR_GPCM_CSNT \
270 | OR_GPCM_XACS \
271 | OR_GPCM_SCY_15 \
272 | OR_GPCM_SETA \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500273 | OR_GPCM_TRLX_SET \
274 | OR_GPCM_EHTR_SET \
Joe Hershberger396abba2011-10-11 23:57:15 -0500275 | OR_GPCM_EAD)
Timur Tabi7a78f142007-01-31 15:54:29 -0600276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
278#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
Timur Tabi7a78f142007-01-31 15:54:29 -0600279
280#endif
281
282/* LED */
283
Joe Hershberger396abba2011-10-11 23:57:15 -0500284#define CONFIG_SYS_LED_BASE 0xF9000000
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500285#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
286 | BR_PS_8 \
287 | BR_MS_GPCM \
288 | BR_V)
Joe Hershberger396abba2011-10-11 23:57:15 -0500289#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
290 | OR_GPCM_CSNT \
291 | OR_GPCM_ACS_DIV2 \
292 | OR_GPCM_XACS \
293 | OR_GPCM_SCY_9 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500294 | OR_GPCM_TRLX_SET \
295 | OR_GPCM_EHTR_SET \
Joe Hershberger396abba2011-10-11 23:57:15 -0500296 | OR_GPCM_EAD)
Timur Tabi7a78f142007-01-31 15:54:29 -0600297
298/* Compact Flash */
299
300#ifdef CONFIG_COMPACT_FLASH
301
Joe Hershberger396abba2011-10-11 23:57:15 -0500302#define CONFIG_SYS_CF_BASE 0xF0000000
Timur Tabi7a78f142007-01-31 15:54:29 -0600303
Joe Hershberger396abba2011-10-11 23:57:15 -0500304#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
305 | BR_PS_16 \
306 | BR_MS_UPMA \
307 | BR_V)
308#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
Timur Tabi7a78f142007-01-31 15:54:29 -0600309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
311#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
Timur Tabi7a78f142007-01-31 15:54:29 -0600312
313#endif
314
315/*
316 * U-Boot memory configuration
317 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200318#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600319
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
321#define CONFIG_SYS_RAMBOOT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600322#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#undef CONFIG_SYS_RAMBOOT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600324#endif
325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_INIT_RAM_LOCK
Joe Hershberger396abba2011-10-11 23:57:15 -0500327#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
328#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Timur Tabi2ad6b512006-10-31 18:44:42 -0600329
Joe Hershberger396abba2011-10-11 23:57:15 -0500330#define CONFIG_SYS_GBL_DATA_OFFSET \
331 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Timur Tabi2ad6b512006-10-31 18:44:42 -0600333
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Joe Hershberger396abba2011-10-11 23:57:15 -0500335#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Kim Phillipsc8a90642012-06-30 18:29:20 -0500336#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600337
338/*
339 * Local Bus LCRR and LBCR regs
340 * LCRR: DLL bypass, Clock divider is 4
341 * External Local Bus rate is
342 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
343 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500344#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
345#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_LBC_LBCR 0x00000000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600347
Joe Hershberger396abba2011-10-11 23:57:15 -0500348 /* LB sdram refresh timer, about 6us */
349#define CONFIG_SYS_LBC_LSRT 0x32000000
350 /* LB refresh timer prescal, 266MHz/32*/
351#define CONFIG_SYS_LBC_MRTPR 0x20000000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600352
353/*
Timur Tabi2ad6b512006-10-31 18:44:42 -0600354 * Serial Port
355 */
356#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_NS16550
358#define CONFIG_SYS_NS16550_SERIAL
359#define CONFIG_SYS_NS16550_REG_SIZE 1
360#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600361
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger396abba2011-10-11 23:57:15 -0500363 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Timur Tabi7a78f142007-01-31 15:54:29 -0600364
Nikita V. Youshchenko8a364f02007-05-23 12:45:25 +0400365#define CONFIG_CONSOLE ttyS0
Timur Tabi7a78f142007-01-31 15:54:29 -0600366#define CONFIG_BAUDRATE 115200
Timur Tabi2ad6b512006-10-31 18:44:42 -0600367
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
369#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600370
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600371/* pass open firmware flat tree */
Kim Phillips35cc4e42007-08-15 22:30:39 -0500372#define CONFIG_OF_LIBFDT 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600373#define CONFIG_OF_BOARD_SETUP 1
374#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600375
Timur Tabi7a78f142007-01-31 15:54:29 -0600376/*
377 * PCI
378 */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600379#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000380#define CONFIG_PCI_INDIRECT_BRIDGE
Timur Tabi2ad6b512006-10-31 18:44:42 -0600381
382#define CONFIG_MPC83XX_PCI2
383
384/*
385 * General PCI
386 * Addresses are mapped 1-1.
387 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
389#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
390#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500391#define CONFIG_SYS_PCI1_MMIO_BASE \
392 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
394#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500395#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
396#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
397#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600398
399#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger396abba2011-10-11 23:57:15 -0500400#define CONFIG_SYS_PCI2_MEM_BASE \
401 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
403#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500404#define CONFIG_SYS_PCI2_MMIO_BASE \
405 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
407#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger396abba2011-10-11 23:57:15 -0500408#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
409#define CONFIG_SYS_PCI2_IO_PHYS \
410 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
411#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600412#endif
413
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100414#define CONFIG_PCI_PNP /* do pci plug-and-play */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600415
Timur Tabi2ad6b512006-10-31 18:44:42 -0600416#ifndef CONFIG_PCI_PNP
417 #define PCI_ENET0_IOADDR 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
Timur Tabi2ad6b512006-10-31 18:44:42 -0600419 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
420#endif
421
422#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
423
424#endif
425
Wolfgang Denk2ae18242010-10-06 09:05:45 +0200426#define CONFIG_PCI_66M
427#ifdef CONFIG_PCI_66M
Timur Tabi7a78f142007-01-31 15:54:29 -0600428#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
429#else
430#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
431#endif
432
Timur Tabi2ad6b512006-10-31 18:44:42 -0600433/* TSEC */
434
435#ifdef CONFIG_TSEC_ENET
436
Timur Tabi2ad6b512006-10-31 18:44:42 -0600437#define CONFIG_MII
Jon Loeliger659e2f62007-07-10 09:10:49 -0500438#define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600439
Kim Phillips255a35772007-05-16 16:52:19 -0500440#define CONFIG_TSEC1
Timur Tabi2ad6b512006-10-31 18:44:42 -0600441
Kim Phillips255a35772007-05-16 16:52:19 -0500442#ifdef CONFIG_TSEC1
Andy Fleming10327dc2007-08-16 16:35:02 -0500443#define CONFIG_HAS_ETH0
Kim Phillips255a35772007-05-16 16:52:19 -0500444#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100446#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600447#define TSEC1_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500448#define TSEC1_FLAGS TSEC_GIGABIT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600449#endif
450
Kim Phillips255a35772007-05-16 16:52:19 -0500451#ifdef CONFIG_TSEC2
Timur Tabi7a78f142007-01-31 15:54:29 -0600452#define CONFIG_HAS_ETH1
Kim Phillips255a35772007-05-16 16:52:19 -0500453#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200454#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi89c77842008-02-08 13:15:55 -0600455
Timur Tabi2ad6b512006-10-31 18:44:42 -0600456#define TSEC2_PHY_ADDR 4
457#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500458#define TSEC2_FLAGS TSEC_GIGABIT
Timur Tabi2ad6b512006-10-31 18:44:42 -0600459#endif
460
461#define CONFIG_ETHPRIME "Freescale TSEC"
462
463#endif
464
Timur Tabi2ad6b512006-10-31 18:44:42 -0600465/*
466 * Environment
467 */
Timur Tabi7a78f142007-01-31 15:54:29 -0600468#define CONFIG_ENV_OVERWRITE
469
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200471 #define CONFIG_ENV_IS_IN_FLASH
Joe Hershberger396abba2011-10-11 23:57:15 -0500472 #define CONFIG_ENV_ADDR \
473 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200474 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
Joe Hershberger396abba2011-10-11 23:57:15 -0500475 #define CONFIG_ENV_SIZE 0x2000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600476#else
Joe Hershberger396abba2011-10-11 23:57:15 -0500477 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200478 #undef CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200479 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
Joe Hershberger396abba2011-10-11 23:57:15 -0500480 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
481 #define CONFIG_ENV_SIZE 0x2000
Timur Tabi2ad6b512006-10-31 18:44:42 -0600482#endif
483
484#define CONFIG_LOADS_ECHO /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600486
Jon Loeliger8ea54992007-07-04 22:30:06 -0500487/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500488 * BOOTP options
489 */
490#define CONFIG_BOOTP_BOOTFILESIZE
491#define CONFIG_BOOTP_BOOTPATH
492#define CONFIG_BOOTP_GATEWAY
493#define CONFIG_BOOTP_HOSTNAME
494
495
496/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500497 * Command line configuration.
498 */
Jon Loeliger8ea54992007-07-04 22:30:06 -0500499#define CONFIG_CMD_CACHE
500#define CONFIG_CMD_DATE
501#define CONFIG_CMD_IRQ
Jon Loeliger8ea54992007-07-04 22:30:06 -0500502#define CONFIG_CMD_PING
Valeriy Glushkovb7be63a2009-02-04 18:27:49 +0200503#define CONFIG_CMD_DHCP
Jon Loeliger8ea54992007-07-04 22:30:06 -0500504#define CONFIG_CMD_SDRAM
Timur Tabi2ad6b512006-10-31 18:44:42 -0600505
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300506#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
Joe Hershberger396abba2011-10-11 23:57:15 -0500507 || defined(CONFIG_USB_STORAGE)
508 #define CONFIG_DOS_PARTITION
509 #define CONFIG_CMD_FAT
510 #define CONFIG_SUPPORT_VFAT
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200511#endif
512
Timur Tabi2ad6b512006-10-31 18:44:42 -0600513#ifdef CONFIG_COMPACT_FLASH
Joe Hershberger396abba2011-10-11 23:57:15 -0500514 #define CONFIG_CMD_IDE
Valeriy Glushkovc9e34fe2009-02-05 14:35:21 +0200515#endif
516
517#ifdef CONFIG_SATA_SIL3114
Joe Hershberger396abba2011-10-11 23:57:15 -0500518 #define CONFIG_CMD_SATA
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300519#endif
520
521#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
Joe Hershberger396abba2011-10-11 23:57:15 -0500522 #define CONFIG_CMD_EXT2
Timur Tabi2ad6b512006-10-31 18:44:42 -0600523#endif
524
525#ifdef CONFIG_PCI
Joe Hershberger396abba2011-10-11 23:57:15 -0500526 #define CONFIG_CMD_PCI
Timur Tabi2ad6b512006-10-31 18:44:42 -0600527#endif
528
Heiko Schocher00f792e2012-10-24 13:48:22 +0200529#ifdef CONFIG_SYS_I2C
Joe Hershberger396abba2011-10-11 23:57:15 -0500530 #define CONFIG_CMD_I2C
Timur Tabi2ad6b512006-10-31 18:44:42 -0600531#endif
532
Timur Tabi2ad6b512006-10-31 18:44:42 -0600533/* Watchdog */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600534#undef CONFIG_WATCHDOG /* watchdog disabled */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600535
536/*
537 * Miscellaneous configurable options
538 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500539#define CONFIG_SYS_LONGHELP /* undef to save memory */
540#define CONFIG_CMDLINE_EDITING /* Command-line editing */
541#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
542#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
Timur Tabi7a78f142007-01-31 15:54:29 -0600543
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kim Phillips05f91a62009-08-26 21:27:37 -0500545#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Timur Tabi7a78f142007-01-31 15:54:29 -0600546
547#ifdef CONFIG_MPC8349ITX
Joe Hershberger396abba2011-10-11 23:57:15 -0500548#define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
Timur Tabi7a78f142007-01-31 15:54:29 -0600549#else
Joe Hershberger396abba2011-10-11 23:57:15 -0500550#define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
Timur Tabi7a78f142007-01-31 15:54:29 -0600551#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -0600552
Jon Loeliger8ea54992007-07-04 22:30:06 -0500553#if defined(CONFIG_CMD_KGDB)
Joe Hershberger396abba2011-10-11 23:57:15 -0500554 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600555#else
Joe Hershberger396abba2011-10-11 23:57:15 -0500556 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600557#endif
558
Joe Hershberger396abba2011-10-11 23:57:15 -0500559 /* Print Buffer Size */
560#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
561#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
562 /* Boot Argument Buffer Size */
563#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Timur Tabi2ad6b512006-10-31 18:44:42 -0600564
565/*
566 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700567 * have to be in the first 256 MB of memory, since this is
Timur Tabi2ad6b512006-10-31 18:44:42 -0600568 * the maximum mapped by the Linux kernel during initialization.
569 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500570 /* Initial Memory map for Linux*/
571#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600572
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200573#define CONFIG_SYS_HRCW_LOW (\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600574 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
575 HRCWL_DDR_TO_SCB_CLK_1X1 |\
576 HRCWL_CSB_TO_CLKIN_4X1 |\
577 HRCWL_VCO_1X2 |\
578 HRCWL_CORE_TO_CSB_2X1)
579
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200580#ifdef CONFIG_SYS_LOWBOOT
581#define CONFIG_SYS_HRCW_HIGH (\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600582 HRCWH_PCI_HOST |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600583 HRCWH_32_BIT_PCI |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600584 HRCWH_PCI1_ARBITER_ENABLE |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600585 HRCWH_PCI2_ARBITER_ENABLE |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600586 HRCWH_CORE_ENABLE |\
587 HRCWH_FROM_0X00000100 |\
588 HRCWH_BOOTSEQ_DISABLE |\
589 HRCWH_SW_WATCHDOG_DISABLE |\
590 HRCWH_ROM_LOC_LOCAL_16BIT |\
591 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger396abba2011-10-11 23:57:15 -0500592 HRCWH_TSEC2M_IN_GMII)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600593#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200594#define CONFIG_SYS_HRCW_HIGH (\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600595 HRCWH_PCI_HOST |\
596 HRCWH_32_BIT_PCI |\
597 HRCWH_PCI1_ARBITER_ENABLE |\
Timur Tabi7a78f142007-01-31 15:54:29 -0600598 HRCWH_PCI2_ARBITER_ENABLE |\
Timur Tabi2ad6b512006-10-31 18:44:42 -0600599 HRCWH_CORE_ENABLE |\
600 HRCWH_FROM_0XFFF00100 |\
601 HRCWH_BOOTSEQ_DISABLE |\
602 HRCWH_SW_WATCHDOG_DISABLE |\
603 HRCWH_ROM_LOC_LOCAL_16BIT |\
604 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger396abba2011-10-11 23:57:15 -0500605 HRCWH_TSEC2M_IN_GMII)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600606#endif
607
Timur Tabi7a78f142007-01-31 15:54:29 -0600608/*
609 * System performance
610 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200611#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
Joe Hershberger396abba2011-10-11 23:57:15 -0500612#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200613#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
614#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
615#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
616#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
Valeriy Glushkovc31e1322009-06-30 15:48:41 +0300617#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
618#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600619
Timur Tabi7a78f142007-01-31 15:54:29 -0600620/*
621 * System IO Config
622 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500623/* Needed for gigabit to work on TSEC 1 */
624#define CONFIG_SYS_SICRH SICRH_TSOBI1
625 /* USB DR as device + USB MPH as host */
626#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600627
Kim Phillips1a2e2032010-04-20 19:37:54 -0500628#define CONFIG_SYS_HID0_INIT 0x00000000
629#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
Timur Tabi2ad6b512006-10-31 18:44:42 -0600630
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200631#define CONFIG_SYS_HID2 HID2_HBE
Becky Bruce31d82672008-05-08 19:02:12 -0500632#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600633
Timur Tabi7a78f142007-01-31 15:54:29 -0600634/* DDR */
Joe Hershberger396abba2011-10-11 23:57:15 -0500635#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500636 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500637 | BATL_MEMCOHERENCE)
638#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
639 | BATU_BL_256M \
640 | BATU_VS \
641 | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600642
Timur Tabi7a78f142007-01-31 15:54:29 -0600643/* PCI */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600644#ifdef CONFIG_PCI
Joe Hershberger396abba2011-10-11 23:57:15 -0500645#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500646 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500647 | BATL_MEMCOHERENCE)
648#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
649 | BATU_BL_256M \
650 | BATU_VS \
651 | BATU_VP)
652#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500653 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500654 | BATL_CACHEINHIBIT \
655 | BATL_GUARDEDSTORAGE)
656#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
657 | BATU_BL_256M \
658 | BATU_VS \
659 | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600660#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200661#define CONFIG_SYS_IBAT1L 0
662#define CONFIG_SYS_IBAT1U 0
663#define CONFIG_SYS_IBAT2L 0
664#define CONFIG_SYS_IBAT2U 0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600665#endif
666
667#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger396abba2011-10-11 23:57:15 -0500668#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500669 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500670 | BATL_MEMCOHERENCE)
671#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
672 | BATU_BL_256M \
673 | BATU_VS \
674 | BATU_VP)
675#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500676 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500677 | BATL_CACHEINHIBIT \
678 | BATL_GUARDEDSTORAGE)
679#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
680 | BATU_BL_256M \
681 | BATU_VS \
682 | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600683#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200684#define CONFIG_SYS_IBAT3L 0
685#define CONFIG_SYS_IBAT3U 0
686#define CONFIG_SYS_IBAT4L 0
687#define CONFIG_SYS_IBAT4U 0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600688#endif
689
690/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500691#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500692 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500693 | BATL_CACHEINHIBIT \
694 | BATL_GUARDEDSTORAGE)
695#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
696 | BATU_BL_256M \
697 | BATU_VS \
698 | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600699
700/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Joe Hershberger396abba2011-10-11 23:57:15 -0500701#define CONFIG_SYS_IBAT6L (0xF0000000 \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500702 | BATL_PP_RW \
Joe Hershberger396abba2011-10-11 23:57:15 -0500703 | BATL_MEMCOHERENCE \
704 | BATL_GUARDEDSTORAGE)
705#define CONFIG_SYS_IBAT6U (0xF0000000 \
706 | BATU_BL_256M \
707 | BATU_VS \
708 | BATU_VP)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600709
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200710#define CONFIG_SYS_IBAT7L 0
711#define CONFIG_SYS_IBAT7U 0
Timur Tabi2ad6b512006-10-31 18:44:42 -0600712
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200713#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
714#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
715#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
716#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
717#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
718#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
719#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
720#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
721#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
722#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
723#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
724#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
725#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
726#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
727#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
728#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Timur Tabi2ad6b512006-10-31 18:44:42 -0600729
Jon Loeliger8ea54992007-07-04 22:30:06 -0500730#if defined(CONFIG_CMD_KGDB)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600731#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600732#endif
733
734
735/*
736 * Environment Configuration
737 */
738#define CONFIG_ENV_OVERWRITE
739
Joe Hershberger396abba2011-10-11 23:57:15 -0500740#define CONFIG_NETDEV "eth0"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600741
Timur Tabi7a78f142007-01-31 15:54:29 -0600742#ifdef CONFIG_MPC8349ITX
Joe Hershberger396abba2011-10-11 23:57:15 -0500743#define CONFIG_HOSTNAME "mpc8349emitx"
Timur Tabi7a78f142007-01-31 15:54:29 -0600744#else
Joe Hershberger396abba2011-10-11 23:57:15 -0500745#define CONFIG_HOSTNAME "mpc8349emitxgp"
Timur Tabi7a78f142007-01-31 15:54:29 -0600746#endif
747
748/* Default path and filenames */
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000749#define CONFIG_ROOTPATH "/nfsroot/rootfs"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000750#define CONFIG_BOOTFILE "uImage"
Joe Hershberger396abba2011-10-11 23:57:15 -0500751 /* U-Boot image on TFTP server */
752#define CONFIG_UBOOTPATH "u-boot.bin"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600753
Timur Tabi7a78f142007-01-31 15:54:29 -0600754#ifdef CONFIG_MPC8349ITX
Joe Hershberger396abba2011-10-11 23:57:15 -0500755#define CONFIG_FDTFILE "mpc8349emitx.dtb"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600756#else
Joe Hershberger396abba2011-10-11 23:57:15 -0500757#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600758#endif
759
Kim Phillips05f91a62009-08-26 21:27:37 -0500760#define CONFIG_BOOTDELAY 6
Timur Tabi7a78f142007-01-31 15:54:29 -0600761
Timur Tabi98883332006-10-31 19:14:41 -0600762#define CONFIG_BOOTARGS \
763 "root=/dev/nfs rw" \
Marek Vasut5368c552012-09-23 17:41:24 +0200764 " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
765 " ip=" __stringify(CONFIG_IPADDR) ":" \
766 __stringify(CONFIG_SERVERIP) ":" \
767 __stringify(CONFIG_GATEWAYIP) ":" \
768 __stringify(CONFIG_NETMASK) ":" \
Joe Hershberger396abba2011-10-11 23:57:15 -0500769 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
Marek Vasut5368c552012-09-23 17:41:24 +0200770 " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE)
Timur Tabi98883332006-10-31 19:14:41 -0600771
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100772#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200773 "console=" __stringify(CONFIG_CONSOLE) "\0" \
Joe Hershberger396abba2011-10-11 23:57:15 -0500774 "netdev=" CONFIG_NETDEV "\0" \
775 "uboot=" CONFIG_UBOOTPATH "\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200776 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut5368c552012-09-23 17:41:24 +0200777 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
778 " +$filesize; " \
779 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
780 " +$filesize; " \
781 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
782 " $filesize; " \
783 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
784 " +$filesize; " \
785 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
786 " $filesize\0" \
Kim Phillips05f91a62009-08-26 21:27:37 -0500787 "fdtaddr=780000\0" \
Joe Hershberger396abba2011-10-11 23:57:15 -0500788 "fdtfile=" CONFIG_FDTFILE "\0"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600789
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100790#define CONFIG_NFSBOOTCOMMAND \
Timur Tabi7a78f142007-01-31 15:54:29 -0600791 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
Joe Hershberger396abba2011-10-11 23:57:15 -0500792 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
Timur Tabi7a78f142007-01-31 15:54:29 -0600793 " console=$console,$baudrate $othbootargs; " \
794 "tftp $loadaddr $bootfile;" \
795 "tftp $fdtaddr $fdtfile;" \
796 "bootm $loadaddr - $fdtaddr"
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600797
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100798#define CONFIG_RAMBOOTCOMMAND \
Timur Tabi7a78f142007-01-31 15:54:29 -0600799 "setenv bootargs root=/dev/ram rw" \
800 " console=$console,$baudrate $othbootargs; " \
801 "tftp $ramdiskaddr $ramdiskfile;" \
802 "tftp $loadaddr $bootfile;" \
803 "tftp $fdtaddr $fdtfile;" \
804 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Timur Tabi2ad6b512006-10-31 18:44:42 -0600805
Timur Tabi2ad6b512006-10-31 18:44:42 -0600806#endif