blob: e60e753e40547b340c9249fb0bed30cebd80a537 [file] [log] [blame]
Heiko Schochereaf8c982014-01-25 07:53:48 +01001/*
2 * (C) Copyright 2013
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * Based on:
6 * Copyright (c) 2011 IDS GmbH, Germany
7 * Sergej Stepanov <ste@ids.de>
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 */
18#define CONFIG_MPC831x
19#define CONFIG_MPC8313
20#define CONFIG_IDS8313
21
Heiko Schocher03838052014-06-22 06:33:30 +020022#define CONFIG_SYS_GENERIC_BOARD
23
Heiko Schochereaf8c982014-01-25 07:53:48 +010024#define CONFIG_FSL_ELBC
25
26#define CONFIG_MISC_INIT_R
27
Heiko Schochereaf8c982014-01-25 07:53:48 +010028#define CONFIG_BOOT_RETRY_TIME 900
29#define CONFIG_BOOT_RETRY_MIN 30
30#define CONFIG_BOOTDELAY 1
31#define CONFIG_RESET_TO_RETRY
32
33#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
34#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
35
36#define CONFIG_SYS_IMMR 0xF0000000
37
38#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
39#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
40
41/*
42 * Hardware Reset Configuration Word
43 * if CLKIN is 66.000MHz, then
44 * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
45 */
46#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
47 HRCWL_DDR_TO_SCB_CLK_2X1 |\
48 HRCWL_CSB_TO_CLKIN_2X1 |\
49 HRCWL_CORE_TO_CSB_2X1)
50
51#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\
52 HRCWH_CORE_ENABLE |\
53 HRCWH_FROM_0XFFF00100 |\
54 HRCWH_BOOTSEQ_DISABLE |\
55 HRCWH_SW_WATCHDOG_DISABLE |\
56 HRCWH_ROM_LOC_LOCAL_8BIT |\
57 HRCWH_RL_EXT_LEGACY |\
58 HRCWH_TSEC1M_IN_MII |\
59 HRCWH_TSEC2M_IN_MII |\
60 HRCWH_BIG_ENDIAN)
61
62#define CONFIG_SYS_SICRH 0x00000000
63#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
64
65#define CONFIG_HWCONFIG
66
67#define CONFIG_SYS_HID0_INIT 0x000000000
68#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\
69 HID0_ENABLE_INSTRUCTION_CACHE |\
70 HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
71
72#define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
73
74/*
75 * Definitions for initial stack pointer and data area (in DCACHE )
76 */
77#define CONFIG_SYS_INIT_RAM_LOCK
78#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
79#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
80#define CONFIG_SYS_GBL_DATA_SIZE 0x100
81#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
82 - CONFIG_SYS_GBL_DATA_SIZE)
83#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
84
85/*
86 * Local Bus LCRR and LBCR regs
87 */
88#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
89#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
90#define CONFIG_SYS_LBC_LBCR (0x00040000 |\
91 (0xFF << LBCR_BMT_SHIFT) |\
92 0xF)
93
94#define CONFIG_SYS_LBC_MRTPR 0x20000000
95
96/*
97 * Internal Definitions
98 */
99/*
100 * DDR Setup
101 */
102#define CONFIG_SYS_DDR_BASE 0x00000000
103#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
104#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
105
106/*
107 * Manually set up DDR parameters,
108 * as this board has not the SPD connected to I2C.
109 */
110#define CONFIG_SYS_DDR_SIZE 256 /* MB */
111#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
112 0x00010000 |\
113 CSCONFIG_ROW_BIT_13 |\
114 CSCONFIG_COL_BIT_10)
115
116#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
117 CSCONFIG_BANK_BIT_3)
118
119#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
120#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
121 (3 << TIMING_CFG0_WRT_SHIFT) |\
122 (3 << TIMING_CFG0_RRT_SHIFT) |\
123 (3 << TIMING_CFG0_WWT_SHIFT) |\
124 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
125 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
126 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
127 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
128#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
129 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
130 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
131 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
132 (4 << TIMING_CFG1_REFREC_SHIFT) |\
133 (4 << TIMING_CFG1_WRREC_SHIFT) |\
134 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
135 (2 << TIMING_CFG1_WRTORD_SHIFT))
136#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
137 (5 << TIMING_CFG2_CPO_SHIFT) |\
138 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
139 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
140 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
141 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
142 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
143
144#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
145 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
146
147#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
148 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
149 SDRAM_CFG_DBW_32 |\
150 SDRAM_CFG_SDRAM_TYPE_DDR2)
151
152#define CONFIG_SYS_SDRAM_CFG2 0x00401000
153#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
154 (0x0242 << SDRAM_MODE_SD_SHIFT))
155#define CONFIG_SYS_DDR_MODE_2 0x00000000
156#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
157#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
158 DDRCDR_PZ_NOMZ |\
159 DDRCDR_NZ_NOMZ |\
160 DDRCDR_ODT |\
161 DDRCDR_M_ODR |\
162 DDRCDR_Q_DRN)
163
164/*
165 * on-board devices
166 */
167#define CONFIG_TSEC1
168#define CONFIG_TSEC2
169#define CONFIG_TSEC_ENET
Heiko Schochereaf8c982014-01-25 07:53:48 +0100170#define CONFIG_HARD_SPI
171#define CONFIG_HARD_I2C
172
173/*
174 * NOR FLASH setup
175 */
176#define CONFIG_SYS_FLASH_CFI
177#define CONFIG_FLASH_CFI_DRIVER
178#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
179#define CONFIG_FLASH_SHOW_PROGRESS 50
180#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
181
182#define CONFIG_SYS_FLASH_BASE 0xFF800000
183#define CONFIG_SYS_FLASH_SIZE 8
184#define CONFIG_SYS_FLASH_PROTECTION
185
186#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
187#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016
188
189#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
190 BR_PS_8 |\
191 BR_MS_GPCM |\
192 BR_V)
193
194#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
195 OR_GPCM_SCY_10 |\
196 OR_GPCM_EHTR |\
197 OR_GPCM_TRLX |\
198 OR_GPCM_CSNT |\
199 OR_GPCM_EAD)
200#define CONFIG_SYS_MAX_FLASH_BANKS 1
201#define CONFIG_SYS_MAX_FLASH_SECT 128
202
203#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
204#define CONFIG_SYS_FLASH_WRITE_TOUT 500
205
206/*
207 * NAND FLASH setup
208 */
209#define CONFIG_SYS_NAND_BASE 0xE1000000
210#define CONFIG_SYS_MAX_NAND_DEVICE 1
211#define CONFIG_SYS_NAND_MAX_CHIPS 1
Heiko Schochereaf8c982014-01-25 07:53:48 +0100212#define CONFIG_NAND_FSL_ELBC
213#define CONFIG_SYS_NAND_PAGE_SIZE (2048)
214#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
215#define NAND_CACHE_PAGES 64
216
217#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
218#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
219#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
220#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
221
222#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\
223 (2<<BR_DECC_SHIFT) |\
224 BR_PS_8 |\
225 BR_MS_FCM |\
226 BR_V)
227
228#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\
229 OR_FCM_PGS |\
230 OR_FCM_CSCT |\
231 OR_FCM_CST |\
232 OR_FCM_CHT |\
233 OR_FCM_SCY_4 |\
234 OR_FCM_TRLX |\
235 OR_FCM_EHTR |\
236 OR_FCM_RST)
237
238/*
239 * MRAM setup
240 */
241#define CONFIG_SYS_MRAM_BASE 0xE2000000
242#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
243#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE
244#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */
245
246#define CONFIG_SYS_OR_TIMING_MRAM
247
248#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\
249 BR_PS_8 |\
250 BR_MS_GPCM |\
251 BR_V)
252
253#define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74
254
255/*
256 * CPLD setup
257 */
258#define CONFIG_SYS_CPLD_BASE 0xE3000000
259#define CONFIG_SYS_CPLD_SIZE 0x8000
260#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE
261#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E
262
263#define CONFIG_SYS_OR_TIMING_MRAM
264
265#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\
266 BR_PS_8 |\
267 BR_MS_GPCM |\
268 BR_V)
269
270#define CONFIG_SYS_OR3_PRELIM 0xFFFF8814
271
272/*
273 * HW-Watchdog
274 */
275#define CONFIG_WATCHDOG 1
276#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
277
278/*
279 * I2C setup
280 */
281#define CONFIG_CMD_I2C
282#define CONFIG_SYS_I2C
283#define CONFIG_SYS_I2C_FSL
284#define CONFIG_SYS_FSL_I2C_SPEED 400000
285#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
286#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
287#define CONFIG_RTC_PCF8563
288#define CONFIG_SYS_I2C_RTC_ADDR 0x51
289
290/*
291 * SPI setup
292 */
293#ifdef CONFIG_HARD_SPI
294#define CONFIG_MPC8XXX_SPI
295#define CONFIG_CMD_SPI
296#define CONFIG_SYS_GPIO1_PRELIM
297#define CONFIG_SYS_GPIO1_DIR 0x00000001
298#define CONFIG_SYS_GPIO1_DAT 0x00000001
299#endif
300
301/*
302 * Ethernet setup
303 */
304#ifdef CONFIG_TSEC1
305#define CONFIG_HAS_ETH0
306#define CONFIG_TSEC1_NAME "TSEC0"
307#define CONFIG_SYS_TSEC1_OFFSET 0x24000
308#define TSEC1_PHY_ADDR 0x1
309#define TSEC1_FLAGS TSEC_GIGABIT
310#define TSEC1_PHYIDX 0
311#endif
312
313#ifdef CONFIG_TSEC2
314#define CONFIG_HAS_ETH1
315#define CONFIG_TSEC2_NAME "TSEC1"
316#define CONFIG_SYS_TSEC2_OFFSET 0x25000
317#define TSEC2_PHY_ADDR 0x3
318#define TSEC2_FLAGS TSEC_GIGABIT
319#define TSEC2_PHYIDX 0
320#endif
321#define CONFIG_ETHPRIME "TSEC1"
322
323/*
324 * Serial Port
325 */
326#define CONFIG_CONS_INDEX 1
327#define CONFIG_SYS_NS16550
328#define CONFIG_SYS_NS16550_SERIAL
329#define CONFIG_SYS_NS16550_REG_SIZE 1
330
331#define CONFIG_SYS_BAUDRATE_TABLE \
332 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
333#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
334#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
335#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
336
337#define CONFIG_HAS_FSL_DR_USB
338#define CONFIG_SYS_SCCR_USBDRCM 3
339
340/*
341 * BAT's
342 */
343#define CONFIG_HIGH_BATS
344
345/* DDR @ 0x00000000 */
346#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\
347 BATL_PP_10)
348#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\
349 BATU_BL_256M |\
350 BATU_VS |\
351 BATU_VP)
352#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
353#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
354
355/* Initial RAM @ 0xFD000000 */
356#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\
357 BATL_PP_10 |\
358 BATL_GUARDEDSTORAGE)
359#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\
360 BATU_BL_256K |\
361 BATU_VS |\
362 BATU_VP)
363#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
364#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
365
366/* FLASH @ 0xFF800000 */
367#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\
368 BATL_PP_10 |\
369 BATL_GUARDEDSTORAGE)
370#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\
371 BATU_BL_8M |\
372 BATU_VS |\
373 BATU_VP)
374#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\
375 BATL_PP_10 |\
376 BATL_CACHEINHIBIT |\
377 BATL_GUARDEDSTORAGE)
378#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
379
380#define CONFIG_SYS_IBAT3L (0)
381#define CONFIG_SYS_IBAT3U (0)
382#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
383#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
384
385#define CONFIG_SYS_IBAT4L (0)
386#define CONFIG_SYS_IBAT4U (0)
387#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
388#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
389
390/* IMMRBAR @ 0xF0000000 */
391#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\
392 BATL_PP_10 |\
393 BATL_CACHEINHIBIT |\
394 BATL_GUARDEDSTORAGE)
395#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\
396 BATU_BL_128M |\
397 BATU_VS |\
398 BATU_VP)
399#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
400#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
401
402/* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
403#define CONFIG_SYS_IBAT6L (0xE0000000 |\
404 BATL_PP_10 |\
405 BATL_GUARDEDSTORAGE)
406#define CONFIG_SYS_IBAT6U (0xE0000000 |\
407 BATU_BL_256M |\
408 BATU_VS |\
409 BATU_VP)
410#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
411#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
412
413#define CONFIG_SYS_IBAT7L (0)
414#define CONFIG_SYS_IBAT7U (0)
415#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
416#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
417
418/*
419 * U-Boot environment setup
420 */
Heiko Schochereaf8c982014-01-25 07:53:48 +0100421#define CONFIG_CMD_DHCP
422#define CONFIG_CMD_PING
Heiko Schochereaf8c982014-01-25 07:53:48 +0100423#define CONFIG_CMD_NAND
Heiko Schochereaf8c982014-01-25 07:53:48 +0100424#define CONFIG_CMD_SNTP
425#define CONFIG_CMD_MII
426#define CONFIG_CMD_DATE
427#define CONFIG_CMDLINE_EDITING
Heiko Schochereaf8c982014-01-25 07:53:48 +0100428#define CONFIG_CMD_JFFS2
429#define CONFIG_BOOTP_SUBNETMASK
430#define CONFIG_BOOTP_GATEWAY
431#define CONFIG_BOOTP_HOSTNAME
432#define CONFIG_BOOTP_BOOTPATH
433#define CONFIG_BOOTP_BOOTFILESIZE
434/* pass open firmware flat tree */
435#define CONFIG_OF_LIBFDT
436#define CONFIG_OF_BOARD_SETUP
437#define CONFIG_OF_STDOUT_VIA_ALIAS
438
439/*
440 * The reserved memory
441 */
442#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
443#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
444#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
445
446/*
447 * Environment Configuration
448 */
449#define CONFIG_ENV_IS_IN_FLASH
450#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
451 + CONFIG_SYS_MONITOR_LEN)
452#define CONFIG_ENV_SIZE 0x20000
453#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
454#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
455
456
457#define CONFIG_NETDEV eth1
458#define CONFIG_HOSTNAME ids8313
459#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
460#define CONFIG_BOOTFILE "ids8313/uImage"
461#define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
462#define CONFIG_FDTFILE "ids8313/ids8313.dtb"
463#define CONFIG_LOADADDR 0x400000
464#define CONFIG_CMD_ENV_FLAGS
465#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
466
467#define CONFIG_BAUDRATE 115200
Heiko Schochereaf8c982014-01-25 07:53:48 +0100468
469/* Initial Memory map for Linux*/
470#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
471
472/*
473 * Miscellaneous configurable options
474 */
475#define CONFIG_SYS_LONGHELP
Heiko Schochereaf8c982014-01-25 07:53:48 +0100476#define CONFIG_SYS_CBSIZE 1024
477#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
478 + sizeof(CONFIG_SYS_PROMPT)+16)
479#define CONFIG_SYS_MAXARGS 16
480#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
481#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
482#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
483
484#define CONFIG_SYS_MEMTEST_START 0x00001000
485#define CONFIG_SYS_MEMTEST_END 0x00C00000
486
487#define CONFIG_SYS_LOAD_ADDR 0x100000
488#define CONFIG_MII
489#define CONFIG_LOADS_ECHO
490#define CONFIG_TIMESTAMP
491#define CONFIG_PREBOOT "echo;" \
492 "echo Type \\\"run nfsboot\\\" " \
493 "to mount root filesystem over NFS;echo"
494#undef CONFIG_BOOTARGS
495#define CONFIG_BOOTCOMMAND "run boot_cramfs"
496#undef CONFIG_SYS_LOADS_BAUD_CHANGE
497
498#define CONFIG_JFFS2_NAND
499#define CONFIG_JFFS2_DEV "0"
500
501/* mtdparts command line support */
502#define CONFIG_CMD_MTDPARTS
503#define CONFIG_FLASH_CFI_MTD
504#define CONFIG_MTD_DEVICE
505#define MTDIDS_DEFAULT "nor0=ff800000.flash,nand0=e1000000.flash"
506#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:7m(dum)," \
507 "768k(BOOT-BIN)," \
508 "128k(BOOT-ENV),128k(BOOT-REDENV);" \
509 "e1000000.flash:-(ubi)"
510
511#define CONFIG_EXTRA_ENV_SETTINGS \
512 "netdev=" __stringify(CONFIG_NETDEV) "\0" \
513 "ethprime=TSEC1\0" \
514 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
515 "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
516 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
517 " +${filesize}; " \
518 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
519 " +${filesize}; " \
520 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
521 " ${filesize}; " \
522 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
523 " +${filesize}; " \
524 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
525 " ${filesize}\0" \
526 "console=ttyS0\0" \
527 "fdtaddr=0x780000\0" \
528 "kernel_addr=ff800000\0" \
529 "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
530 "setbootargs=setenv bootargs " \
531 "root=${rootdev} rw console=${console}," \
532 "${baudrate} ${othbootargs}\0" \
533 "setipargs=setenv bootargs root=${rootdev} rw " \
534 "nfsroot=${serverip}:${rootpath} " \
535 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
536 "${netmask}:${hostname}:${netdev}:off " \
537 "console=${console},${baudrate} ${othbootargs}\0" \
538 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
539 "mtdids=" MTDIDS_DEFAULT "\0" \
540 "mtdparts=" MTDPARTS_DEFAULT "\0" \
541 "\0"
542
543#define CONFIG_NFSBOOTCOMMAND \
544 "setenv rootdev /dev/nfs;" \
545 "run setipargs;run addmtd;" \
546 "tftp ${loadaddr} ${bootfile};" \
547 "tftp ${fdtaddr} ${fdtfile};" \
548 "fdt addr ${fdtaddr};" \
549 "bootm ${loadaddr} - ${fdtaddr}"
550
551/* UBI Support */
552#define CONFIG_CMD_NAND_TRIMFFS
553#define CONFIG_CMD_UBI
554#define CONFIG_CMD_UBIFS
555#define CONFIG_RBTREE
556#define CONFIG_LZO
557#define CONFIG_MTD_PARTITIONS
558
559/* bootcount support */
560#define CONFIG_BOOTCOUNT_LIMIT
561#define CONFIG_BOOTCOUNT_I2C
562#define CONFIG_BOOTCOUNT_ALEN 1
563#define CONFIG_SYS_BOOTCOUNT_ADDR 0x9
564
565#define CONFIG_VERSION_VARIABLE
566
Heiko Schocherd835e912014-05-28 11:33:34 +0200567#define CONFIG_IMAGE_FORMAT_LEGACY
Heiko Schochereaf8c982014-01-25 07:53:48 +0100568#define CONFIG_CMD_FDT
569#define CONFIG_CMD_HASH
Heiko Schochereaf8c982014-01-25 07:53:48 +0100570#define CONFIG_SHA1
571#define CONFIG_SHA256
Heiko Schochereaf8c982014-01-25 07:53:48 +0100572
573#endif /* __CONFIG_H */