blob: 15ee28414d3b3024a00368a365dc19d479347da2 [file] [log] [blame]
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +02001/*
2 * WORK Microwave work_92105 board configuration file
3 *
4 * (C) Copyright 2014 DENX Software Engineering GmbH
5 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_WORK_92105_H__
11#define __CONFIG_WORK_92105_H__
12
13/* SoC and board defines */
14#include <linux/sizes.h>
15#include <asm/arch/cpu.h>
16
17/*
18 * Define work_92105 machine type by hand -- done only for compatibility
19 * with original board code
20 */
21#define MACH_TYPE_WORK_92105 736
22#define CONFIG_MACH_TYPE MACH_TYPE_WORK_92105
23
24#define CONFIG_SYS_ICACHE_OFF
25#define CONFIG_SYS_DCACHE_OFF
26#if !defined(CONFIG_SPL_BUILD)
27#define CONFIG_SKIP_LOWLEVEL_INIT
28#endif
29#define CONFIG_BOARD_EARLY_INIT_F
30#define CONFIG_BOARD_EARLY_INIT_R
31
32/* generate LPC32XX-specific SPL image */
33#define CONFIG_LPC32XX_SPL
34
35/*
36 * Memory configurations
37 */
38#define CONFIG_NR_DRAM_BANKS 1
39#define CONFIG_SYS_MALLOC_LEN SZ_1M
40#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
41#define CONFIG_SYS_SDRAM_SIZE SZ_128M
42#define CONFIG_SYS_TEXT_BASE 0x80100000
43#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
44#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
45
46#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
47
48#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
49 - GENERATED_GBL_DATA_SIZE)
50
51/*
52 * Serial Driver
53 */
54#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */
55#define CONFIG_BAUDRATE 115200
56
57/*
58 * Ethernet Driver
59 */
60
61#define CONFIG_PHY_SMSC
62#define CONFIG_LPC32XX_ETH
63#define CONFIG_PHYLIB
64#define CONFIG_PHY_ADDR 0
65#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
66#define CONFIG_CMD_MII
67#define CONFIG_CMD_PING
68#define CONFIG_CMD_DHCP
69/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
70
71/*
72 * I2C driver
73 */
74
75#define CONFIG_SYS_I2C_LPC32XX
76#define CONFIG_SYS_I2C
77#define CONFIG_CMD_I2C
78#define CONFIG_SYS_I2C_SPEED 350000
79
80/*
81 * I2C EEPROM
82 */
83
84#define CONFIG_CMD_EEPROM
85#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
86#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
87
88/*
89 * I2C RTC
90 */
91
92#define CONFIG_CMD_DATE
93#define CONFIG_RTC_DS1374
94
95/*
96 * I2C Temperature Sensor (DTT)
97 */
98
99#define CONFIG_CMD_DTT
100#define CONFIG_DTT_SENSORS { 0, 1 }
101#define CONFIG_DTT_DS620
102
103/*
104 * U-Boot General Configurations
105 */
106#define CONFIG_SYS_GENERIC_BOARD
107#define CONFIG_SYS_LONGHELP
108#define CONFIG_SYS_CBSIZE 1024
109#define CONFIG_SYS_PBSIZE \
110 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
111#define CONFIG_SYS_MAXARGS 16
112#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
113
114#define CONFIG_SYS_HUSH_PARSER
115
116#define CONFIG_AUTO_COMPLETE
117#define CONFIG_CMDLINE_EDITING
118#define CONFIG_VERSION_VARIABLE
119#define CONFIG_DISPLAY_CPUINFO
120#define CONFIG_DOS_PARTITION
121
122/*
123 * No NOR
124 */
125
126#define CONFIG_SYS_NO_FLASH
127
128/*
129 * NAND chip timings for FIXME: which one?
130 */
131
132#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
133#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
134#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818
135#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000
136#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545
137#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
138#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
139
140/*
141 * NAND
142 */
143
144/* driver configuration */
145#define CONFIG_SYS_NAND_SELF_INIT
146#define CONFIG_SYS_MAX_NAND_DEVICE 1
147#define CONFIG_SYS_MAX_NAND_CHIPS 1
148#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
149#define CONFIG_NAND_LPC32XX_MLC
150
151#define CONFIG_CMD_NAND
152
153/*
154 * GPIO
155 */
156
157#define CONFIG_CMD_GPIO
158#define CONFIG_LPC32XX_GPIO
159
160/*
161 * SSP/SPI/DISPLAY
162 */
163
164#define CONFIG_CMD_SPI
165#define CONFIG_LPC32XX_SSP
166#define CONFIG_LPC32XX_SSP_TIMEOUT 100000
167#define CONFIG_CMD_MAX6957
168#define CONFIG_CMD_HD44760
169/*
170 * Environment
171 */
172
173#define CONFIG_ENV_IS_IN_NAND 1
174#define CONFIG_ENV_SIZE 0x00020000
175#define CONFIG_ENV_OFFSET 0x00100000
176#define CONFIG_ENV_OFFSET_REDUND 0x00120000
177#define CONFIG_ENV_ADDR 0x80000100
178
179/*
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +0200180 * Boot Linux
181 */
182#define CONFIG_CMDLINE_TAG
183#define CONFIG_SETUP_MEMORY_TAGS
184#define CONFIG_INITRD_TAG
185
186#define CONFIG_ZERO_BOOTDELAY_CHECK
187#define CONFIG_BOOTDELAY 3
188
189#define CONFIG_BOOTFILE "uImage"
190#define CONFIG_BOOTARGS "console=ttyS2,115200n8"
191#define CONFIG_LOADADDR 0x80008000
192
193/*
194 * SPL
195 */
196
197/* SPL will be executed at offset 0 */
198#define CONFIG_SPL_TEXT_BASE 0x00000000
199/* SPL will use SRAM as stack */
200#define CONFIG_SPL_STACK 0x0000FFF8
201#define CONFIG_SPL_BOARD_INIT
202/* Use the framework and generic lib */
203#define CONFIG_SPL_FRAMEWORK
204#define CONFIG_SPL_LIBGENERIC_SUPPORT
205#define CONFIG_SPL_LIBCOMMON_SUPPORT
206/* SPL will use serial */
207#define CONFIG_SPL_SERIAL_SUPPORT
208/* SPL will load U-Boot from NAND offset 0x40000 */
209#define CONFIG_SPL_NAND_SUPPORT
210#define CONFIG_SPL_NAND_DRIVERS
211#define CONFIG_SPL_NAND_BASE
212#define CONFIG_SPL_NAND_BOOT
213#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
214#define CONFIG_SPL_PAD_TO 0x20000
215/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
216#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
217#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
218#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
219
220/*
221 * Include SoC specific configuration
222 */
223#include <asm/arch/config.h>
224
225#endif /* __CONFIG_WORK_92105_H__*/