blob: 2404c6a8f0ef37962f19644925cc076b013730eb [file] [log] [blame]
Dave Liu7737d5c2006-11-03 12:11:15 -06001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
4 * Dave Liu <daveliu@freescale.com>
5 * based on source code of Shlomi Gridish
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __UCCF_H__
24#define __UCCF_H__
25
26#include "common.h"
27#include "qe.h"
Anton Vorontsovd77c7792009-09-16 23:21:55 +040028#include "asm/immap_qe.h"
Dave Liu7737d5c2006-11-03 12:11:15 -060029
30/* Fast or Giga ethernet
31*/
32typedef enum enet_type {
33 FAST_ETH,
34 GIGA_ETH,
35} enet_type_e;
36
37/* General UCC Extended Mode Register
38*/
39#define UCC_GUEMR_MODE_MASK_RX 0x02
40#define UCC_GUEMR_MODE_MASK_TX 0x01
41#define UCC_GUEMR_MODE_FAST_RX 0x02
42#define UCC_GUEMR_MODE_FAST_TX 0x01
43#define UCC_GUEMR_MODE_SLOW_RX 0x00
44#define UCC_GUEMR_MODE_SLOW_TX 0x00
45#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 must be set 1 */
46
47/* General UCC FAST Mode Register
48*/
49#define UCC_FAST_GUMR_TCI 0x20000000
50#define UCC_FAST_GUMR_TRX 0x10000000
51#define UCC_FAST_GUMR_TTX 0x08000000
52#define UCC_FAST_GUMR_CDP 0x04000000
53#define UCC_FAST_GUMR_CTSP 0x02000000
54#define UCC_FAST_GUMR_CDS 0x01000000
55#define UCC_FAST_GUMR_CTSS 0x00800000
56#define UCC_FAST_GUMR_TXSY 0x00020000
57#define UCC_FAST_GUMR_RSYN 0x00010000
58#define UCC_FAST_GUMR_RTSM 0x00002000
59#define UCC_FAST_GUMR_REVD 0x00000400
60#define UCC_FAST_GUMR_ENR 0x00000020
61#define UCC_FAST_GUMR_ENT 0x00000010
62
63/* GUMR [MODE] bit maps
64*/
65#define UCC_FAST_GUMR_HDLC 0x00000000
66#define UCC_FAST_GUMR_QMC 0x00000002
67#define UCC_FAST_GUMR_UART 0x00000004
68#define UCC_FAST_GUMR_BISYNC 0x00000008
69#define UCC_FAST_GUMR_ATM 0x0000000a
70#define UCC_FAST_GUMR_ETH 0x0000000c
71
72/* Transmit On Demand (UTORD)
73*/
74#define UCC_SLOW_TOD 0x8000
75#define UCC_FAST_TOD 0x8000
76
77/* Fast Ethernet (10/100 Mbps)
78*/
79#define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size */
80#define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */
81#define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */
82#define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size */
83#define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */
84#define UCC_GETH_UTFTT_INIT 128
85
86/* Gigabit Ethernet (1000 Mbps)
87*/
88#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual FIFO size */
89#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */
90#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */
91#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual FIFO size */
92#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */
93#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */
94
95/* UCC fast alignment
96*/
97#define UCC_FAST_RX_ALIGN 4
98#define UCC_FAST_MRBLR_ALIGNMENT 4
99#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
100
101/* Sizes
102*/
103#define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD 8
104
105/* UCC fast structure.
106*/
107typedef struct ucc_fast_info {
108 int ucc_num;
109 qe_clock_e rx_clock;
110 qe_clock_e tx_clock;
111 enet_type_e eth_type;
112} ucc_fast_info_t;
113
114typedef struct ucc_fast_private {
115 ucc_fast_info_t *uf_info;
116 ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs */
117 u32 *p_ucce; /* a pointer to the event register */
118 u32 *p_uccm; /* a pointer to the mask register */
119 int enabled_tx; /* whether UCC is enabled for Tx (ENT) */
120 int enabled_rx; /* whether UCC is enabled for Rx (ENR) */
121 u32 ucc_fast_tx_virtual_fifo_base_offset;
122 u32 ucc_fast_rx_virtual_fifo_base_offset;
123} ucc_fast_private_t;
124
125void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf);
126u32 ucc_fast_get_qe_cr_subblock(int ucc_num);
127void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode);
128void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode);
129int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret);
130
131#endif /* __UCCF_H__ */