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Stefan Roeseb79316f2005-08-15 12:31:23 +02001/*
2 * (C) Copyright 2004 Sandburst Corporation
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/************************************************************************
24 * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
Wolfgang Denk3d078ce2005-08-15 16:03:56 +020025 * design.
Stefan Roeseb79316f2005-08-15 12:31:23 +020026 ***********************************************************************/
27
28/*
29 * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
30 *
31 */
32
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
36/*-----------------------------------------------------------------------
37 * High Level Configuration Options
38 *----------------------------------------------------------------------*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +020039#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
40#define CONFIG_440GX 1 /* Specifc GX support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020041#define CONFIG_440 1 /* ... PPC440 family */
Wolfgang Denk3d078ce2005-08-15 16:03:56 +020042#define CONFIG_4xx 1 /* ... PPC4xx family */
Stefan Roeseb79316f2005-08-15 12:31:23 +020043#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Wolfgang Denk3d078ce2005-08-15 16:03:56 +020044#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
45#define CONFIG_MISC_INIT_R 1 /* Call board misc_init_r */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#undef CONFIG_SYS_DRAM_TEST /* Disable-takes long time!*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +020047#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
Stefan Roeseb79316f2005-08-15 12:31:23 +020048
49#define CONFIG_VERY_BIG_RAM 1
50#define CONFIG_VERSION_VARIABLE
51
52#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
53
54/*-----------------------------------------------------------------------
55 * Base addresses -- Note these are effective addresses where the
56 * actual resources get mapped (not physical addresses)
57 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
59#define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */
60#define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */
61#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
62#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
63#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
64#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
Stefan Roeseb79316f2005-08-15 12:31:23 +020065
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
67#define CONFIG_SYS_KAREF_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
68#define CONFIG_SYS_OFEM_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000)
69#define CONFIG_SYS_BME32_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
70#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
Stefan Roeseb79316f2005-08-15 12:31:23 +020071
72/* Here for completeness */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_OFEMAC_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000)
Stefan Roeseb79316f2005-08-15 12:31:23 +020074
75/*-----------------------------------------------------------------------
76 * Initial RAM & stack pointer (placed in internal SRAM)
77 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_TEMP_STACK_OCM 1
79#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
80#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
81#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
82#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
Stefan Roeseb79316f2005-08-15 12:31:23 +020083
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
85#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
86#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
Stefan Roeseb79316f2005-08-15 12:31:23 +020087
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Rsrv 256kB for Mon */
89#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Rsrv 128kB for malloc */
Stefan Roeseb79316f2005-08-15 12:31:23 +020090
91/*-----------------------------------------------------------------------
92 * Serial Port
93 *----------------------------------------------------------------------*/
94#undef CONFIG_SERIAL_SOFTWARE_FIFO
95#define CONFIG_SERIAL_MULTI 1
96#define CONFIG_BAUDRATE 9600
97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_BAUDRATE_TABLE \
Stefan Roeseb79316f2005-08-15 12:31:23 +020099 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
100
101/*-----------------------------------------------------------------------
102 * NVRAM/RTC
103 *
104 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
105 * The DS1743 code assumes this condition (i.e. -- it assumes the base
106 * address for the RTC registers is:
107 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108 * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
Stefan Roeseb79316f2005-08-15 12:31:23 +0200109 *
110 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200112#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200113
114/*-----------------------------------------------------------------------
115 * FLASH related
116 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
118#define CONFIG_SYS_MAX_FLASH_SECT 8 /* sectors per device */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#undef CONFIG_SYS_FLASH_CHECKSUM
121#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase TO (in ms) */
122#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO(in ms) */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200123
124/*-----------------------------------------------------------------------
125 * DDR SDRAM
126 *----------------------------------------------------------------------*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200127#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup*/
128#define SPD_EEPROM_ADDRESS {0x53} /* SPD i2c spd addresses */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200129
130/*-----------------------------------------------------------------------
131 * I2C
132 *----------------------------------------------------------------------*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200133#define CONFIG_HARD_I2C 1 /* I2C hardware support */
134#undef CONFIG_SOFT_I2C /* I2C !bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed 400kHz */
136#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
137#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200138#define CONFIG_I2C_BUS1 1 /* Include i2c bus 1 supp */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200139
140
141/*-----------------------------------------------------------------------
142 * Environment
143 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200144#define CONFIG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200145#undef CONFIG_ENV_IS_IN_FLASH /* ... not in flash */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200146#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200147#define CONFIG_ENV_OVERWRITE 1 /* allow env overwrite */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200148
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200149#define CONFIG_ENV_SIZE 0x1000 /* Size of Env vars */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE_ADDR)
Stefan Roeseb79316f2005-08-15 12:31:23 +0200151
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200152#define CONFIG_BOOTDELAY 5 /* 5 second autoboot */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200153
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200154#define CONFIG_LOADS_ECHO 1 /* echo on for serial dnld */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200156
157/*-----------------------------------------------------------------------
158 * Networking
159 *----------------------------------------------------------------------*/
Ben Warren96e21f82008-10-27 23:50:15 -0700160#define CONFIG_PPC4xx_EMAC
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200161#define CONFIG_MII 1 /* MII PHY management */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200162#define CONFIG_NET_MULTI 1
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200163#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
164#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
165#define CONFIG_PHY2_ADDR 0x08 /* PHY addr, MGMT, EMAC2 */
166#define CONFIG_PHY3_ADDR 0x18 /* PHY addr, LCL, EMAC3 */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200167#define CONFIG_HAS_ETH0
168#define CONFIG_HAS_ETH1
169#define CONFIG_HAS_ETH2
170#define CONFIG_HAS_ETH3
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200171#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200172#define CONFIG_CIS8201_PHY 1 /* RGMII mode for Cicada */
173#define CONFIG_CIS8201_SHORT_ETCH 1 /* Use short etch mode */
174#define CONFIG_PHY_GIGE 1 /* GbE speed/duplex detect */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200175#define CONFIG_PHY_RESET_DELAY 1000
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200176#define CONFIG_NETMASK 255.255.0.0
177#define CONFIG_ETHADDR 00:00:00:00:00:00 /* No EMAC 0 support */
178#define CONFIG_ETH1ADDR 00:00:00:00:00:00 /* No EMAC 1 support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200180
181
Jon Loeliger348f2582007-07-08 13:46:18 -0500182/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500183 * BOOTP options
184 */
185#define CONFIG_BOOTP_BOOTFILESIZE
186#define CONFIG_BOOTP_BOOTPATH
187#define CONFIG_BOOTP_GATEWAY
188#define CONFIG_BOOTP_HOSTNAME
189
190
191/*
Jon Loeliger348f2582007-07-08 13:46:18 -0500192 * Command line configuration.
193 */
194#include <config_cmd_default.h>
195
196#define CONFIG_CMD_PCI
197#define CONFIG_CMD_IRQ
198#define CONFIG_CMD_I2C
199#define CONFIG_CMD_DHCP
200#define CONFIG_CMD_DATE
201#define CONFIG_CMD_BEDBUG
202#define CONFIG_CMD_PING
203#define CONFIG_CMD_DIAG
204#define CONFIG_CMD_MII
205#define CONFIG_CMD_NET
206#define CONFIG_CMD_ELF
207#define CONFIG_CMD_IDE
208#define CONFIG_CMD_FAT
209
Stefan Roeseb79316f2005-08-15 12:31:23 +0200210
211/* Include NetConsole support */
212#define CONFIG_NETCONSOLE
213
214/* Include auto complete with tabs */
215#define CONFIG_AUTO_COMPLETE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_ALT_MEMTEST 1 /* use real memory test */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_LONGHELP /* undef to save memory */
219#define CONFIG_SYS_PROMPT "KaRefDes=> " /* Monitor Command Prompt */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_HUSH_PARSER 1 /* HUSH for ext'd cli */
222#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Stefan Roeseb79316f2005-08-15 12:31:23 +0200223
224
225/*-----------------------------------------------------------------------
226 * Console Buffer
227 *----------------------------------------------------------------------*/
Jon Loeliger348f2582007-07-08 13:46:18 -0500228#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200230#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200232#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200234 /* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
236#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200237
238/*-----------------------------------------------------------------------
239 * Memory Test
240 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
242#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200243
244/*-----------------------------------------------------------------------
245 * Compact Flash (in true IDE mode)
246 *----------------------------------------------------------------------*/
247#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
248#undef CONFIG_IDE_LED /* no led for ide supported */
249
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200250#define CONFIG_IDE_RESET /* reset for ide supported */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
252#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_ATA_BASE_ADDR 0xF0000000
255#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
256#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
257#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses*/
258#define CONFIG_SYS_ATA_ALT_OFFSET 0x100000 /* Offset for alternate registers */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_ATA_STRIDE 2 /* Directly connected CF, needs a stride
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200261 to get to the correct offset */
262#define CONFIG_DOS_PARTITION 1 /* Include dos partition */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200263
264/*-----------------------------------------------------------------------
265 * PCI
266 *----------------------------------------------------------------------*/
267/* General PCI */
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200268#define CONFIG_PCI /* include pci support */
269#define CONFIG_PCI_PNP /* do pci plug-and-play */
270#define CONFIG_PCI_SCAN_SHOW /* show pci devices */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_PCI_TARGBASE (CONFIG_SYS_PCI_MEMBASE)
Stefan Roeseb79316f2005-08-15 12:31:23 +0200272
273/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target*/
Stefan Roeseb79316f2005-08-15 12:31:23 +0200275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */
277#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200278
279/*
280 * For booting Linux, the board info and command line data
281 * have to be in the first 8 MB of memory, since this is
282 * the maximum mapped by the Linux kernel during initialization.
283 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200285
286/*
287 * Internal Definitions
288 *
289 * Boot Flags
290 */
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200291#define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */
292#define BOOTFLAG_WARM 0x02 /* Software reboot */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200293
Jon Loeliger348f2582007-07-08 13:46:18 -0500294#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200295#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */
296#define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200297#endif
298
299/*-----------------------------------------------------------------------
300 * Miscellaneous configurable options
301 *----------------------------------------------------------------------*/
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200302#undef CONFIG_WATCHDOG /* watchdog disabled */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_LOAD_ADDR 0x8000000 /* default load address */
304#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_HZ 100 /* decr freq: 1 ms ticks */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200307
308
309#endif /* __CONFIG_H */