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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek-jpeg-decoder.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek JPEG Decoder
8
9maintainers:
10 - Xia Jiang <xia.jiang@mediatek.com>
11
12description: |-
13 Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs
14
15properties:
16 compatible:
17 oneOf:
18 - items:
19 - enum:
20 - mediatek,mt8173-jpgdec
21 - mediatek,mt2701-jpgdec
22 - items:
23 - enum:
24 - mediatek,mt7623-jpgdec
25 - mediatek,mt8188-jpgdec
26 - const: mediatek,mt2701-jpgdec
27
28 reg:
29 maxItems: 1
30
31 interrupts:
32 maxItems: 1
33
34 clocks:
35 maxItems: 2
36 minItems: 2
37
38 clock-names:
39 items:
40 - const: jpgdec-smi
41 - const: jpgdec
42
43 power-domains:
44 maxItems: 1
45
46 iommus:
47 maxItems: 2
48 description: |
49 Points to the respective IOMMU block with master port as argument, see
50 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
51 Ports are according to the HW.
52
53required:
54 - compatible
55 - reg
56 - interrupts
57 - clocks
58 - clock-names
59 - power-domains
60 - iommus
61
62additionalProperties: false
63
64examples:
65 - |
66 #include <dt-bindings/clock/mt2701-clk.h>
67 #include <dt-bindings/interrupt-controller/arm-gic.h>
68 #include <dt-bindings/memory/mt2701-larb-port.h>
69 #include <dt-bindings/power/mt2701-power.h>
70 jpegdec: jpegdec@15004000 {
71 compatible = "mediatek,mt2701-jpgdec";
72 reg = <0x15004000 0x1000>;
73 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
74 clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
75 <&imgsys CLK_IMG_JPGDEC>;
76 clock-names = "jpgdec-smi",
77 "jpgdec";
78 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
79 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
80 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
81 };