| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Lantiq VRX200 and ARX300 PCIe PHY |
| 8 | |
| 9 | maintainers: |
| 10 | - Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
| 11 | |
| 12 | properties: |
| 13 | "#phy-cells": |
| 14 | const: 1 |
| 15 | description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h> |
| 16 | |
| 17 | compatible: |
| 18 | enum: |
| 19 | - lantiq,vrx200-pcie-phy |
| 20 | - lantiq,arx300-pcie-phy |
| 21 | |
| 22 | reg: |
| 23 | maxItems: 1 |
| 24 | |
| 25 | clocks: |
| 26 | items: |
| 27 | - description: PHY module clock |
| 28 | - description: PDI register clock |
| 29 | |
| 30 | clock-names: |
| 31 | items: |
| 32 | - const: phy |
| 33 | - const: pdi |
| 34 | |
| 35 | resets: |
| 36 | items: |
| 37 | - description: exclusive PHY reset line |
| 38 | - description: shared reset line between the PCIe PHY and PCIe controller |
| 39 | |
| 40 | reset-names: |
| 41 | items: |
| 42 | - const: phy |
| 43 | - const: pcie |
| 44 | |
| 45 | lantiq,rcu: |
| 46 | $ref: /schemas/types.yaml#/definitions/phandle |
| 47 | description: phandle to the RCU syscon |
| 48 | |
| 49 | lantiq,rcu-endian-offset: |
| 50 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 51 | description: the offset of the endian registers for this PHY instance in the RCU syscon |
| 52 | |
| 53 | lantiq,rcu-big-endian-mask: |
| 54 | $ref: /schemas/types.yaml#/definitions/uint32 |
| 55 | description: the mask to set the PDI (PHY) registers for this PHY instance to big endian |
| 56 | |
| 57 | big-endian: |
| 58 | description: Configures the PDI (PHY) registers in big-endian mode |
| 59 | type: boolean |
| 60 | |
| 61 | little-endian: |
| 62 | description: Configures the PDI (PHY) registers in big-endian mode |
| 63 | type: boolean |
| 64 | |
| 65 | required: |
| 66 | - "#phy-cells" |
| 67 | - compatible |
| 68 | - reg |
| 69 | - clocks |
| 70 | - clock-names |
| 71 | - resets |
| 72 | - reset-names |
| 73 | - lantiq,rcu |
| 74 | - lantiq,rcu-endian-offset |
| 75 | - lantiq,rcu-big-endian-mask |
| 76 | |
| 77 | additionalProperties: false |
| 78 | |
| 79 | examples: |
| 80 | - | |
| 81 | pcie0_phy: phy@106800 { |
| 82 | compatible = "lantiq,vrx200-pcie-phy"; |
| 83 | reg = <0x106800 0x100>; |
| 84 | lantiq,rcu = <&rcu0>; |
| 85 | lantiq,rcu-endian-offset = <0x4c>; |
| 86 | lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */ |
| 87 | big-endian; |
| 88 | clocks = <&pmu 32>, <&pmu 36>; |
| 89 | clock-names = "phy", "pdi"; |
| 90 | resets = <&reset0 12 24>, <&reset0 22 22>; |
| 91 | reset-names = "phy", "pcie"; |
| 92 | #phy-cells = <1>; |
| 93 | }; |
| 94 | |
| 95 | ... |