| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | TI Davinci DSP devices |
| 2 | ======================= |
| 3 | |
| 4 | Binding status: Unstable - Subject to changes for DT representation of clocks |
| 5 | and resets |
| 6 | |
| 7 | The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that |
| 8 | is used to offload some of the processor-intensive tasks or algorithms, for |
| 9 | achieving various system level goals. |
| 10 | |
| 11 | The processor cores in the sub-system usually contain additional sub-modules |
| 12 | like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory |
| 13 | controller, a dedicated local power/sleep controller etc. The DSP processor |
| 14 | core used in Davinci SoCs is usually a C674x DSP CPU. |
| 15 | |
| 16 | DSP Device Node: |
| 17 | ================ |
| 18 | Each DSP Core sub-system is represented as a single DT node. |
| 19 | |
| 20 | Required properties: |
| 21 | -------------------- |
| 22 | The following are the mandatory properties: |
| 23 | |
| 24 | - compatible: Should be one of the following, |
| 25 | "ti,da850-dsp" for DSPs on OMAP-L138 SoCs |
| 26 | |
| 27 | - reg: Should contain an entry for each value in 'reg-names'. |
| 28 | Each entry should have the memory region's start address |
| 29 | and the size of the region, the representation matching |
| 30 | the parent node's '#address-cells' and '#size-cells' values. |
| 31 | |
| 32 | - reg-names: Should contain strings with the following names, each |
| 33 | representing a specific internal memory region or a |
| 34 | specific register space, |
| 35 | "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig_base" |
| 36 | |
| 37 | - interrupts: Should contain the interrupt number used to receive the |
| 38 | interrupts from the DSP. The value should follow the |
| 39 | interrupt-specifier format as dictated by the |
| 40 | 'interrupt-parent' node. |
| 41 | |
| 42 | - memory-region: phandle to the reserved memory node to be associated |
| 43 | with the remoteproc device. The reserved memory node |
| 44 | can be a CMA memory node, and should be defined as |
| 45 | per the bindings in |
| 46 | Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt |
| 47 | |
| 48 | |
| 49 | Example: |
| 50 | -------- |
| 51 | |
| 52 | /* DSP Reserved Memory node */ |
| 53 | reserved-memory { |
| 54 | #address-cells = <1>; |
| 55 | #size-cells = <1>; |
| 56 | ranges; |
| 57 | |
| 58 | dsp_memory_region: dsp-memory@c3000000 { |
| 59 | compatible = "shared-dma-pool"; |
| 60 | reg = <0xc3000000 0x1000000>; |
| 61 | reusable; |
| 62 | }; |
| 63 | }; |
| 64 | |
| 65 | /* DSP node */ |
| 66 | { |
| 67 | dsp: dsp@11800000 { |
| 68 | compatible = "ti,da850-dsp"; |
| 69 | reg = <0x11800000 0x40000>, |
| 70 | <0x11e00000 0x8000>, |
| 71 | <0x11f00000 0x8000>, |
| 72 | <0x01c14044 0x4>, |
| 73 | <0x01c14174 0x8>; |
| 74 | reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", |
| 75 | "chipsig"; |
| 76 | interrupt-parent = <&intc>; |
| 77 | interrupts = <28>; |
| 78 | memory-region = <&dsp_memory_region>; |
| 79 | }; |
| 80 | }; |