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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Yan2d1951f2017-06-01 18:01:31 +08002/*
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
Andy Yan2d1951f2017-06-01 18:01:31 +08004 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/rv1108-cru.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 compatible = "rockchip,rv1108";
16
17 interrupt-parent = <&gic>;
18
19 aliases {
20 serial0 = &uart0;
21 serial1 = &uart1;
22 serial2 = &uart2;
23 spi0 = &sfc;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu0: cpu@f00 {
31 device_type = "cpu";
32 compatible = "arm,cortex-a7";
33 reg = <0xf00>;
34 };
35 };
36
37 arm-pmu {
38 compatible = "arm,cortex-a7-pmu";
39 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
40 };
41
42 timer {
43 compatible = "arm,armv7-timer";
44 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
45 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
46 clock-frequency = <24000000>;
47 };
48
49 xin24m: oscillator {
50 compatible = "fixed-clock";
51 clock-frequency = <24000000>;
52 clock-output-names = "xin24m";
53 #clock-cells = <0>;
54 };
55
56 amba {
57 compatible = "simple-bus";
58 #address-cells = <1>;
59 #size-cells = <1>;
60 ranges;
61
62 pdma: pdma@102a0000 {
63 compatible = "arm,pl330", "arm,primecell";
64 reg = <0x102a0000 0x4000>;
65 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
66 #dma-cells = <1>;
67 arm,pl330-broken-no-flushp;
68 clocks = <&cru ACLK_DMAC>;
69 clock-names = "apb_pclk";
70 };
71 };
72
73 bus_intmem@10080000 {
74 compatible = "mmio-sram";
75 reg = <0x10080000 0x2000>;
76 #address-cells = <1>;
77 #size-cells = <1>;
78 ranges = <0 0x10080000 0x2000>;
79 };
80
81 uart2: serial@10210000 {
82 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
83 reg = <0x10210000 0x100>;
84 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
85 reg-shift = <2>;
86 reg-io-width = <4>;
87 clock-frequency = <24000000>;
88 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
89 clock-names = "baudclk", "apb_pclk";
90 pinctrl-names = "default";
91 pinctrl-0 = <&uart2m0_xfer>;
92 status = "disabled";
93 };
94
95 uart1: serial@10220000 {
96 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
97 reg = <0x10220000 0x100>;
98 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
99 reg-shift = <2>;
100 reg-io-width = <4>;
101 clock-frequency = <24000000>;
102 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
103 clock-names = "baudclk", "apb_pclk";
104 pinctrl-names = "default";
105 pinctrl-0 = <&uart1_xfer>;
106 status = "disabled";
107 };
108
109 uart0: serial@10230000 {
110 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
111 reg = <0x10230000 0x100>;
112 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
113 reg-shift = <2>;
114 reg-io-width = <4>;
115 clock-frequency = <24000000>;
116 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
117 clock-names = "baudclk", "apb_pclk";
118 pinctrl-names = "default";
119 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
120 status = "disabled";
121 };
122
123 grf: syscon@10300000 {
124 compatible = "rockchip,rv1108-grf", "syscon";
125 reg = <0x10300000 0x1000>;
126 };
127
David Wufdc1ecc2017-09-20 14:40:11 +0800128 saradc: saradc@1038c000 {
129 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
130 reg = <0x1038c000 0x100>;
131 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
132 #io-channel-cells = <1>;
133 clock-frequency = <1000000>;
134 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
135 clock-names = "saradc", "apb_pclk";
136 status = "disabled";
137 };
138
Andy Yan2d1951f2017-06-01 18:01:31 +0800139 pmugrf: syscon@20060000 {
140 compatible = "rockchip,rv1108-pmugrf", "syscon";
141 reg = <0x20060000 0x1000>;
142 };
143
144 cru: clock-controller@20200000 {
145 compatible = "rockchip,rv1108-cru";
146 reg = <0x20200000 0x1000>;
147 rockchip,grf = <&grf>;
148 #clock-cells = <1>;
149 #reset-cells = <1>;
150 };
151
152 emmc: dwmmc@30110000 {
153 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
154 clock-freq-min-max = <400000 150000000>;
155 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
156 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
157 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
158 fifo-depth = <0x100>;
159 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
160 reg = <0x30110000 0x4000>;
161 status = "disabled";
162 };
163
164 sdio: dwmmc@30120000 {
165 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
166 clock-freq-min-max = <400000 150000000>;
167 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
168 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
169 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
170 fifo-depth = <0x100>;
171 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
172 reg = <0x30120000 0x4000>;
173 status = "disabled";
174 };
175
176 sdmmc: dwmmc@30130000 {
177 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
178 clock-freq-min-max = <400000 100000000>;
179 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
180 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
181 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
182 fifo-depth = <0x100>;
183 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
184 reg = <0x30130000 0x4000>;
185 status = "disabled";
186 };
187
William Wu809ec942017-08-09 11:36:28 +0800188 usb_host_ehci: usb@30140000 {
189 compatible = "generic-ehci";
190 reg = <0x30140000 0x20000>;
191 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
192 status = "disabled";
193 };
194
195 usb_host_ohci: usb@30160000 {
196 compatible = "generic-ohci";
197 reg = <0x30160000 0x20000>;
198 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
199 status = "disabled";
200 };
201
202 usb20_otg: usb@30180000 {
203 compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb",
204 "snps,dwc2";
205 reg = <0x30180000 0x40000>;
206 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
207 hnp-srp-disable;
208 dr_mode = "otg";
209 status = "disabled";
210 };
211
Andy Yan2d1951f2017-06-01 18:01:31 +0800212 sfc: sfc@301c0000 {
213 compatible = "rockchip,sfc";
214 reg = <0x301c0000 0x200>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
219 clock-names = "clk_sfc", "hclk_sfc";
220 pinctrl-0 = <&sfc_pins>;
221 pinctrl-names = "default";
222 status = "disabled";
223 };
224
225 gmac: ethernet@30200000 {
226 compatible = "rockchip,rv1108-gmac";
227 reg = <0x30200000 0x10000>;
228 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
229 interrupt-names = "macirq";
230 rockchip,grf = <&grf>;
231 clocks = <&cru SCLK_MAC>,
232 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
233 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
234 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
235 clock-names = "stmmaceth",
236 "mac_clk_rx", "mac_clk_tx",
237 "clk_mac_ref", "clk_mac_refout",
238 "aclk_mac", "pclk_mac";
239 pinctrl-names = "default";
240 pinctrl-0 = <&rmii_pins>;
241 phy-mode = "rmii";
242 max-speed = <100>;
243 status = "disabled";
244 };
245
246 gic: interrupt-controller@32010000 {
247 compatible = "arm,gic-400";
248 interrupt-controller;
249 #interrupt-cells = <3>;
250 #address-cells = <0>;
251
252 reg = <0x32011000 0x1000>,
253 <0x32012000 0x1000>,
254 <0x32014000 0x2000>,
255 <0x32016000 0x2000>;
256 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
257 };
258
259 pinctrl: pinctrl {
260 compatible = "rockchip,rv1108-pinctrl";
261 rockchip,grf = <&grf>;
262 rockchip,pmu = <&pmugrf>;
263 #address-cells = <1>;
264 #size-cells = <1>;
265 ranges;
266
267 gpio0: gpio0@20030000 {
268 compatible = "rockchip,gpio-bank";
269 reg = <0x20030000 0x100>;
270 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&xin24m>;
272
273 gpio-controller;
274 #gpio-cells = <2>;
275
276 interrupt-controller;
277 #interrupt-cells = <2>;
278 };
279
280 gpio1: gpio1@10310000 {
281 compatible = "rockchip,gpio-bank";
282 reg = <0x10310000 0x100>;
283 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&xin24m>;
285
286 gpio-controller;
287 #gpio-cells = <2>;
288
289 interrupt-controller;
290 #interrupt-cells = <2>;
291 };
292
293 gpio2: gpio2@10320000 {
294 compatible = "rockchip,gpio-bank";
295 reg = <0x10320000 0x100>;
296 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&xin24m>;
298
299 gpio-controller;
300 #gpio-cells = <2>;
301
302 interrupt-controller;
303 #interrupt-cells = <2>;
304 };
305
306 gpio3: gpio3@10330000 {
307 compatible = "rockchip,gpio-bank";
308 reg = <0x10330000 0x100>;
309 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&xin24m>;
311
312 gpio-controller;
313 #gpio-cells = <2>;
314
315 interrupt-controller;
316 #interrupt-cells = <2>;
317 };
318
319 pcfg_pull_up: pcfg-pull-up {
320 bias-pull-up;
321 };
322
323 pcfg_pull_down: pcfg-pull-down {
324 bias-pull-down;
325 };
326
327 pcfg_pull_none: pcfg-pull-none {
328 bias-disable;
329 };
330
331 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
332 drive-strength = <8>;
333 };
334
335 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
336 drive-strength = <12>;
337 };
338
339 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
340 bias-pull-up;
341 drive-strength = <8>;
342 };
343
344 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
345 drive-strength = <4>;
346 };
347
348 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
349 bias-pull-up;
350 drive-strength = <4>;
351 };
352
353 pcfg_output_high: pcfg-output-high {
354 output-high;
355 };
356
357 pcfg_output_low: pcfg-output-low {
358 output-low;
359 };
360
361 pcfg_input_high: pcfg-input-high {
362 bias-pull-up;
363 input-enable;
364 };
365
366 gmac {
367 rmii_pins: rmii-pins {
368 rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
369 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
370 <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
371 <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
372 <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
373 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
374 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
375 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
376 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
377 <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
378 };
379 };
380
381 i2c1 {
382 i2c1_xfer: i2c1-xfer {
383 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
384 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
385 };
386 };
387
388 i2c2m1 {
389 i2c2m1_xfer: i2c2m1-xfer {
390 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
391 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
392 };
393
394 i2c2m1_gpio: i2c2m1-gpio {
395 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
396 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
397 };
398 };
399
400 i2c2m05v {
401 i2c2m05v_xfer: i2c2m05v-xfer {
402 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
403 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
404 };
405
406 i2c2m05v_gpio: i2c2m05v-gpio {
407 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
408 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
409 };
410 };
411
412 i2c3 {
413 i2c3_xfer: i2c3-xfer {
414 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
415 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
416 };
417 };
418
419 sfc {
420 sfc_pins: sfc-pins {
421 rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>,
422 <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>,
423 <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,
424 <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>,
425 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
426 <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>;
427 };
428 };
429
Otavio Salvadora8819e92018-11-30 11:34:14 -0200430 emmc {
431 emmc_clk: emmc-clk {
432 rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
433 };
434
435 emmc_cmd: emmc-cmd {
436 rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
437 };
438
439 emmc_pwren: emmc-pwren {
440 rockchip,pins = <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
441 };
442
443 emmc_bus1: emmc-bus1 {
444 rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
445 };
446
447 emmc_bus8: emmc-bus8 {
448 rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
449 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
450 <2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
451 <2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
452 <2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
453 <2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
454 <2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
455 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
456 };
457 };
458
Andy Yan2d1951f2017-06-01 18:01:31 +0800459 sdmmc {
460 sdmmc_clk: sdmmc-clk {
461 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
462 };
463
464 sdmmc_cmd: sdmmc-cmd {
465 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
466 };
467
468 sdmmc_cd: sdmmc-cd {
469 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
470 };
471
472 sdmmc_bus1: sdmmc-bus1 {
473 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
474 };
475
476 sdmmc_bus4: sdmmc-bus4 {
477 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
478 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
479 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
480 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
481 };
482 };
483
484 uart0 {
485 uart0_xfer: uart0-xfer {
486 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
487 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
488 };
489
490 uart0_cts: uart0-cts {
491 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
492 };
493
494 uart0_rts: uart0-rts {
495 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
496 };
497
498 uart0_rts_gpio: uart0-rts-gpio {
499 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
500 };
501 };
502
503 uart1 {
504 uart1_xfer: uart1-xfer {
505 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
506 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
507 };
508
509 uart1_cts: uart1-cts {
510 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
511 };
512
513 uart01rts: uart1-rts {
514 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
515 };
516 };
517
518 uart2m0 {
519 uart2m0_xfer: uart2m0-xfer {
520 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
521 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
522 };
523 };
524
525 uart2m1 {
526 uart2m1_xfer: uart2m1-xfer {
527 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
528 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
529 };
530 };
531
532 uart2_5v {
533 uart2_5v_cts: uart2_5v-cts {
534 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
535 };
536
537 uart2_5v_rts: uart2_5v-rts {
538 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
539 };
540 };
541 };
542};