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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_MVS 1 /* ...on a MVsensor module */
38#define CONFIG_MVS_16BIT_FLASH /* ...with 16-bit flash access */
39#define CONFIG_8xx_GCLK_FREQ 50000000/* ... and a 50 MHz CPU */
40
41#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
42
43#undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */
44#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
45#undef CONFIG_8xx_CONS_NONE
46#define CONFIG_BAUDRATE 115200 /* console baudrate */
47#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */
48
49#define CONFIG_PREBOOT "echo;echo To mount root over NFS use \"run bootnet\";echo To mount root from FLASH use \"run bootflash\";echo"
50#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
51#define CONFIG_BOOTCOMMAND \
52 "bootp; " \
53 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
54 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
55 "bootm"
56
57#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
58#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
59
60#define CONFIG_WATCHDOG /* watchdog disabled/enabled */
61
62#undef CONFIG_STATUS_LED /* Status LED disabled/enabled */
63
64#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
65
66#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_VENDOREX )
67
68#undef CONFIG_MAC_PARTITION
69#undef CONFIG_DOS_PARTITION
70
71#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
72
73/* MVsensor uses a really minimal U-Boot ! */
74#define CONFIG_COMMANDS (CFG_CMD_LOADS | \
75 CFG_CMD_LOADB | \
76 CFG_CMD_IMI | \
77 CFG_CMD_FLASH | \
78 CFG_CMD_MEMORY | \
79 CFG_CMD_NET | \
80 CFG_CMD_DHCP | \
81 CFG_CMD_ENV | \
82 CFG_CMD_BOOTD | \
83 CFG_CMD_RUN )
84
85/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
86#include <cmd_confdefs.h>
87
88/*
89 * Miscellaneous configurable options
90 */
91#undef CFG_LONGHELP /* undef to save memory */
92#define CFG_PROMPT "=> " /* Monitor Command Prompt */
93
94#undef CFG_HUSH_PARSER /* Hush parse for U-Boot ?? */
95#ifdef CFG_HUSH_PARSER
96#define CFG_PROMPT_HUSH_PS2 "> "
97#endif
98
99#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
100#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
101#else
102#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
103#endif
104#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
105#define CFG_MAXARGS 16 /* max number of command args */
106#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
107
108#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
109#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
110
111#define CFG_LOAD_ADDR 0x100000 /* default load address */
112
113#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
114
115#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
116
117/*
118 * Low Level Configuration Settings
119 * (address mappings, register initial values, etc.)
120 * You should know what you are doing if you make changes here.
121 */
122/*-----------------------------------------------------------------------
123 * Internal Memory Mapped Register
124 */
125#define CFG_IMMR 0xFFF00000
126
127/*-----------------------------------------------------------------------
128 * Definitions for initial stack pointer and data area (in DPRAM)
129 */
130#define CFG_INIT_RAM_ADDR CFG_IMMR
131#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
132#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
133#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
134#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
135
136/*-----------------------------------------------------------------------
137 * Start addresses for the final memory configuration
138 * (Set up by the startup code)
139 * Please note that CFG_SDRAM_BASE _must_ start at 0
140 */
141#define CFG_SDRAM_BASE 0x00000000
142#define CFG_FLASH_BASE 0x40000000
143
144#define CFG_MONITOR_LEN (128 << 10) /* Reserve 192 kB for Monitor */
145
146#define CFG_MONITOR_BASE CFG_FLASH_BASE
147#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
148
149/*
150 * For booting Linux, the board info and command line data
151 * have to be in the first 8 MB of memory, since this is
152 * the maximum mapped by the Linux kernel during initialization.
153 */
154#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
155
156/*-----------------------------------------------------------------------
157 * FLASH organization
158 */
159#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
160#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip (for AMD320DB chip) */
161
162#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
163#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
164
165#define CFG_ENV_IS_IN_FLASH 1
166
167/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */
168#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector (bottom boot sector) */
169#define CFG_ENV_SIZE 0x2000 /* Used Size of Environment Sector 8k */
170
171/*-----------------------------------------------------------------------
172 * Cache Configuration
173 */
174#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
175#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
176#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
177#endif
178
179/*-----------------------------------------------------------------------
180 * SYPCR - System Protection Control 11-9
181 * SYPCR can only be written once after reset!
182 *-----------------------------------------------------------------------
183 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
184 */
185#if defined(CONFIG_WATCHDOG)
186#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk8bde7f72003-06-27 21:31:46 +0000187 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
wdenkc6097192002-11-03 00:24:07 +0000188#else
189#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
190#endif
191
192/*-----------------------------------------------------------------------
193 * SIUMCR - SIU Module Configuration 11-6
194 *-----------------------------------------------------------------------
195 * PCMCIA config., multi-function pin tri-state
196 */
197#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
198
199/*-----------------------------------------------------------------------
200 * TBSCR - Time Base Status and Control 11-26
201 *-----------------------------------------------------------------------
202 * Clear Reference Interrupt Status, Timebase freezing enabled
203 */
204#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
205
206/*-----------------------------------------------------------------------
207 * RTCSC - Real-Time Clock Status and Control Register 11-27
208 *-----------------------------------------------------------------------
209 */
210#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
211
212/*-----------------------------------------------------------------------
213 * PISCR - Periodic Interrupt Status and Control 11-31
214 *-----------------------------------------------------------------------
215 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
216 */
217#define CFG_PISCR (PISCR_PS | PISCR_PITF)
218
219/*-----------------------------------------------------------------------
220 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
221 *-----------------------------------------------------------------------
222 * Reset PLL lock status sticky bit, timer expired status bit and timer
223 * interrupt status bit
224 *
225 */
226#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
227
228/*-----------------------------------------------------------------------
229 * SCCR - System Clock and reset Control Register 15-27
230 *-----------------------------------------------------------------------
231 * Set clock output, timebase and RTC source and divider,
232 * power management and some other internal clocks
233 */
234#define SCCR_MASK SCCR_EBDF11
235#define CFG_SCCR (SCCR_TBS | \
236 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
237 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
238 SCCR_DFALCD00)
239
240/*-----------------------------------------------------------------------
241 * PCMCIA stuff
242 *-----------------------------------------------------------------------
243 *
244 */
245#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
246#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
247#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
248#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
249#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
250#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
251#define CFG_PCMCIA_IO_ADDR (0xEC000000)
252#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
253
254/*-----------------------------------------------------------------------
255 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
256 *-----------------------------------------------------------------------
257 */
258
259#define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */
260
261#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
262#undef CONFIG_IDE_LED /* LED for ide not supported */
263#undef CONFIG_IDE_RESET /* reset for ide not supported */
264
265#define CFG_IDE_MAXBUS 0 /* max. no. of IDE buses */
266#define CFG_IDE_MAXDEVICE 0 /* max. no. of drives per IDE bus */
267
268
269#define CFG_ATA_IDE0_OFFSET 0x0000
270
271#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
272
273/* Offset for data I/O */
274#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
275
276/* Offset for normal register accesses */
277#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
278
279/* Offset for alternate registers */
280#define CFG_ATA_ALT_OFFSET 0x0100
281
282/*-----------------------------------------------------------------------
283 *
284 *-----------------------------------------------------------------------
285 *
286 */
287/*#define CFG_DER 0x2002000F*/
288#define CFG_DER 0
289
290/*
291 * Init Memory Controller:
292 *
293 * BR0/1 and OR0/1 (FLASH)
294 */
295
296#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
297#undef FLASH_BASE1_PRELIM
298
299/* used to re-map FLASH both when starting from SRAM or FLASH:
300 * restrict access enough to keep SRAM working (if any)
301 * but not too much to meddle with FLASH accesses
302 */
303#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
304#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
305
306
307/*
308 * FLASH timing:
309 */
310/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
311#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
312 OR_SCY_2_CLK | OR_EHTR | OR_BI)
313/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
314/*
315#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
316 OR_SCY_5_CLK | OR_EHTR)
317*/
318
319#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
320#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
321#ifdef CONFIG_MVS_16BIT_FLASH
322#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
323#else
324#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
325#endif
326
327#undef CFG_OR1_REMAP
328#undef CFG_OR1_PRELIM
329#undef CFG_BR1_PRELIM
330/*
331 * BR2/3 and OR2/3 (SDRAM)
332 *
333 */
334#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
335#undef SDRAM_BASE3_PRELIM
336#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
337
338/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
339#define CFG_OR_TIMING_SDRAM 0x00000A00
340
341#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
342#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
343
344#undef CFG_OR3_PRELIM
345#undef CFG_BR3_PRELIM
346
347
348/*
349 * Memory Periodic Timer Prescaler
350 *
351 * The Divider for PTA (refresh timer) configuration is based on an
352 * example SDRAM configuration (64 MBit, one bank). The adjustment to
353 * the number of chip selects (NCS) and the actually needed refresh
354 * rate is done by setting MPTPR.
355 *
356 * PTA is calculated from
357 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
358 *
359 * gclk CPU clock (not bus clock!)
360 * Trefresh Refresh cycle * 4 (four word bursts used)
361 *
362 * 4096 Rows from SDRAM example configuration
363 * 1000 factor s -> ms
364 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
365 * 4 Number of refresh cycles per period
366 * 64 Refresh cycle in ms per number of rows
367 * --------------------------------------------
368 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
369 *
370 * 50 MHz => 50.000.000 / Divider = 98
371 * 66 Mhz => 66.000.000 / Divider = 129
372 * 80 Mhz => 80.000.000 / Divider = 156
373 */
374#define CFG_MAMR_PTA 98
375
376/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
377#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
378#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
379
380/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
381#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
382#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
383
384/*
385 * MAMR settings for SDRAM
386 */
387
388/* 8 column SDRAM */
389#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
390 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
391 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
392/* 9 column SDRAM */
393#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
394 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 | \
395 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
396
397
398/*
399 * Internal Definitions
400 *
401 * Boot Flags
402 */
403#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
404#define BOOTFLAG_WARM 0x02 /* Software reboot */
405
406#endif /* __CONFIG_H */