Blame - board/renesas/r2dplus/lowlevel_init.S - platform/external/u-boot

blob: 33f6e078260d8eaccae9a5dd7ce4132086221fa1 [file] [log] [blame]

Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	1	/*
				2	* modified from SH-IPL+g (init-r0p751rlc0011rl.S)
				3	* Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
				4	* Coyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
				5	*/
				6
				7	#include <config.h>
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	8
				9	#include <asm/processor.h>
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	10	#include <asm/macro.h>
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	11
				12	.global lowlevel_init
				13	.text
Jean-Christophe PLAGNIOL-VILLARD	4d4a960	2008-12-02 07:40:03 +0100	[diff] [blame]	14	.align 2
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	15
				16	lowlevel_init:
				17
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	18	write32 CCR_A, CCR_D_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	19
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	20	write32 MMUCR_A, MMUCR_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	21
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	22	write32 BCR1_A, BCR1_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	23
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	24	write16 BCR2_A, BCR2_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	25
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	26	write16 BCR3_A, BCR3_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	27
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	28	write32 BCR4_A, BCR4_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	29
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	30	write32 WCR1_A, WCR1_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	31
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	32	write32 WCR2_A, WCR2_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	33
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	34	write32 WCR3_A, WCR3_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	35
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	36	write16 PCR_A, PCR_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	37
Nobuhiro Iwamatsu	c9935c9	2009-01-11 17:48:56 +0900	[diff] [blame]	38	write16 LED_A, LED_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	39
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	40	write32 MCR_A, MCR_D1
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	41
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	42	write16 RTCNT_A, RTCNT_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	43
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	44	write16 RTCOR_A, RTCOR_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	45
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	46	write16 RFCR_A, RFCR_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	47
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	48	write16 RTCSR_A, RTCSR_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	49
Nobuhiro Iwamatsu	c9935c9	2009-01-11 17:48:56 +0900	[diff] [blame]	50	write8 SDMR3_A, SDMR3_D0
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	51
				52	/* Wait DRAM refresh 30 times */
Jean-Christophe PLAGNIOL-VILLARD	e443077	2008-12-20 19:29:48 +0100	[diff] [blame]	53	mov.l RFCR_A, r1
				54	mov #30, r3
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	55	1:
Jean-Christophe PLAGNIOL-VILLARD	e443077	2008-12-20 19:29:48 +0100	[diff] [blame]	56	mov.w @r1, r0
				57	extu.w r0, r2
				58	cmp/hi r3, r2
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	59	bf 1b
				60
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	61	write32 MCR_A, MCR_D2
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	62
Nobuhiro Iwamatsu	c9935c9	2009-01-11 17:48:56 +0900	[diff] [blame]	63	write8 SDMR3_A, SDMR3_D1
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	64
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	65	write32 IRLMASK_A, IRLMASK_D
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	66
Jean-Christophe PLAGNIOL-VILLARD	f7e78f3	2008-12-20 19:29:49 +0100	[diff] [blame]	67	write32 CCR_A, CCR_D_E
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	68
				69	rts
				70	nop
				71
				72	.align 2
				73	CCR_A: .long CCR /* Cache Control Register */
				74	CCR_D_D: .long 0x0808 /* Flush the cache, disable */
				75	CCR_D_E: .long 0x8000090B
				76
				77	FRQCR_A: .long FRQCR /* FRQCR Address */
				78	FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */
Jean-Christophe PLAGNIOL-VILLARD	4d4a960	2008-12-02 07:40:03 +0100	[diff] [blame]	79	BCR1_A: .long BCR1 /* BCR1 Address */
				80	BCR1_D: .long 0x00180008
				81	BCR2_A: .long BCR2 /* BCR2 Address */
				82	BCR2_D: .long 0xabe8
				83	BCR3_A: .long BCR3 /* BCR3 Address */
				84	BCR3_D: .long 0x0000
				85	BCR4_A: .long BCR4 /* BCR4 Address */
				86	BCR4_D: .long 0x00000010
				87	WCR1_A: .long WCR1 /* WCR1 Address */
				88	WCR1_D: .long 0x33343333
				89	WCR2_A: .long WCR2 /* WCR2 Address */
				90	WCR2_D: .long 0xcff86fbf
				91	WCR3_A: .long WCR3 /* WCR3 Address */
				92	WCR3_D: .long 0x07777707
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	93	LED_A: .long 0x04000036 /* LED Address */
Nobuhiro Iwamatsu	c9935c9	2009-01-11 17:48:56 +0900	[diff] [blame]	94	LED_D: .long 0xFF /* LED Data */
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	95	RTCNT_A: .long RTCNT /* RTCNT Address */
Nobuhiro Iwamatsu	edb3205	2010-07-22 15:41:49 +0900	[diff] [blame]	96	RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */
				97	.align 2
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	98	RTCOR_A: .long RTCOR /* RTCOR Address */
Nobuhiro Iwamatsu	edb3205	2010-07-22 15:41:49 +0900	[diff] [blame]	99	RTCOR_D: .word 0xA534 /* RTCOR Write Code */
				100	.align 2
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	101	RTCSR_A: .long RTCSR /* RTCSR Address */
Nobuhiro Iwamatsu	edb3205	2010-07-22 15:41:49 +0900	[diff] [blame]	102	RTCSR_D: .word 0xA510 /* RTCSR Write Code */
				103	.align 2
Jean-Christophe PLAGNIOL-VILLARD	4d4a960	2008-12-02 07:40:03 +0100	[diff] [blame]	104	SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */
Nobuhiro Iwamatsu	c9935c9	2009-01-11 17:48:56 +0900	[diff] [blame]	105	SDMR3_D0: .long 0x55
				106	SDMR3_D1: .long 0x00
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	107	MCR_A: .long MCR /* MCR Address */
Jean-Christophe PLAGNIOL-VILLARD	4d4a960	2008-12-02 07:40:03 +0100	[diff] [blame]	108	MCR_D1: .long 0x081901F4 /* MRSET:'0' */
				109	MCR_D2: .long 0x481901F4 /* MRSET:'1' */
				110	RFCR_A: .long RFCR /* RFCR Address */
				111	RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
Nobuhiro Iwamatsu	f5e2466	2008-03-25 17:11:24 +0900	[diff] [blame]	112	PCR_A: .long PCR /* PCR Address */
				113	PCR_D: .long 0x0000
				114	MMUCR_A: .long MMUCR /* MMUCCR Address */
				115	MMUCR_D: .long 0x00000000 /* MMUCCR Data */
				116	IRLMASK_A: .long 0xA4000000 /* IRLMASK Address */
				117	IRLMASK_D: .long 0x00000000 /* IRLMASK Data */