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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ilya Yanok0b23fb32009-07-21 19:32:21 +04002/*
3 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
4 * (C) Copyright 2008 Armadeus Systems, nc
5 * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
6 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 *
9 * (C) Copyright 2003
10 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 *
12 * This file is based on mpc4200fec.h
13 * (C) Copyright Motorola, Inc., 2000
Ilya Yanok0b23fb32009-07-21 19:32:21 +040014 */
15
Ilya Yanok0b23fb32009-07-21 19:32:21 +040016#ifndef __FEC_MXC_H
17#define __FEC_MXC_H
18
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +020019#include <clk.h>
20
Jagan Teki567173a2016-12-06 00:00:50 +010021/* Layout description of the FEC */
Ilya Yanok0b23fb32009-07-21 19:32:21 +040022struct ethernet_regs {
Jagan Teki567173a2016-12-06 00:00:50 +010023 /* [10:2]addr = 00 */
Ilya Yanok0b23fb32009-07-21 19:32:21 +040024
Jagan Teki567173a2016-12-06 00:00:50 +010025 /* Control and status Registers (offset 000-1FF) */
Ilya Yanok0b23fb32009-07-21 19:32:21 +040026 uint32_t res0[1]; /* MBAR_ETH + 0x000 */
27 uint32_t ievent; /* MBAR_ETH + 0x004 */
28 uint32_t imask; /* MBAR_ETH + 0x008 */
29
30 uint32_t res1[1]; /* MBAR_ETH + 0x00C */
31 uint32_t r_des_active; /* MBAR_ETH + 0x010 */
32 uint32_t x_des_active; /* MBAR_ETH + 0x014 */
33 uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */
34 uint32_t ecntrl; /* MBAR_ETH + 0x024 */
35
36 uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */
37 uint32_t mii_data; /* MBAR_ETH + 0x040 */
38 uint32_t mii_speed; /* MBAR_ETH + 0x044 */
39 uint32_t res4[7]; /* MBAR_ETH + 0x048-60 */
40 uint32_t mib_control; /* MBAR_ETH + 0x064 */
41
42 uint32_t res5[7]; /* MBAR_ETH + 0x068-80 */
43 uint32_t r_cntrl; /* MBAR_ETH + 0x084 */
44 uint32_t res6[15]; /* MBAR_ETH + 0x088-C0 */
45 uint32_t x_cntrl; /* MBAR_ETH + 0x0C4 */
46 uint32_t res7[7]; /* MBAR_ETH + 0x0C8-E0 */
47 uint32_t paddr1; /* MBAR_ETH + 0x0E4 */
48 uint32_t paddr2; /* MBAR_ETH + 0x0E8 */
49 uint32_t op_pause; /* MBAR_ETH + 0x0EC */
50
51 uint32_t res8[10]; /* MBAR_ETH + 0x0F0-114 */
52 uint32_t iaddr1; /* MBAR_ETH + 0x118 */
53 uint32_t iaddr2; /* MBAR_ETH + 0x11C */
54 uint32_t gaddr1; /* MBAR_ETH + 0x120 */
55 uint32_t gaddr2; /* MBAR_ETH + 0x124 */
56 uint32_t res9[7]; /* MBAR_ETH + 0x128-140 */
57
58 uint32_t x_wmrk; /* MBAR_ETH + 0x144 */
59 uint32_t res10[1]; /* MBAR_ETH + 0x148 */
60 uint32_t r_bound; /* MBAR_ETH + 0x14C */
61 uint32_t r_fstart; /* MBAR_ETH + 0x150 */
62 uint32_t res11[11]; /* MBAR_ETH + 0x154-17C */
63 uint32_t erdsr; /* MBAR_ETH + 0x180 */
64 uint32_t etdsr; /* MBAR_ETH + 0x184 */
65 uint32_t emrbr; /* MBAR_ETH + 0x188 */
66 uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */
67
Jagan Teki567173a2016-12-06 00:00:50 +010068 /* MIB COUNTERS (Offset 200-2FF) */
Ilya Yanok0b23fb32009-07-21 19:32:21 +040069 uint32_t rmon_t_drop; /* MBAR_ETH + 0x200 */
70 uint32_t rmon_t_packets; /* MBAR_ETH + 0x204 */
71 uint32_t rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
72 uint32_t rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */
73 uint32_t rmon_t_crc_align; /* MBAR_ETH + 0x210 */
74 uint32_t rmon_t_undersize; /* MBAR_ETH + 0x214 */
75 uint32_t rmon_t_oversize; /* MBAR_ETH + 0x218 */
76 uint32_t rmon_t_frag; /* MBAR_ETH + 0x21C */
77 uint32_t rmon_t_jab; /* MBAR_ETH + 0x220 */
78 uint32_t rmon_t_col; /* MBAR_ETH + 0x224 */
79 uint32_t rmon_t_p64; /* MBAR_ETH + 0x228 */
80 uint32_t rmon_t_p65to127; /* MBAR_ETH + 0x22C */
81 uint32_t rmon_t_p128to255; /* MBAR_ETH + 0x230 */
82 uint32_t rmon_t_p256to511; /* MBAR_ETH + 0x234 */
83 uint32_t rmon_t_p512to1023; /* MBAR_ETH + 0x238 */
84 uint32_t rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */
85 uint32_t rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */
86 uint32_t rmon_t_octets; /* MBAR_ETH + 0x244 */
87 uint32_t ieee_t_drop; /* MBAR_ETH + 0x248 */
88 uint32_t ieee_t_frame_ok; /* MBAR_ETH + 0x24C */
89 uint32_t ieee_t_1col; /* MBAR_ETH + 0x250 */
90 uint32_t ieee_t_mcol; /* MBAR_ETH + 0x254 */
91 uint32_t ieee_t_def; /* MBAR_ETH + 0x258 */
92 uint32_t ieee_t_lcol; /* MBAR_ETH + 0x25C */
93 uint32_t ieee_t_excol; /* MBAR_ETH + 0x260 */
94 uint32_t ieee_t_macerr; /* MBAR_ETH + 0x264 */
95 uint32_t ieee_t_cserr; /* MBAR_ETH + 0x268 */
96 uint32_t ieee_t_sqe; /* MBAR_ETH + 0x26C */
97 uint32_t t_fdxfc; /* MBAR_ETH + 0x270 */
98 uint32_t ieee_t_octets_ok; /* MBAR_ETH + 0x274 */
99
100 uint32_t res13[2]; /* MBAR_ETH + 0x278-27C */
101 uint32_t rmon_r_drop; /* MBAR_ETH + 0x280 */
102 uint32_t rmon_r_packets; /* MBAR_ETH + 0x284 */
103 uint32_t rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */
104 uint32_t rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */
105 uint32_t rmon_r_crc_align; /* MBAR_ETH + 0x290 */
106 uint32_t rmon_r_undersize; /* MBAR_ETH + 0x294 */
107 uint32_t rmon_r_oversize; /* MBAR_ETH + 0x298 */
108 uint32_t rmon_r_frag; /* MBAR_ETH + 0x29C */
109 uint32_t rmon_r_jab; /* MBAR_ETH + 0x2A0 */
110
111 uint32_t rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */
112
113 uint32_t rmon_r_p64; /* MBAR_ETH + 0x2A8 */
114 uint32_t rmon_r_p65to127; /* MBAR_ETH + 0x2AC */
115 uint32_t rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */
116 uint32_t rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */
117 uint32_t rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */
118 uint32_t rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */
119 uint32_t rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */
120 uint32_t rmon_r_octets; /* MBAR_ETH + 0x2C4 */
121 uint32_t ieee_r_drop; /* MBAR_ETH + 0x2C8 */
122 uint32_t ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */
123 uint32_t ieee_r_crc; /* MBAR_ETH + 0x2D0 */
124 uint32_t ieee_r_align; /* MBAR_ETH + 0x2D4 */
125 uint32_t r_macerr; /* MBAR_ETH + 0x2D8 */
126 uint32_t r_fdxfc; /* MBAR_ETH + 0x2DC */
127 uint32_t ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
128
John Rigby740d6ae2010-01-25 23:12:57 -0700129 uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400130
Fabio Estevam7df51fd2013-09-13 00:36:27 -0300131#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
John Rigby740d6ae2010-01-25 23:12:57 -0700132 uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */
133 uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */
134 uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */
135 uint16_t res16[3]; /* MBAR_ETH + 0x30a-30e */
136 uint32_t res17[60]; /* MBAR_ETH + 0x300-3FF */
137#else
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400138 uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */
John Rigby740d6ae2010-01-25 23:12:57 -0700139#endif
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400140};
141
142#define FEC_IEVENT_HBERR 0x80000000
143#define FEC_IEVENT_BABR 0x40000000
144#define FEC_IEVENT_BABT 0x20000000
145#define FEC_IEVENT_GRA 0x10000000
146#define FEC_IEVENT_TXF 0x08000000
147#define FEC_IEVENT_TXB 0x04000000
148#define FEC_IEVENT_RXF 0x02000000
149#define FEC_IEVENT_RXB 0x01000000
150#define FEC_IEVENT_MII 0x00800000
151#define FEC_IEVENT_EBERR 0x00400000
152#define FEC_IEVENT_LC 0x00200000
153#define FEC_IEVENT_RL 0x00100000
154#define FEC_IEVENT_UN 0x00080000
155
156#define FEC_IMASK_HBERR 0x80000000
157#define FEC_IMASK_BABR 0x40000000
158#define FEC_IMASKT_BABT 0x20000000
159#define FEC_IMASK_GRA 0x10000000
160#define FEC_IMASKT_TXF 0x08000000
161#define FEC_IMASK_TXB 0x04000000
162#define FEC_IMASKT_RXF 0x02000000
163#define FEC_IMASK_RXB 0x01000000
164#define FEC_IMASK_MII 0x00800000
165#define FEC_IMASK_EBERR 0x00400000
166#define FEC_IMASK_LC 0x00200000
167#define FEC_IMASKT_RL 0x00100000
168#define FEC_IMASK_UN 0x00080000
169
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400170#define FEC_RCNTRL_MAX_FL_SHIFT 16
171#define FEC_RCNTRL_LOOP 0x00000001
172#define FEC_RCNTRL_DRT 0x00000002
173#define FEC_RCNTRL_MII_MODE 0x00000004
174#define FEC_RCNTRL_PROM 0x00000008
175#define FEC_RCNTRL_BC_REJ 0x00000010
176#define FEC_RCNTRL_FCE 0x00000020
Jason Liu2ef2b952011-12-16 05:17:07 +0000177#define FEC_RCNTRL_RGMII 0x00000040
Marek Vasuta50a90c2011-09-11 18:05:32 +0000178#define FEC_RCNTRL_RMII 0x00000100
Troy Kisky28774cb2012-02-07 14:08:46 +0000179#define FEC_RCNTRL_RMII_10T 0x00000200
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400180
181#define FEC_TCNTRL_GTS 0x00000001
182#define FEC_TCNTRL_HBC 0x00000002
183#define FEC_TCNTRL_FDEN 0x00000004
184#define FEC_TCNTRL_TFC_PAUSE 0x00000008
185#define FEC_TCNTRL_RFC_PAUSE 0x00000010
186
187#define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */
188#define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */
Troy Kisky28774cb2012-02-07 14:08:46 +0000189#define FEC_ECNTRL_SPEED 0x00000020
Jason Liu2ef2b952011-12-16 05:17:07 +0000190#define FEC_ECNTRL_DBSWAP 0x00000100
Philippe Schenkera1a34fa2020-03-11 11:52:58 +0100191#define FEC_ECNTRL_TXC_DLY 0x00010000 /* TXC delayed */
192#define FEC_ECNTRL_RXC_DLY 0x00020000 /* RXC delayed */
Jason Liu2ef2b952011-12-16 05:17:07 +0000193
194#define FEC_X_WMRK_STRFWD 0x00000100
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400195
Marek Vasutc0b5a3b2012-08-29 03:49:51 +0000196#define FEC_X_DES_ACTIVE_TDAR 0x01000000
197#define FEC_R_DES_ACTIVE_RDAR 0x01000000
198
Fabio Estevam7df51fd2013-09-13 00:36:27 -0300199#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
John Rigby740d6ae2010-01-25 23:12:57 -0700200/* defines for MIIGSK */
201/* RMII frequency control: 0=50MHz, 1=5MHz */
202#define MIIGSK_CFGR_FRCONT (1 << 6)
203/* loopback mode */
204#define MIIGSK_CFGR_LBMODE (1 << 4)
205/* echo mode */
206#define MIIGSK_CFGR_EMODE (1 << 3)
207/* MII gasket mode field */
208#define MIIGSK_CFGR_IF_MODE_MASK (3 << 0)
209/* MMI/7-Wire mode */
210#define MIIGSK_CFGR_IF_MODE_MII (0 << 0)
211/* RMII mode */
212#define MIIGSK_CFGR_IF_MODE_RMII (1 << 0)
213/* reflects MIIGSK Enable bit (RO) */
214#define MIIGSK_ENR_READY (1 << 2)
215/* enable MIGSK (set by default) */
216#define MIIGSK_ENR_EN (1 << 1)
217#endif
218
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400219/**
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400220 * @brief Receive & Transmit Buffer Descriptor definitions
221 *
222 * Note: The first BD must be aligned (see DB_ALIGNMENT)
223 */
224struct fec_bd {
225 uint16_t data_length; /* payload's length in bytes */
226 uint16_t status; /* BD's staus (see datasheet) */
227 uint32_t data_pointer; /* payload's buffer address */
228};
229
Jagan Teki567173a2016-12-06 00:00:50 +0100230/* Supported phy types on this platform */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400231enum xceiver_type {
232 SEVENWIRE, /* 7-wire */
233 MII10, /* MII 10Mbps */
Marek Vasuta50a90c2011-09-11 18:05:32 +0000234 MII100, /* MII 100Mbps */
Jason Liu2ef2b952011-12-16 05:17:07 +0000235 RMII, /* RMII */
236 RGMII, /* RGMII */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400237};
238
Jagan Teki567173a2016-12-06 00:00:50 +0100239/* @brief i.MX27-FEC private structure */
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400240struct fec_priv {
241 struct ethernet_regs *eth; /* pointer to register'S base */
242 enum xceiver_type xcv_type; /* transceiver type */
243 struct fec_bd *rbd_base; /* RBD ring */
244 int rbd_index; /* next receive BD to read */
245 struct fec_bd *tbd_base; /* TBD ring */
246 int tbd_index; /* next transmit BD to write */
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900247 struct bd_info *bd;
Eric Nelson5c1ad3e2012-03-15 18:33:25 +0000248 uint8_t *tdb_ptr;
Marek Vasut9e27e9d2011-09-16 01:13:47 +0200249 int dev_id;
Troy Kisky13947f42012-02-07 14:08:47 +0000250 struct mii_dev *bus;
251#ifdef CONFIG_PHYLIB
252 struct phy_device *phydev;
Fabio Estevam89b5bd52020-06-18 20:21:18 -0300253 ofnode phy_of_node;
Troy Kisky13947f42012-02-07 14:08:47 +0000254#else
Troy Kiskyfe428b92012-10-22 16:40:46 +0000255 int phy_id;
Marek Vasut2e5f4422011-09-11 18:05:36 +0000256 int (*mii_postcall)(int);
Troy Kisky13947f42012-02-07 14:08:47 +0000257#endif
Martin Fuzzeyad8c43c2018-10-04 19:59:20 +0200258#ifdef CONFIG_DM_REGULATOR
259 struct udevice *phy_supply;
260#endif
Simon Glassbcee8d62019-12-06 21:41:35 -0700261#if CONFIG_IS_ENABLED(DM_GPIO)
Michael Trimarchiefd0b792018-06-17 15:22:39 +0200262 struct gpio_desc phy_reset_gpio;
263 uint32_t reset_delay;
Andrejs Cainikovs31d40452019-03-01 13:27:59 +0000264 uint32_t reset_post_delay;
Michael Trimarchiefd0b792018-06-17 15:22:39 +0200265#endif
Jagan Teki60752ca2016-12-06 00:00:49 +0100266#ifdef CONFIG_DM_ETH
267 u32 interface;
268#endif
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +0200269 struct clk ipg_clk;
Peng Fan673f6592019-10-25 09:48:02 +0000270 struct clk ahb_clk;
271 struct clk clk_enet_out;
272 struct clk clk_ref;
273 struct clk clk_ptp;
Anatolij Gustschin58ec4d32018-10-18 16:15:11 +0200274 u32 clk_rate;
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400275};
276
Ilya Yanok0b23fb32009-07-21 19:32:21 +0400277/**
278 * @brief Numbers of buffer descriptors for receiving
279 *
280 * The number defines the stocked memory buffers for the receiving task.
281 * Larger values makes no sense in this limited environment.
282 */
283#define FEC_RBD_NUM 64
284
285/**
286 * @brief Define the ethernet packet size limit in memory
287 *
288 * Note: Do not shrink this number. This will force the FEC to spread larger
289 * frames in more than one BD. This is nothing to worry about, but the current
290 * driver can't handle it.
291 */
292#define FEC_MAX_PKT_SIZE 1536
293
294/* Receive BD status bits */
295#define FEC_RBD_EMPTY 0x8000 /* Receive BD status: Buffer is empty */
296#define FEC_RBD_WRAP 0x2000 /* Receive BD status: Last BD in ring */
297/* Receive BD status: Buffer is last in frame (useless here!) */
298#define FEC_RBD_LAST 0x0800
299#define FEC_RBD_MISS 0x0100 /* Receive BD status: Miss bit for prom mode */
300/* Receive BD status: The received frame is broadcast frame */
301#define FEC_RBD_BC 0x0080
302/* Receive BD status: The received frame is multicast frame */
303#define FEC_RBD_MC 0x0040
304#define FEC_RBD_LG 0x0020 /* Receive BD status: Frame length violation */
305#define FEC_RBD_NO 0x0010 /* Receive BD status: Nonoctet align frame */
306#define FEC_RBD_CR 0x0004 /* Receive BD status: CRC error */
307#define FEC_RBD_OV 0x0002 /* Receive BD status: Receive FIFO overrun */
308#define FEC_RBD_TR 0x0001 /* Receive BD status: Frame is truncated */
309#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
310 FEC_RBD_OV | FEC_RBD_TR)
311
312/* Transmit BD status bits */
313#define FEC_TBD_READY 0x8000 /* Tansmit BD status: Buffer is ready */
314#define FEC_TBD_WRAP 0x2000 /* Tansmit BD status: Mark as last BD in ring */
315#define FEC_TBD_LAST 0x0800 /* Tansmit BD status: Buffer is last in frame */
316#define FEC_TBD_TC 0x0400 /* Tansmit BD status: Transmit the CRC */
317#define FEC_TBD_ABC 0x0200 /* Tansmit BD status: Append bad CRC */
318
319/* MII-related definitios */
320#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
321#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
322#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
323#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
324#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
325#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
326#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
327
328#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
329#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
330
331#endif /* __FEC_MXC_H */