| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | |
| 26 | /* |
| 27 | * CPU test |
| 28 | * Ternary instructions instr rA,rS,UIMM |
| 29 | * |
| 30 | * Logic instructions: ori, oris, xori, xoris |
| 31 | * |
| 32 | * The test contains a pre-built table of instructions, operands and |
| 33 | * expected results. For each table entry, the test will cyclically use |
| 34 | * different sets of operand registers and result registers. |
| 35 | */ |
| 36 | |
| 37 | #ifdef CONFIG_POST |
| 38 | |
| 39 | #include <post.h> |
| 40 | #include "cpu_asm.h" |
| 41 | |
| 42 | #if CONFIG_POST & CFG_POST_CPU |
| 43 | |
| 44 | extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); |
| 45 | extern ulong cpu_post_makecr (long v); |
| 46 | |
| 47 | static struct cpu_post_threei_s |
| 48 | { |
| 49 | ulong cmd; |
| 50 | ulong op1; |
| 51 | ushort op2; |
| 52 | ulong res; |
| 53 | } cpu_post_threei_table[] = |
| 54 | { |
| 55 | { |
| 56 | OP_ORI, |
| 57 | 0x80000000, |
| 58 | 0xffff, |
| 59 | 0x8000ffff |
| 60 | }, |
| 61 | { |
| 62 | OP_ORIS, |
| 63 | 0x00008000, |
| 64 | 0xffff, |
| 65 | 0xffff8000 |
| 66 | }, |
| 67 | { |
| 68 | OP_XORI, |
| 69 | 0x8000ffff, |
| 70 | 0xffff, |
| 71 | 0x80000000 |
| 72 | }, |
| 73 | { |
| 74 | OP_XORIS, |
| 75 | 0x00008000, |
| 76 | 0xffff, |
| 77 | 0xffff8000 |
| 78 | }, |
| 79 | }; |
| 80 | static unsigned int cpu_post_threei_size = |
| 81 | sizeof (cpu_post_threei_table) / sizeof (struct cpu_post_threei_s); |
| 82 | |
| 83 | int cpu_post_test_threei (void) |
| 84 | { |
| 85 | int ret = 0; |
| 86 | unsigned int i, reg; |
| 87 | int flag = disable_interrupts(); |
| 88 | |
| 89 | for (i = 0; i < cpu_post_threei_size && ret == 0; i++) |
| 90 | { |
| 91 | struct cpu_post_threei_s *test = cpu_post_threei_table + i; |
| 92 | |
| 93 | for (reg = 0; reg < 32 && ret == 0; reg++) |
| 94 | { |
| 95 | unsigned int reg0 = (reg + 0) % 32; |
| 96 | unsigned int reg1 = (reg + 1) % 32; |
| 97 | unsigned int stk = reg < 16 ? 31 : 15; |
| 98 | unsigned long code[] = |
| 99 | { |
| 100 | ASM_STW(stk, 1, -4), |
| 101 | ASM_ADDI(stk, 1, -16), |
| 102 | ASM_STW(3, stk, 8), |
| 103 | ASM_STW(reg0, stk, 4), |
| 104 | ASM_STW(reg1, stk, 0), |
| 105 | ASM_LWZ(reg0, stk, 8), |
| 106 | ASM_11IX(test->cmd, reg1, reg0, test->op2), |
| 107 | ASM_STW(reg1, stk, 8), |
| 108 | ASM_LWZ(reg1, stk, 0), |
| 109 | ASM_LWZ(reg0, stk, 4), |
| 110 | ASM_LWZ(3, stk, 8), |
| 111 | ASM_ADDI(1, stk, 16), |
| 112 | ASM_LWZ(stk, 1, -4), |
| 113 | ASM_BLR, |
| 114 | }; |
| 115 | ulong res; |
| 116 | ulong cr; |
| 117 | |
| 118 | cr = 0; |
| 119 | cpu_post_exec_21 (code, & cr, & res, test->op1); |
| 120 | |
| 121 | ret = res == test->res && cr == 0 ? 0 : -1; |
| 122 | |
| 123 | if (ret != 0) |
| 124 | { |
| 125 | post_log ("Error at threei test %d !\n", i); |
| 126 | } |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | if (flag) |
| 131 | enable_interrupts(); |
| 132 | |
| 133 | return ret; |
| 134 | } |
| 135 | |
| 136 | #endif |
| 137 | #endif |