| Camelia Groza | 13ea307 | 2021-06-11 15:28:08 +0300 | [diff] [blame] | 1 | CONFIG_PPC=y |
| 2 | CONFIG_SYS_TEXT_BASE=0x00201000 |
| 3 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 4 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 5 | CONFIG_SYS_MEMTEST_START=0x00200000 |
| 6 | CONFIG_SYS_MEMTEST_END=0x00400000 |
| 7 | CONFIG_ENV_SIZE=0x2000 |
| 8 | CONFIG_ENV_OFFSET=0x100000 |
| 9 | CONFIG_ENV_SECT_SIZE=0x10000 |
| Tom Rini | 2bba780 | 2021-06-28 10:17:29 -0400 | [diff] [blame] | 10 | CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" |
| Camelia Groza | 13ea307 | 2021-06-11 15:28:08 +0300 | [diff] [blame] | 11 | CONFIG_SPL_TEXT_BASE=0xFFFD8000 |
| Simon Glass | 2a73606 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 12 | CONFIG_SPL_SERIAL=y |
| Simon Glass | 9ca0068 | 2021-07-10 21:14:31 -0600 | [diff] [blame] | 13 | CONFIG_SPL_DRIVERS_MISC=y |
| Camelia Groza | 13ea307 | 2021-06-11 15:28:08 +0300 | [diff] [blame] | 14 | CONFIG_SPL=y |
| 15 | CONFIG_SPL_SPI_FLASH_SUPPORT=y |
| Simon Glass | ea2ca7e | 2021-08-08 12:20:14 -0600 | [diff] [blame] | 16 | CONFIG_SPL_SPI=y |
| Camelia Groza | 13ea307 | 2021-06-11 15:28:08 +0300 | [diff] [blame] | 17 | CONFIG_MPC85xx=y |
| 18 | CONFIG_TARGET_T2080RDB=y |
| 19 | CONFIG_T2080RDB_REV_D=y |
| 20 | CONFIG_FIT=y |
| 21 | CONFIG_FIT_VERBOSE=y |
| 22 | CONFIG_OF_BOARD_SETUP=y |
| 23 | CONFIG_OF_STDOUT_VIA_ALIAS=y |
| Tom Rini | d8ef01e | 2021-08-24 23:11:49 -0400 | [diff] [blame] | 24 | CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" |
| 25 | CONFIG_RAMBOOT_PBL=y |
| 26 | CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg" |
| 27 | CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_spi_rcw.cfg" |
| Camelia Groza | 13ea307 | 2021-06-11 15:28:08 +0300 | [diff] [blame] | 28 | CONFIG_BOOTDELAY=10 |
| 29 | CONFIG_BOARD_EARLY_INIT_R=y |
| 30 | # CONFIG_SPL_FRAMEWORK is not set |
| 31 | CONFIG_SPL_SPI_BOOT=y |
| 32 | CONFIG_SPL_FSL_PBL=y |
| 33 | CONFIG_SPL_ENV_SUPPORT=y |
| Simon Glass | 975e7cf | 2021-07-10 21:14:36 -0600 | [diff] [blame] | 34 | CONFIG_SPL_I2C=y |
| Simon Glass | 6f004ad | 2021-08-08 12:20:16 -0600 | [diff] [blame] | 35 | CONFIG_SPL_MPC8XXX_INIT_DDR=y |
| Camelia Groza | 13ea307 | 2021-06-11 15:28:08 +0300 | [diff] [blame] | 36 | CONFIG_HUSH_PARSER=y |
| 37 | CONFIG_CMD_IMLS=y |
| Tom Rini | 88cd7d0 | 2021-08-17 17:59:45 -0400 | [diff] [blame] | 38 | CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 |
| Camelia Groza | 13ea307 | 2021-06-11 15:28:08 +0300 | [diff] [blame] | 39 | CONFIG_CMD_MEMTEST=y |
| 40 | CONFIG_SYS_ALT_MEMTEST=y |
| 41 | CONFIG_CMD_DM=y |
| 42 | CONFIG_CMD_I2C=y |
| 43 | CONFIG_CMD_MMC=y |
| 44 | CONFIG_CMD_USB=y |
| 45 | CONFIG_CMD_DHCP=y |
| 46 | CONFIG_CMD_MII=y |
| 47 | CONFIG_CMD_PING=y |
| 48 | CONFIG_MP=y |
| 49 | CONFIG_CMD_EXT2=y |
| 50 | CONFIG_CMD_FAT=y |
| 51 | CONFIG_CMD_MTDPARTS=y |
| 52 | CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" |
| 53 | CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)" |
| 54 | # CONFIG_CMD_IRQ is not set |
| 55 | CONFIG_OF_CONTROL=y |
| 56 | CONFIG_ENV_OVERWRITE=y |
| 57 | CONFIG_ENV_IS_IN_SPI_FLASH=y |
| 58 | CONFIG_DM=y |
| 59 | CONFIG_FSL_CAAM=y |
| Tom Rini | efb5dab7 | 2021-08-21 13:50:17 -0400 | [diff] [blame] | 60 | CONFIG_DDR_CLK_FREQ=133330000 |
| Tom Rini | 9537216 | 2021-08-21 13:50:18 -0400 | [diff] [blame] | 61 | CONFIG_DDR_ECC=y |
| 62 | CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y |
| Camelia Groza | 13ea307 | 2021-06-11 15:28:08 +0300 | [diff] [blame] | 63 | CONFIG_DM_I2C=y |
| Tom Rini | 55dabcc | 2021-08-18 23:12:24 -0400 | [diff] [blame] | 64 | CONFIG_SPL_SYS_I2C_LEGACY=y |
| Tom Rini | fc8d3b9 | 2021-08-18 23:12:37 -0400 | [diff] [blame] | 65 | CONFIG_I2C_SET_DEFAULT_BUS_NUM=y |
| Tom Rini | 6d5d0c9 | 2021-08-18 23:12:35 -0400 | [diff] [blame] | 66 | CONFIG_SYS_I2C_FSL=y |
| 67 | CONFIG_SYS_FSL_I2C_OFFSET=0x118000 |
| 68 | CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y |
| 69 | CONFIG_SYS_FSL_I2C2_OFFSET=0x118100 |
| 70 | CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y |
| 71 | CONFIG_SYS_FSL_I2C3_OFFSET=0x119000 |
| 72 | CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y |
| 73 | CONFIG_SYS_FSL_I2C4_OFFSET=0x119100 |
| Tom Rini | 88cd7d0 | 2021-08-17 17:59:45 -0400 | [diff] [blame] | 74 | CONFIG_SYS_I2C_EEPROM_ADDR=0x50 |
| Camelia Groza | 13ea307 | 2021-06-11 15:28:08 +0300 | [diff] [blame] | 75 | CONFIG_FSL_ESDHC=y |
| 76 | CONFIG_MTD=y |
| 77 | CONFIG_MTD_NOR_FLASH=y |
| 78 | CONFIG_FLASH_CFI_DRIVER=y |
| 79 | CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y |
| 80 | CONFIG_FLASH_CFI_MTD=y |
| 81 | CONFIG_SYS_FLASH_CFI=y |
| 82 | CONFIG_DM_SPI_FLASH=y |
| Camelia Groza | 13ea307 | 2021-06-11 15:28:08 +0300 | [diff] [blame] | 83 | CONFIG_SF_DEFAULT_SPEED=10000000 |
| 84 | CONFIG_SPI_FLASH_STMICRO=y |
| 85 | CONFIG_PHYLIB=y |
| 86 | CONFIG_PHY_AQUANTIA=y |
| 87 | CONFIG_PHY_CORTINA=y |
| 88 | CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y |
| Kuldeep Singh | e99b1df | 2021-08-10 11:20:07 +0530 | [diff] [blame] | 89 | CONFIG_CORTINA_FW_ADDR=0x120000 |
| Camelia Groza | 13ea307 | 2021-06-11 15:28:08 +0300 | [diff] [blame] | 90 | CONFIG_PHY_REALTEK=y |
| 91 | CONFIG_DM_ETH=y |
| 92 | CONFIG_DM_MDIO=y |
| 93 | CONFIG_E1000=y |
| 94 | CONFIG_FMAN_ENET=y |
| Rajesh Bhagat | a97a071 | 2021-11-09 16:30:38 +0530 | [diff] [blame^] | 95 | CONFIG_SYS_FMAN_FW_ADDR=0x110000 |
| Camelia Groza | 13ea307 | 2021-06-11 15:28:08 +0300 | [diff] [blame] | 96 | CONFIG_MII=y |
| Camelia Groza | 13ea307 | 2021-06-11 15:28:08 +0300 | [diff] [blame] | 97 | CONFIG_DM_PCI_COMPAT=y |
| 98 | CONFIG_PCIE_FSL=y |
| 99 | CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y |
| 100 | CONFIG_DM_RTC=y |
| 101 | CONFIG_RTC_DS1307=y |
| 102 | CONFIG_SYS_NS16550=y |
| 103 | CONFIG_SPI=y |
| 104 | CONFIG_DM_SPI=y |
| 105 | CONFIG_FSL_ESPI=y |
| 106 | CONFIG_USB=y |
| Camelia Groza | 13ea307 | 2021-06-11 15:28:08 +0300 | [diff] [blame] | 107 | CONFIG_USB_STORAGE=y |
| 108 | CONFIG_ADDR_MAP=y |
| 109 | CONFIG_SYS_NUM_ADDR_MAP=64 |