blob: 77909a8383326f77b10e13b4aff9bc63e3dea28c [file] [log] [blame]
Haiying Wangd11fec52006-05-26 10:24:48 -05001Freescale MPC8641HPCN board
2===========================
3
4Created 05/24/2006 Haiying Wang
5-------------------------------
6
71. Building U-Boot
8------------------
9The 86xx HPCN code base is known to compile using:
10 Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
11
12 $ make MPC8641HPCN_config
13 Configuring for MPC8641HPCN board...
14
15 $ make
16
17
182. Switch and Jumper Setting
19----------------------------
20Jumpers:
21 J14 Pins 1-2 (near plcc32 socket)
22
23Switches:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024 SW1(1-5) = 01100 CONFIG_SYS_COREPLL = 01000 :: CORE = 2:1
Haiying Wangd11fec52006-05-26 10:24:48 -050025 01100 :: CORE = 2.5:1
26 10000 :: CORE = 3:1
27 11100 :: CORE = 3.5:1
28 10100 :: CORE = 4:1
29 01110 :: CORE = 4.5:1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020030 SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz
Haiying Wangd11fec52006-05-26 10:24:48 -050031 001 :: SYSCLK = 40MHz
32
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033 SW2(1-4) = 1100 CONFIG_SYS_CCBPLL = 0010 :: 2X
Haiying Wangd11fec52006-05-26 10:24:48 -050034 0100 :: 4X
35 0110 :: 6X
36 1000 :: 8X
37 1010 :: 10X
38 1100 :: 12X
39 1110 :: 14X
40 0000 :: 16X
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041 SW2(5-8) = 1110 CONFIG_SYS_BOOTLOC = 1110 :: boot 16-bit localbus
Haiying Wangd11fec52006-05-26 10:24:48 -050042
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043 SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V
Haiying Wangd11fec52006-05-26 10:24:48 -050044 0100000 :: VCORE = 1.11V
45 SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
46 1 :: VCC_PLAT = 1.0V
47
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048 SW4(1-2) = 11 CONFIG_SYS_HOSTMODE = 11 :: both prots host/root
49 SW4(3-4) = 11 CONFIG_SYS_BOOTSEQ = 11 :: no boot seq
50 SW4(5-8) = 0011 CONFIG_SYS_IOPORT = 0011 :: both PEX
Haiying Wangd11fec52006-05-26 10:24:48 -050051
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052 SW5(1) = 1 CONFIG_SYS_FLASHMAP = 1 :: boot from flash
Haiying Wangd11fec52006-05-26 10:24:48 -050053 0 :: boot from PromJet
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054 SW5(2) = 1 CONFIG_SYS_FLASHBANK = 1 :: swap upper/lower
Haiying Wangd11fec52006-05-26 10:24:48 -050055 halves (virtual banks)
56 0 :: normal
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057 SW5(3) = 0 CONFIG_SYS_FLASHWP = 0 :: not protected
58 SW5(4) = 0 CONFIG_SYS_PORTDIV = 1 :: 2:1 for PD4
Haiying Wangd11fec52006-05-26 10:24:48 -050059 1:1 for PD6
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060 SW5(5-6) = 11 CONFIG_SYS_PIXISOPT = 11 :: s/w determined
61 SW5(7-8) = 11 CONFIG_SYS_LADOPT = 11 :: s/w determined
Haiying Wangd11fec52006-05-26 10:24:48 -050062
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063 SW6(1) = 1 CONFIG_SYS_CPUBOOT = 1 :: no boot holdoff
64 SW6(2) = 1 CONFIG_SYS_BOOTADDR = 1 :: no traslation
65 SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ
66 SW6(6) = 1 CONFIG_SYS_SERROM_ADDR= 1 ::
67 SW6(7) = 1 CONFIG_SYS_MEMDEBUG = 1 ::
68 SW6(8) = 1 CONFIG_SYS_DDRDEBUG = 1 ::
Haiying Wangd11fec52006-05-26 10:24:48 -050069
70 SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49
71 SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled
72 SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode
73 SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz
74 SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
75 SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled
76 SW8(7) = 1 ACPWR = 1 :: non-battery
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077 SW8(8) = 0 CONFIG_SYS_IDWP = 0 :: write enable
Haiying Wangd11fec52006-05-26 10:24:48 -050078
79
803. Flash U-Boot
81---------------
Becky Brucec759a012008-11-06 17:36:04 -060082The flash range 0xEF800000 to 0xEFFFFFFF can be divided into 2 halves.
Bin Menga1875592016-02-05 19:30:11 -080083It is possible to use either half to boot using U-Boot. Switch 5 bit 2
Haiying Wangd11fec52006-05-26 10:24:48 -050084is used for this purpose.
85
Becky Brucec759a012008-11-06 17:36:04 -0600860xEF800000 to 0xEFBFFFFF - 4MB
870xEFC00000 to 0xEFFFFFFF - 4MB
88When this bit is 0, U-Boot is at 0xEFF00000.
89When this bit is 1, U-Boot is at 0xEFB00000.
Haiying Wangd11fec52006-05-26 10:24:48 -050090
91Use the above mentioned flash commands to program the other half, and
92use switch 5, bit 2 to alternate between the halves. Note: The booting
Becky Brucec759a012008-11-06 17:36:04 -060093version of U-Boot will always be at 0xEFF00000.
Haiying Wangd11fec52006-05-26 10:24:48 -050094
Becky Brucec759a012008-11-06 17:36:04 -060095To Flash U-Boot into the booting bank (0xEFC00000 - 0xEFFFFFFF):
Haiying Wangd11fec52006-05-26 10:24:48 -050096
97 tftp 1000000 u-boot.bin
98 protect off all
Becky Brucec759a012008-11-06 17:36:04 -060099 erase eff00000 +$filesize
100 cp.b 1000000 eff00000 $filesize
Ed Swarthout32922cd2007-06-05 12:30:52 -0500101
102or use tftpflash command:
103 run tftpflash
Haiying Wangd11fec52006-05-26 10:24:48 -0500104
Bin Menga1875592016-02-05 19:30:11 -0800105To Flash U-Boot into the alternative bank (0xEF800000 - 0xEFBFFFFF):
Haiying Wangd11fec52006-05-26 10:24:48 -0500106
107 tftp 1000000 u-boot.bin
Becky Brucec759a012008-11-06 17:36:04 -0600108 erase efb00000 +$filesize
109 cp.b 1000000 efb00000 $filesize
Haiying Wangd11fec52006-05-26 10:24:48 -0500110
111
1124. Memory Map
113-------------
Becky Brucec759a012008-11-06 17:36:04 -0600114NOTE: RIO and PCI are mutually exclusive, so they share an address
Haiying Wangd11fec52006-05-26 10:24:48 -0500115
Bin Menga1875592016-02-05 19:30:11 -0800116For 32-bit U-Boot, devices are mapped so that the virtual address ==
Becky Bruce3111d322008-11-06 17:37:35 -0600117the physical address, and the map looks liks this:
118
Jon Loeligere10390d2006-10-10 17:06:53 -0500119 Memory Range Device Size
Haiying Wangd11fec52006-05-26 10:24:48 -0500120 ------------ ------ ----
121 0x0000_0000 0x7fff_ffff DDR 2G
Becky Brucec759a012008-11-06 17:36:04 -0600122 0x8000_0000 0x9fff_ffff RIO MEM 512M
Haiying Wangd11fec52006-05-26 10:24:48 -0500123 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
Becky Brucec759a012008-11-06 17:36:04 -0600124 0xa000_0000 0xbfff_ffff PCI2/PEX2 MEM 512M
125 0xffe0_0000 0xffef_ffff CCSR 1M
126 0xffdf_0000 0xffdf_7fff PIXIS 8K
127 0xffdf_8000 0xffdf_ffff CF 8K
Haiying Wangd11fec52006-05-26 10:24:48 -0500128 0xf840_0000 0xf840_3fff Stack space 32K
Becky Brucec759a012008-11-06 17:36:04 -0600129 0xffc0_0000 0xffc0_ffff PCI1/PEX1 IO 64K
130 0xffc1_0000 0xffc1_ffff PCI2/PEX2 IO 64K
131 0xef80_0000 0xefff_ffff Flash 8M
Haiying Wang3d98b852007-01-22 12:37:30 -0600132
Bin Menga1875592016-02-05 19:30:11 -0800133For 36-bit-enabled U-Boot, the virtual map is the same as for 32-bit.
Becky Bruce3111d322008-11-06 17:37:35 -0600134However, the physical map is altered to reside in 36-bit space, as follows.
135Addresses are no longer mapped with VA == PA. All accesses from
136software use the VA; the PA is only used for setting up windows
Becky Bruce29382d42008-11-20 16:43:52 -0600137and mappings. Note that with the exception of PCI MEM and RIO, the low
138 32 bits are the same as the VA above; only the top 4 bits vary:
Becky Bruce3111d322008-11-06 17:37:35 -0600139
140 Memory Range Device Size
141 ------------ ------ ----
142 0x0_0000_0000 0x0_7fff_ffff DDR 2G
Becky Bruce29382d42008-11-20 16:43:52 -0600143 0xc_0000_0000 0xc_1fff_ffff RIO MEM 512M
144 0xc_0000_0000 0xc_1fff_ffff PCI1/PEX1 MEM 512M
145 0xc_2000_0000 0xc_3fff_ffff PCI2/PEX2 MEM 512M
Becky Bruce3111d322008-11-06 17:37:35 -0600146 0xf_ffe0_0000 0xf_ffef_ffff CCSR 1M
147 0xf_ffdf_0000 0xf_ffdf_7fff PIXIS 8K
148 0xf_ffdf_8000 0xf_ffdf_ffff CF 8K
149 0x0_f840_0000 0xf_f840_3fff Stack space 32K
150 0xf_ffc0_0000 0xf_ffc0_ffff PCI1/PEX1 IO 64K
151 0xf_ffc1_0000 0xf_ffc1_ffff PCI2/PEX2 IO 64K
152 0xf_ef80_0000 0xf_efff_ffff Flash 8M
153
Haiying Wang3d98b852007-01-22 12:37:30 -06001545. pixis_reset command
155--------------------
156A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
157using the FPGA sequencer. When the board restarts, it has the option
158of using either the current or alternate flash bank as the boot
159image, with or without the watchdog timer enabled, and finally with
160or without frequency changes.
161
162Usage is;
163
164 pixis_reset
165 pixis_reset altbank
166 pixis_reset altbank wd
167 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
168 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
169
170Examples;
171
172 /* reset to current bank, like "reset" command */
173 pixis_reset
174
175 /* reset board but use the to alternate flash bank */
176 pixis_reset altbank
177
178 /* reset board, use alternate flash bank with watchdog timer enabled*/
179 pixis_reset altbank wd
180
181 /* reset board to alternate bank with frequency changed.
182 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
183 */
184 pixis-reset altbank cf 40 2.5 10
185
186Valid clock choices are in the 8641 Reference Manuals.