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Mike Rapoport36b4e2d2010-12-18 17:43:19 -05001/*
Nikita Kiryanovce15ec92012-01-02 04:01:31 +00002 * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il>
Mike Rapoport36b4e2d2010-12-18 17:43:19 -05003 *
Igor Grinbergdccd9a02011-04-18 17:48:31 -04004 * Authors: Mike Rapoport <mike@compulab.co.il>
5 * Igor Grinberg <grinberg@compulab.co.il>
Mike Rapoport36b4e2d2010-12-18 17:43:19 -05006 *
7 * Derived from omap3evm and Beagle Board by
8 * Manikandan Pillai <mani.pillai@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <x0khasim@ti.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
Igor Grinbergdccd9a02011-04-18 17:48:31 -040027 * Foundation, Inc.
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050028 */
29
30#include <common.h>
Igor Grinberg2b8754b2011-04-18 17:54:33 -040031#include <status_led.h>
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050032#include <netdev.h>
33#include <net.h>
34#include <i2c.h>
35#include <twl4030.h>
Nikita Kiryanov82309252012-01-12 03:26:30 +000036#include <linux/compiler.h>
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050037
38#include <asm/io.h>
39#include <asm/arch/mem.h>
40#include <asm/arch/mux.h>
41#include <asm/arch/mmc_host_def.h>
42#include <asm/arch/sys_proto.h>
43#include <asm/mach-types.h>
44
Nikita Kiryanove4e2bf52012-01-12 03:28:09 +000045#include "eeprom.h"
46
Igor Grinberg557aa152011-04-18 17:43:26 -040047DECLARE_GLOBAL_DATA_PTR;
48
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050049const omap3_sysinfo sysinfo = {
50 DDR_DISCRETE,
Igor Grinbergb65a77a2011-04-18 17:55:21 -040051 "CM-T3x board",
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050052 "NAND",
53};
54
55static u32 gpmc_net_config[GPMC_MAX_REG] = {
56 NET_GPMC_CONFIG1,
57 NET_GPMC_CONFIG2,
58 NET_GPMC_CONFIG3,
59 NET_GPMC_CONFIG4,
60 NET_GPMC_CONFIG5,
61 NET_GPMC_CONFIG6,
62 0
63};
64
65static u32 gpmc_nand_config[GPMC_MAX_REG] = {
66 SMNAND_GPMC_CONFIG1,
67 SMNAND_GPMC_CONFIG2,
68 SMNAND_GPMC_CONFIG3,
69 SMNAND_GPMC_CONFIG4,
70 SMNAND_GPMC_CONFIG5,
71 SMNAND_GPMC_CONFIG6,
72 0,
73};
74
75/*
76 * Routine: board_init
Igor Grinberg64f10842012-06-13 19:41:40 +000077 * Description: hardware init.
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050078 */
79int board_init(void)
80{
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050081 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
82
83 enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
84 CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
85
86 /* board id for Linux */
Igor Grinbergb65a77a2011-04-18 17:55:21 -040087 if (get_cpu_family() == CPU_OMAP34XX)
88 gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
89 else
90 gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
91
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050092 /* boot param addr */
93 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
94
Igor Grinberg2b8754b2011-04-18 17:54:33 -040095#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
96 status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
97#endif
98
Mike Rapoport36b4e2d2010-12-18 17:43:19 -050099 return 0;
100}
101
Nikita Kiryanov8c318eb2012-05-24 04:01:24 +0000102static u32 cm_t3x_rev;
103
104/*
105 * Routine: get_board_rev
106 * Description: read system revision
107 */
108u32 get_board_rev(void)
109{
110 if (!cm_t3x_rev)
111 cm_t3x_rev = cm_t3x_eeprom_get_board_rev();
112
113 return cm_t3x_rev;
114};
115
116/*
117 * Routine: misc_init_r
118 * Description: display die ID
119 */
120int misc_init_r(void)
121{
122 u32 board_rev = get_board_rev();
123 u32 rev_major = board_rev / 100;
124 u32 rev_minor = board_rev - (rev_major * 100);
125
126 if ((rev_minor / 10) * 10 == rev_minor)
127 rev_minor = rev_minor / 10;
128
129 printf("PCB: %u.%u\n", rev_major, rev_minor);
130 dieid_num_r();
131
132 return 0;
133}
134
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500135/*
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500136 * Routine: set_muxconf_regs
137 * Description: Setting up the configuration Mux registers specific to the
138 * hardware. Many pins need to be moved from protect to primary
139 * mode.
140 */
Igor Grinbergb65a77a2011-04-18 17:55:21 -0400141static void cm_t3x_set_common_muxconf(void)
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500142{
143 /* SDRC */
144 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
145 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
146 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
147 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
148 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
149 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
150 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
151 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
152 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
153 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
154 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
155 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
156 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
157 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
158 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
159 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
160 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
161 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
162 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
163 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
164 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
165 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
166 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
167 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
168 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
169 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
170 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
171 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
172 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
173 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
174 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
175 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
176 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
177 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
178 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
179 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
180 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
181 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
182 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
183
184 /* GPMC */
185 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
186 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
187 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
188 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
189 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
190 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
191 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
192 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
193 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
194 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
195 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
196 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
197 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
198 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
199 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
200 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
201 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
202 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
203 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
204 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
205 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
206 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
207 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
208 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
209 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
210 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
211 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
212
213 /* SB-T35 Ethernet */
214 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
215
Igor Grinbergb65a77a2011-04-18 17:55:21 -0400216 /* CM-T3x Ethernet */
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500217 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
218 MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
219 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
220 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/
221 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/
222 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/
223 MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/
224 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/
225 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/
226
227 /* DSS */
228 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
229 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
230 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
231 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500232 MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
233 MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
234 MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
235 MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
236 MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
237 MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
238 MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
239 MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
240 MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
241 MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
242 MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
243 MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500244
245 /* serial interface */
246 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/
247 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/
248
249 /* mUSB */
250 MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
251 MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
252 MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
253 MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
254 MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
255 MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
256 MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
257 MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
258 MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
259 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
260 MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
261 MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
262
263 /* I2C1 */
264 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
265 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
Nikita Kiryanov79874ae2012-04-02 02:29:31 +0000266 /* I2C2 */
267 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/
268 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/
269 /* I2C3 */
270 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/
271 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500272
273 /* control and debug */
274 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
275 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
276 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
277 MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
278 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
Igor Grinberg2b8754b2011-04-18 17:54:33 -0400279 MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500280 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/
281 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
282 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
283 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
Igor Grinbergeec70c22011-04-18 17:50:07 -0400284
285 /* MMC1 */
286 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
287 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
288 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
289 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
290 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
291 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
Igor Grinbergb65a77a2011-04-18 17:55:21 -0400292}
293
294static void cm_t35_set_muxconf(void)
295{
296 /* DSS */
297 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
298 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
299 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
300 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
301 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
302 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
303
304 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
305 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
306 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
307 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
308 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
309 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
310
311 /* MMC1 */
Igor Grinbergeec70c22011-04-18 17:50:07 -0400312 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/
313 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/
314 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/
315 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500316}
317
Igor Grinbergb65a77a2011-04-18 17:55:21 -0400318static void cm_t3730_set_muxconf(void)
319{
320 /* DSS */
321 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/
322 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/
323 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/
324 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/
325 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/
326 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/
327
328 MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/
329 MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/
330 MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/
331 MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/
332 MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/
333 MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/
334}
335
336void set_muxconf_regs(void)
337{
338 cm_t3x_set_common_muxconf();
339
340 if (get_cpu_family() == CPU_OMAP34XX)
341 cm_t35_set_muxconf();
342 else
343 cm_t3730_set_muxconf();
344}
345
Tom Rini28fed362011-09-03 21:49:24 -0400346#ifdef CONFIG_GENERIC_MMC
347int board_mmc_init(bd_t *bis)
348{
Jonathan Solnitbbbc1ae2012-02-24 11:30:18 +0000349 return omap_mmc_init(0, 0, 0);
Tom Rini28fed362011-09-03 21:49:24 -0400350}
351#endif
352
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500353/*
354 * Routine: setup_net_chip_gmpc
355 * Description: Setting up the configuration GPMC registers specific to the
356 * Ethernet hardware.
357 */
358static void setup_net_chip_gmpc(void)
359{
360 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
361
362 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
Igor Grinbergb65a77a2011-04-18 17:55:21 -0400363 CM_T3X_SMC911X_BASE, GPMC_SIZE_16M);
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500364 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
365 SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
366
367 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
368 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
369
370 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
371 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
372
373 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
374 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
375 &ctrl_base->gpmc_nadv_ale);
376}
377
378#ifdef CONFIG_DRIVER_OMAP34XX_I2C
379/*
380 * Routine: reset_net_chip
381 * Description: reset the Ethernet controller via TPS65930 GPIO
382 */
383static void reset_net_chip(void)
384{
385 /* Set GPIO1 of TPS65930 as output */
386 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
Igor Grinberg07277e72012-04-02 20:12:58 +0000387 TWL4030_BASEADD_GPIO + 0x03);
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500388 /* Send a pulse on the GPIO pin */
389 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
Igor Grinberg07277e72012-04-02 20:12:58 +0000390 TWL4030_BASEADD_GPIO + 0x0C);
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500391 udelay(1);
392 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
Igor Grinberg07277e72012-04-02 20:12:58 +0000393 TWL4030_BASEADD_GPIO + 0x09);
394 mdelay(40);
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500395 twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02,
Igor Grinberg07277e72012-04-02 20:12:58 +0000396 TWL4030_BASEADD_GPIO + 0x0C);
397 mdelay(1);
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500398}
399#else
400static inline void reset_net_chip(void) {}
401#endif
402
Nikita Kiryanovce15ec92012-01-02 04:01:31 +0000403#ifdef CONFIG_SMC911X
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500404/*
405 * Routine: handle_mac_address
406 * Description: prepare MAC address for on-board Ethernet.
407 */
408static int handle_mac_address(void)
409{
410 unsigned char enetaddr[6];
411 int rc;
412
413 rc = eth_getenv_enetaddr("ethaddr", enetaddr);
414 if (rc)
415 return 0;
416
Nikita Kiryanove4e2bf52012-01-12 03:28:09 +0000417 rc = cm_t3x_eeprom_read_mac_addr(enetaddr);
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500418 if (rc)
419 return rc;
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500420
421 if (!is_valid_ether_addr(enetaddr))
422 return -1;
423
424 return eth_setenv_enetaddr("ethaddr", enetaddr);
425}
426
427
428/*
429 * Routine: board_eth_init
430 * Description: initialize module and base-board Ethernet chips
431 */
432int board_eth_init(bd_t *bis)
433{
434 int rc = 0, rc1 = 0;
435
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500436 setup_net_chip_gmpc();
437 reset_net_chip();
438
439 rc1 = handle_mac_address();
440 if (rc1)
Igor Grinberg64f10842012-06-13 19:41:40 +0000441 printf("No MAC address found! ");
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500442
Igor Grinbergb65a77a2011-04-18 17:55:21 -0400443 rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500444 if (rc1 > 0)
445 rc++;
446
447 rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
448 if (rc1 > 0)
449 rc++;
Mike Rapoport36b4e2d2010-12-18 17:43:19 -0500450
451 return rc;
452}
Nikita Kiryanovce15ec92012-01-02 04:01:31 +0000453#endif
Nikita Kiryanov82309252012-01-12 03:26:30 +0000454
455void __weak get_board_serial(struct tag_serialnr *serialnr)
456{
457 /*
458 * This corresponds to what happens when we can communicate with the
459 * eeprom but don't get a valid board serial value.
460 */
461 serialnr->low = 0;
462 serialnr->high = 0;
463};