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TsiChung Liew8e585f02007-06-18 13:50:13 -05001/*
2 * MCF5329 Internal Memory Map
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __IMMAP_5329__
27#define __IMMAP_5329__
28
TsiChungLiew514871f2007-07-05 22:41:24 -050029#define MMAP_SCM1 0xEC000000
30#define MMAP_MDHA 0xEC080000
31#define MMAP_SKHA 0xEC084000
32#define MMAP_RNG 0xEC088000
33#define MMAP_SCM2 0xFC000000
34#define MMAP_XBS 0xFC004000
35#define MMAP_FBCS 0xFC008000
36#define MMAP_CAN 0xFC020000
37#define MMAP_FEC 0xFC030000
38#define MMAP_SCM3 0xFC040000
39#define MMAP_EDMA 0xFC044000
40#define MMAP_TCD 0xFC045000
41#define MMAP_INTC0 0xFC048000
42#define MMAP_INTC1 0xFC04C000
43#define MMAP_INTCACK 0xFC054000
44#define MMAP_I2C 0xFC058000
45#define MMAP_QSPI 0xFC05C000
46#define MMAP_UART0 0xFC060000
47#define MMAP_UART1 0xFC064000
48#define MMAP_UART2 0xFC068000
49#define MMAP_DTMR0 0xFC070000
50#define MMAP_DTMR1 0xFC074000
51#define MMAP_DTMR2 0xFC078000
52#define MMAP_DTMR3 0xFC07C000
53#define MMAP_PIT0 0xFC080000
54#define MMAP_PIT1 0xFC084000
55#define MMAP_PIT2 0xFC088000
56#define MMAP_PIT3 0xFC08C000
57#define MMAP_PWM 0xFC090000
58#define MMAP_EPORT 0xFC094000
59#define MMAP_WDOG 0xFC098000
TsiChungLiew248c7c12007-11-07 17:56:15 -060060#define MMAP_RCM 0xFC0A0000
61#define MMAP_CCM 0xFC0A0004
TsiChungLiew514871f2007-07-05 22:41:24 -050062#define MMAP_GPIO 0xFC0A4000
63#define MMAP_RTC 0xFC0A8000
64#define MMAP_LCDC 0xFC0AC000
65#define MMAP_USBOTG 0xFC0B0000
66#define MMAP_USBH 0xFC0B4000
67#define MMAP_SDRAM 0xFC0B8000
68#define MMAP_SSI 0xFC0BC000
69#define MMAP_PLL 0xFC0C0000
TsiChung Liew8e585f02007-06-18 13:50:13 -050070
TsiChungLiewd9aae622008-01-14 16:59:42 -060071#include <asm/coldfire/crossbar.h>
72#include <asm/coldfire/edma.h>
73#include <asm/coldfire/flexbus.h>
74#include <asm/coldfire/lcd.h>
75#include <asm/coldfire/ssi.h>
76
TsiChung Liew8e585f02007-06-18 13:50:13 -050077/* System control module registers */
78typedef struct scm1_ctrl {
79 u32 mpr0; /* 0x00 Master Privilege Register 0 */
80 u32 res1[15]; /* 0x04 - 0x3F */
81 u32 pacrh; /* 0x40 Peripheral Access Control Register H */
82 u32 res2[3]; /* 0x44 - 0x53 */
83 u32 bmt0; /*0x54 Bus Monitor Timeout 0 */
84} scm1_t;
85
86/* Message Digest Hardware Accelerator */
87typedef struct mdha_ctrl {
88 u32 mdmr; /* 0x00 MDHA Mode Register */
89 u32 mdcr; /* 0x04 Control register */
90 u32 mdcmr; /* 0x08 Command Register */
91 u32 mdsr; /* 0x0C Status Register */
92 u32 mdisr; /* 0x10 Interrupt Status Register */
93 u32 mdimr; /* 0x14 Interrupt Mask Register */
94 u32 mddsr; /* 0x1C Data Size Register */
95 u32 mdin; /* 0x20 Input FIFO */
96 u32 res1[3]; /* 0x24 - 0x2F */
97 u32 mdao; /* 0x30 Message Digest AO Register */
98 u32 mdbo; /* 0x34 Message Digest BO Register */
99 u32 mdco; /* 0x38 Message Digest CO Register */
100 u32 mddo; /* 0x3C Message Digest DO Register */
101 u32 mdeo; /* 0x40 Message Digest EO Register */
102 u32 mdmds; /* 0x44 Message Data Size Register */
103 u32 res[10]; /* 0x48 - 0x6F */
104 u32 mda1; /* 0x70 Message Digest A1 Register */
105 u32 mdb1; /* 0x74 Message Digest B1 Register */
106 u32 mdc1; /* 0x78 Message Digest C1 Register */
107 u32 mdd1; /* 0x7C Message Digest D1 Register */
108 u32 mde1; /* 0x80 Message Digest E1 Register */
109} mdha_t;
110
111/* Symmetric Key Hardware Accelerator */
112typedef struct skha_ctrl {
113 u32 mr; /* 0x00 Mode Register */
114 u32 cr; /* 0x04 Control Register */
115 u32 cmr; /* 0x08 Command Register */
116 u32 sr; /* 0x0C Status Register */
117 u32 esr; /* 0x10 Error Status Register */
118 u32 emr; /* 0x14 Error Status Mask Register) */
119 u32 ksr; /* 0x18 Key Size Register */
120 u32 dsr; /* 0x1C Data Size Register */
121 u32 in; /* 0x20 Input FIFO */
122 u32 out; /* 0x24 Output FIFO */
123 u32 res1[2]; /* 0x28 - 0x2F */
124 u32 kdr1; /* 0x30 Key Data Register 1 */
125 u32 kdr2; /* 0x34 Key Data Register 2 */
126 u32 kdr3; /* 0x38 Key Data Register 3 */
127 u32 kdr4; /* 0x3C Key Data Register 4 */
128 u32 kdr5; /* 0x40 Key Data Register 5 */
129 u32 kdr6; /* 0x44 Key Data Register 6 */
130 u32 res2[10]; /* 0x48 - 0x6F */
131 u32 c1; /* 0x70 Context 1 */
132 u32 c2; /* 0x74 Context 2 */
133 u32 c3; /* 0x78 Context 3 */
134 u32 c4; /* 0x7C Context 4 */
135 u32 c5; /* 0x80 Context 5 */
136 u32 c6; /* 0x84 Context 6 */
137 u32 c7; /* 0x88 Context 7 */
138 u32 c8; /* 0x8C Context 8 */
139 u32 c9; /* 0x90 Context 9 */
140 u32 c10; /* 0x94 Context 10 */
141 u32 c11; /* 0x98 Context 11 */
142} skha_t;
143
144/* Random Number Generator */
145typedef struct rng_ctrl {
146 u32 rngcr; /* 0x00 RNG Control Register */
147 u32 rngsr; /* 0x04 RNG Status Register */
148 u32 rnger; /* 0x08 RNG Entropy Register */
149 u32 rngout; /* 0x0C RNG Output FIFO */
150} rng_t;
151
152/* System control module registers 2 */
153typedef struct scm2_ctrl {
154 u32 mpr1; /* 0x00 Master Privilege Register */
155 u32 res1[7]; /* 0x04 - 0x1F */
156 u32 pacra; /* 0x20 Peripheral Access Control Register A */
157 u32 pacrb; /* 0x24 Peripheral Access Control Register B */
158 u32 pacrc; /* 0x28 Peripheral Access Control Register C */
159 u32 pacrd; /* 0x2C Peripheral Access Control Register D */
160 u32 res2[4]; /* 0x30 - 0x3F */
161 u32 pacre; /* 0x40 Peripheral Access Control Register E */
162 u32 pacrf; /* 0x44 Peripheral Access Control Register F */
163 u32 pacrg; /* 0x48 Peripheral Access Control Register G */
164 u32 res3[2]; /* 0x4C - 0x53 */
165 u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */
166} scm2_t;
167
TsiChung Liew8e585f02007-06-18 13:50:13 -0500168/* FlexCan module registers */
169typedef struct can_ctrl {
170 u32 mcr; /* 0x00 Module Configuration register */
171 u32 ctrl; /* 0x04 Control register */
172 u32 timer; /* 0x08 Free Running Timer */
173 u32 res1; /* 0x0C */
174 u32 rxgmask; /* 0x10 Rx Global Mask */
175 u32 rx14mask; /* 0x14 RxBuffer 14 Mask */
176 u32 rx15mask; /* 0x18 RxBuffer 15 Mask */
177 u32 errcnt; /* 0x1C Error Counter Register */
178 u32 errstat; /* 0x20 Error and status Register */
179 u32 res2; /* 0x24 */
180 u32 imask; /* 0x28 Interrupt Mask Register */
181 u32 res3; /* 0x2C */
182 u32 iflag; /* 0x30 Interrupt Flag Register */
183 u32 res4[19]; /* 0x34 - 0x7F */
184 u32 MB0_15[2048]; /* 0x80 Message Buffer 0-15 */
185} can_t;
186
187/* System Control Module register 3 */
188typedef struct scm3_ctrl {
189 u8 res1[19]; /* 0x00 - 0x12 */
190 u8 wcr; /* 0x13 wakeup control register */
191 u16 res2; /* 0x14 - 0x15 */
192 u16 cwcr; /* 0x16 Core Watchdog Control Register */
193 u8 res3[3]; /* 0x18 - 0x1A */
194 u8 cwsr; /* 0x1B Core Watchdog Service Register */
195 u8 res4[2]; /* 0x1C - 0x1D */
196 u8 scmisr; /* 0x1F Interrupt Status Register */
197 u32 res5; /* 0x20 */
198 u32 bcr; /* 0x24 Burst Configuration Register */
199 u32 res6[18]; /* 0x28 - 0x6F */
200 u32 cfadr; /* 0x70 Core Fault Address Register */
201 u8 res7[4]; /* 0x71 - 0x74 */
202 u8 cfier; /* 0x75 Core Fault Interrupt Enable Register */
203 u8 cfloc; /* 0x76 Core Fault Location Register */
204 u8 cfatr; /* 0x77 Core Fault Attributes Register */
205 u32 res8; /* 0x78 */
206 u32 cfdtr; /* 0x7C Core Fault Data Register */
207} scm3_t;
208
TsiChung Liew8e585f02007-06-18 13:50:13 -0500209/* Interrupt module registers */
210typedef struct int0_ctrl {
211 /* Interrupt Controller 0 */
212 u32 iprh0; /* 0x00 Pending Register High */
213 u32 iprl0; /* 0x04 Pending Register Low */
214 u32 imrh0; /* 0x08 Mask Register High */
215 u32 imrl0; /* 0x0C Mask Register Low */
216 u32 frch0; /* 0x10 Force Register High */
217 u32 frcl0; /* 0x14 Force Register Low */
218 u16 res1; /* 0x18 - 0x19 */
219 u16 icfg0; /* 0x1A Configuration Register */
220 u8 simr0; /* 0x1C Set Interrupt Mask */
221 u8 cimr0; /* 0x1D Clear Interrupt Mask */
222 u8 clmask0; /* 0x1E Current Level Mask */
223 u8 slmask; /* 0x1F Saved Level Mask */
224 u32 res2[8]; /* 0x20 - 0x3F */
225 u8 icr0[64]; /* 0x40 - 0x7F Control registers */
226 u32 res3[24]; /* 0x80 - 0xDF */
227 u8 swiack0; /* 0xE0 Software Interrupt Acknowledge */
228 u8 res4[3]; /* 0xE1 - 0xE3 */
229 u8 Lniack0_1; /* 0xE4 Level n interrupt acknowledge resister */
230 u8 res5[3]; /* 0xE5 - 0xE7 */
231 u8 Lniack0_2; /* 0xE8 Level n interrupt acknowledge resister */
232 u8 res6[3]; /* 0xE9 - 0xEB */
233 u8 Lniack0_3; /* 0xEC Level n interrupt acknowledge resister */
234 u8 res7[3]; /* 0xED - 0xEF */
235 u8 Lniack0_4; /* 0xF0 Level n interrupt acknowledge resister */
236 u8 res8[3]; /* 0xF1 - 0xF3 */
237 u8 Lniack0_5; /* 0xF4 Level n interrupt acknowledge resister */
238 u8 res9[3]; /* 0xF5 - 0xF7 */
239 u8 Lniack0_6; /* 0xF8 Level n interrupt acknowledge resister */
240 u8 resa[3]; /* 0xF9 - 0xFB */
241 u8 Lniack0_7; /* 0xFC Level n interrupt acknowledge resister */
242 u8 resb[3]; /* 0xFD - 0xFF */
243} int0_t;
244
245typedef struct int1_ctrl {
246 /* Interrupt Controller 1 */
247 u32 iprh1; /* 0x00 Pending Register High */
248 u32 iprl1; /* 0x04 Pending Register Low */
249 u32 imrh1; /* 0x08 Mask Register High */
250 u32 imrl1; /* 0x0C Mask Register Low */
251 u32 frch1; /* 0x10 Force Register High */
252 u32 frcl1; /* 0x14 Force Register Low */
253 u16 res1; /* 0x18 */
254 u16 icfg1; /* 0x1A Configuration Register */
255 u8 simr1; /* 0x1C Set Interrupt Mask */
256 u8 cimr1; /* 0x1D Clear Interrupt Mask */
257 u16 res2; /* 0x1E - 0x1F */
258 u32 res3[8]; /* 0x20 - 0x3F */
259 u8 icr1[64]; /* 0x40 - 0x7F */
260 u32 res4[24]; /* 0x80 - 0xDF */
261 u8 swiack1; /* 0xE0 Software Interrupt Acknowledge */
262 u8 res5[3]; /* 0xE1 - 0xE3 */
263 u8 Lniack1_1; /* 0xE4 Level n interrupt acknowledge resister */
264 u8 res6[3]; /* 0xE5 - 0xE7 */
265 u8 Lniack1_2; /* 0xE8 Level n interrupt acknowledge resister */
266 u8 res7[3]; /* 0xE9 - 0xEB */
267 u8 Lniack1_3; /* 0xEC Level n interrupt acknowledge resister */
268 u8 res8[3]; /* 0xED - 0xEF */
269 u8 Lniack1_4; /* 0xF0 Level n interrupt acknowledge resister */
270 u8 res9[3]; /* 0xF1 - 0xF3 */
271 u8 Lniack1_5; /* 0xF4 Level n interrupt acknowledge resister */
272 u8 resa[3]; /* 0xF5 - 0xF7 */
273 u8 Lniack1_6; /* 0xF8 Level n interrupt acknowledge resister */
274 u8 resb[3]; /* 0xF9 - 0xFB */
275 u8 Lniack1_7; /* 0xFC Level n interrupt acknowledge resister */
276 u8 resc[3]; /* 0xFD - 0xFF */
277} int1_t;
278
279typedef struct intgack_ctrl1 {
280 /* Global IACK Registers */
281 u8 swiack; /* 0xE0 Global Software Interrupt Acknowledge */
282 u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
283} intgack_t;
284
TsiChung Liew8e585f02007-06-18 13:50:13 -0500285/* QSPI module registers */
286typedef struct qspi_ctrl {
287 u16 qmr; /* Mode register */
288 u16 res1;
289 u16 qdlyr; /* Delay register */
290 u16 res2;
291 u16 qwr; /* Wrap register */
292 u16 res3;
293 u16 qir; /* Interrupt register */
294 u16 res4;
295 u16 qar; /* Address register */
296 u16 res5;
297 u16 qdr; /* Data register */
298 u16 res6;
299} qspi_t;
300
301/* PWM module registers */
302typedef struct pwm_ctrl {
303 u8 en; /* 0x00 PWM Enable Register */
304 u8 pol; /* 0x01 Polarity Register */
305 u8 clk; /* 0x02 Clock Select Register */
306 u8 prclk; /* 0x03 Prescale Clock Select Register */
307 u8 cae; /* 0x04 Center Align Enable Register */
308 u8 ctl; /* 0x05 Control Register */
309 u8 res1[2]; /* 0x06 - 0x07 */
310 u8 scla; /* 0x08 Scale A register */
311 u8 sclb; /* 0x09 Scale B register */
312 u8 res2[2]; /* 0x0A - 0x0B */
313 u8 cnt0; /* 0x0C Channel 0 Counter register */
314 u8 cnt1; /* 0x0D Channel 1 Counter register */
315 u8 cnt2; /* 0x0E Channel 2 Counter register */
316 u8 cnt3; /* 0x0F Channel 3 Counter register */
317 u8 cnt4; /* 0x10 Channel 4 Counter register */
318 u8 cnt5; /* 0x11 Channel 5 Counter register */
319 u8 cnt6; /* 0x12 Channel 6 Counter register */
320 u8 cnt7; /* 0x13 Channel 7 Counter register */
321 u8 per0; /* 0x14 Channel 0 Period register */
322 u8 per1; /* 0x15 Channel 1 Period register */
323 u8 per2; /* 0x16 Channel 2 Period register */
324 u8 per3; /* 0x17 Channel 3 Period register */
325 u8 per4; /* 0x18 Channel 4 Period register */
326 u8 per5; /* 0x19 Channel 5 Period register */
327 u8 per6; /* 0x1A Channel 6 Period register */
328 u8 per7; /* 0x1B Channel 7 Period register */
329 u8 dty0; /* 0x1C Channel 0 Duty register */
330 u8 dty1; /* 0x1D Channel 1 Duty register */
331 u8 dty2; /* 0x1E Channel 2 Duty register */
332 u8 dty3; /* 0x1F Channel 3 Duty register */
333 u8 dty4; /* 0x20 Channel 4 Duty register */
334 u8 dty5; /* 0x21 Channel 5 Duty register */
335 u8 dty6; /* 0x22 Channel 6 Duty register */
336 u8 dty7; /* 0x23 Channel 7 Duty register */
337 u8 sdn; /* 0x24 Shutdown register */
338 u8 res3[3]; /* 0x25 - 0x27 */
339} pwm_t;
340
341/* Edge Port module registers */
342typedef struct eport_ctrl {
343 u16 par; /* 0x00 Pin Assignment Register */
344 u8 ddar; /* 0x02 Data Direction Register */
345 u8 ier; /* 0x03 Interrupt Enable Register */
346 u8 dr; /* 0x04 Data Register */
347 u8 pdr; /* 0x05 Pin Data Register */
348 u8 fr; /* 0x06 Flag_Register */
349 u8 res1;
350} eport_t;
351
352/* Watchdog registers */
353typedef struct wdog_ctrl {
354 u16 cr; /* 0x00 Control register */
355 u16 mr; /* 0x02 Modulus register */
356 u16 cntr; /* 0x04 Count register */
357 u16 sr; /* 0x06 Service register */
358} wdog_t;
359
360/*Chip configuration module registers */
361typedef struct ccm_ctrl {
TsiChungLiew8d737a22007-11-08 12:50:18 -0600362 u16 ccr; /* 0x00 Chip configuration register */
363 u16 res2; /* 0x02 */
364 u16 rcon; /* 0x04 Rreset configuration register */
365 u16 cir; /* 0x06 Chip identification register */
366 u32 res3; /* 0x08 */
367 u16 misccr; /* 0x0A Miscellaneous control register */
368 u16 cdr; /* 0x0C Clock divider register */
369 u16 uhcsr; /* 0x10 USB Host controller status register */
370 u16 uocsr; /* 0x12 USB On-the-Go Controller Status Reg */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500371} ccm_t;
372
TsiChungLiew7d7cdea2007-11-08 12:31:11 -0600373typedef struct rcm {
374 u8 rcr;
375 u8 rsr;
376} rcm_t;
377
TsiChung Liew8e585f02007-06-18 13:50:13 -0500378/* GPIO port registers */
379typedef struct gpio_ctrl {
380 /* Port Output Data Registers */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600381#ifdef CONFIG_M5329
TsiChung Liew8e585f02007-06-18 13:50:13 -0500382 u8 podr_fech; /* 0x00 */
383 u8 podr_fecl; /* 0x01 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600384#else
385 u16 res00; /* 0x00 - 0x01 */
386#endif
TsiChung Liew8e585f02007-06-18 13:50:13 -0500387 u8 podr_ssi; /* 0x02 */
388 u8 podr_busctl; /* 0x03 */
389 u8 podr_be; /* 0x04 */
390 u8 podr_cs; /* 0x05 */
391 u8 podr_pwm; /* 0x06 */
392 u8 podr_feci2c; /* 0x07 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600393 u8 res08; /* 0x08 */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500394 u8 podr_uart; /* 0x09 */
395 u8 podr_qspi; /* 0x0A */
396 u8 podr_timer; /* 0x0B */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600397#ifdef CONFIG_M5329
398 u8 res0C; /* 0x0C */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500399 u8 podr_lcddatah; /* 0x0D */
400 u8 podr_lcddatam; /* 0x0E */
401 u8 podr_lcddatal; /* 0x0F */
402 u8 podr_lcdctlh; /* 0x10 */
403 u8 podr_lcdctll; /* 0x11 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600404#else
405 u16 res0C; /* 0x0C - 0x0D */
406 u8 podr_fech; /* 0x0E */
407 u8 podr_fecl; /* 0x0F */
408 u16 res10[3]; /* 0x10 - 0x15 */
409#endif
TsiChung Liew8e585f02007-06-18 13:50:13 -0500410
411 /* Port Data Direction Registers */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600412#ifdef CONFIG_M5329
413 u16 res12; /* 0x12 - 0x13 */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500414 u8 pddr_fech; /* 0x14 */
415 u8 pddr_fecl; /* 0x15 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600416#endif
TsiChung Liew8e585f02007-06-18 13:50:13 -0500417 u8 pddr_ssi; /* 0x16 */
418 u8 pddr_busctl; /* 0x17 */
419 u8 pddr_be; /* 0x18 */
420 u8 pddr_cs; /* 0x19 */
421 u8 pddr_pwm; /* 0x1A */
422 u8 pddr_feci2c; /* 0x1B */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600423 u8 res1C; /* 0x1C */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500424 u8 pddr_uart; /* 0x1D */
425 u8 pddr_qspi; /* 0x1E */
426 u8 pddr_timer; /* 0x1F */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600427#ifdef CONFIG_M5329
428 u8 res20; /* 0x20 */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500429 u8 pddr_lcddatah; /* 0x21 */
430 u8 pddr_lcddatam; /* 0x22 */
431 u8 pddr_lcddatal; /* 0x23 */
432 u8 pddr_lcdctlh; /* 0x24 */
433 u8 pddr_lcdctll; /* 0x25 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600434 u16 res26; /* 0x26 - 0x27 */
435#else
436 u16 res20; /* 0x20 - 0x21 */
437 u8 pddr_fech; /* 0x22 */
438 u8 pddr_fecl; /* 0x23 */
439 u16 res24[3]; /* 0x24 - 0x29 */
440#endif
TsiChung Liew8e585f02007-06-18 13:50:13 -0500441
442 /* Port Data Direction Registers */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600443#ifdef CONFIG_M5329
TsiChung Liew8e585f02007-06-18 13:50:13 -0500444 u8 ppd_fech; /* 0x28 */
445 u8 ppd_fecl; /* 0x29 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600446#endif
TsiChung Liew8e585f02007-06-18 13:50:13 -0500447 u8 ppd_ssi; /* 0x2A */
448 u8 ppd_busctl; /* 0x2B */
449 u8 ppd_be; /* 0x2C */
450 u8 ppd_cs; /* 0x2D */
451 u8 ppd_pwm; /* 0x2E */
452 u8 ppd_feci2c; /* 0x2F */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600453 u8 res30; /* 0x30 */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500454 u8 ppd_uart; /* 0x31 */
455 u8 ppd_qspi; /* 0x32 */
456 u8 ppd_timer; /* 0x33 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600457#ifdef CONFIG_M5329
458 u8 res34; /* 0x34 */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500459 u8 ppd_lcddatah; /* 0x35 */
460 u8 ppd_lcddatam; /* 0x36 */
461 u8 ppd_lcddatal; /* 0x37 */
462 u8 ppd_lcdctlh; /* 0x38 */
463 u8 ppd_lcdctll; /* 0x39 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600464 u16 res3A; /* 0x3A - 0x3B */
465#else
466 u16 res34; /* 0x34 - 0x35 */
467 u8 ppd_fech; /* 0x36 */
468 u8 ppd_fecl; /* 0x37 */
469 u16 res38[3]; /* 0x38 - 0x3D */
470#endif
TsiChung Liew8e585f02007-06-18 13:50:13 -0500471
472 /* Port Clear Output Data Registers */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600473#ifdef CONFIG_M5329
474 u8 res3C; /* 0x3C */
475 u8 pclrr_fech; /* 0x3D */
476 u8 pclrr_fecl; /* 0x3E */
477#else
TsiChung Liew8e585f02007-06-18 13:50:13 -0500478 u8 pclrr_ssi; /* 0x3E */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600479#endif
TsiChung Liew8e585f02007-06-18 13:50:13 -0500480 u8 pclrr_busctl; /* 0x3F */
481 u8 pclrr_be; /* 0x40 */
482 u8 pclrr_cs; /* 0x41 */
483 u8 pclrr_pwm; /* 0x42 */
484 u8 pclrr_feci2c; /* 0x43 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600485 u8 res44; /* 0x44 */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500486 u8 pclrr_uart; /* 0x45 */
487 u8 pclrr_qspi; /* 0x46 */
488 u8 pclrr_timer; /* 0x47 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600489#ifdef CONFIG_M5329
490 u8 pclrr_lcddatah; /* 0x48 */
491 u8 pclrr_lcddatam; /* 0x49 */
492 u8 pclrr_lcddatal; /* 0x4A */
493 u8 pclrr_ssi; /* 0x4B */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500494 u8 pclrr_lcdctlh; /* 0x4C */
495 u8 pclrr_lcdctll; /* 0x4D */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600496 u16 res4E; /* 0x4E - 0x4F */
497#else
498 u16 res48; /* 0x48 - 0x49 */
499 u8 pclrr_fech; /* 0x4A */
500 u8 pclrr_fecl; /* 0x4B */
501 u8 res4C[5]; /* 0x4C - 0x50 */
502#endif
TsiChung Liew8e585f02007-06-18 13:50:13 -0500503
504 /* Pin Assignment Registers */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600505#ifdef CONFIG_M5329
TsiChung Liew8e585f02007-06-18 13:50:13 -0500506 u8 par_fec; /* 0x50 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600507#endif
TsiChung Liew8e585f02007-06-18 13:50:13 -0500508 u8 par_pwm; /* 0x51 */
509 u8 par_busctl; /* 0x52 */
510 u8 par_feci2c; /* 0x53 */
511 u8 par_be; /* 0x54 */
512 u8 par_cs; /* 0x55 */
513 u16 par_ssi; /* 0x56 */
514 u16 par_uart; /* 0x58 */
515 u16 par_qspi; /* 0x5A */
516 u8 par_timer; /* 0x5C */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600517#ifdef CONFIG_M5329
TsiChung Liew8e585f02007-06-18 13:50:13 -0500518 u8 par_lcddata; /* 0x5D */
519 u16 par_lcdctl; /* 0x5E */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600520#else
521 u8 par_fec; /* 0x5D */
522 u16 res5E; /* 0x5E - 0x5F */
523#endif
TsiChung Liew8e585f02007-06-18 13:50:13 -0500524 u16 par_irq; /* 0x60 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600525 u16 res62; /* 0x62 - 0x63 */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500526
527 /* Mode Select Control Registers */
528 u8 mscr_flexbus; /* 0x64 */
529 u8 mscr_sdram; /* 0x65 */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600530 u16 res66; /* 0x66 - 0x67 */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500531
532 /* Drive Strength Control Registers */
533 u8 dscr_i2c; /* 0x68 */
534 u8 dscr_pwm; /* 0x69 */
535 u8 dscr_fec; /* 0x6A */
536 u8 dscr_uart; /* 0x6B */
537 u8 dscr_qspi; /* 0x6C */
538 u8 dscr_timer; /* 0x6D */
539 u8 dscr_ssi; /* 0x6E */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600540#ifdef CONFIG_M5329
TsiChung Liew8e585f02007-06-18 13:50:13 -0500541 u8 dscr_lcd; /* 0x6F */
TsiChungLiewaa5f1f92008-01-14 17:23:08 -0600542#else
543 u8 res6F; /* 0x6F */
544#endif
TsiChung Liew8e585f02007-06-18 13:50:13 -0500545 u8 dscr_debug; /* 0x70 */
546 u8 dscr_clkrst; /* 0x71 */
547 u8 dscr_irq; /* 0x72 */
548} gpio_t;
549
TsiChung Liew8e585f02007-06-18 13:50:13 -0500550/* USB OTG module registers */
551typedef struct usb_otg {
552 u32 id; /* 0x000 Identification Register */
553 u32 hwgeneral; /* 0x004 General HW Parameters */
554 u32 hwhost; /* 0x008 Host HW Parameters */
555 u32 hwdev; /* 0x00C Device HW parameters */
556 u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */
557 u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */
558 u32 res1[58]; /* 0x18 - 0xFF */
559 u8 caplength; /* 0x100 Capability Register Length */
560 u8 res2; /* 0x101 */
561 u16 hciver; /* 0x102 Host Interface Version Number */
562 u32 hcsparams; /* 0x104 Host Structural Parameters */
563 u32 hccparams; /* 0x108 Host Capability Parameters */
564 u32 res3[5]; /* 0x10C - 0x11F */
565 u16 dciver; /* 0x120 Device Interface Version Number */
566 u16 res4; /* 0x122 */
567 u32 dccparams; /* 0x124 Device Capability Parameters */
568 u32 res5[6]; /* 0x128 - 0x13F */
569 u32 cmd; /* 0x140 USB Command */
570 u32 sts; /* 0x144 USB Status */
571 u32 intr; /* 0x148 USB Interrupt Enable */
572 u32 frindex; /* 0x14C USB Frame Index */
573 u32 res6; /* 0x150 */
574 u32 prd_dev; /* 0x154 Periodic Frame List Base or Device Address */
575 u32 aync_ep; /* 0x158 Current Asynchronous List or Address at Endpoint List Address */
576 u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control */
577 u32 burstsize; /* 0x160 Master Interface Data Burst Size */
578 u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control */
579 u32 res7[6]; /* 0x168 - 0x17F */
580 u32 cfgflag; /* 0x180 Configure Flag Register */
581 u32 portsc1; /* 0x184 Port Status/Control */
582 u32 res8[7]; /* 0x188 - 0x1A3 */
583 u32 otgsc; /* 0x1A4 On The Go Status and Control */
584 u32 mode; /* 0x1A8 USB mode register */
585 u32 eptsetstat; /* 0x1AC Endpoint Setup status */
586 u32 eptprime; /* 0x1B0 Endpoint initialization */
587 u32 eptflush; /* 0x1B4 Endpoint de-initialize */
588 u32 eptstat; /* 0x1B8 Endpoint status */
589 u32 eptcomplete; /* 0x1BC Endpoint Complete */
590 u32 eptctrl0; /* 0x1C0 Endpoint control 0 */
591 u32 eptctrl1; /* 0x1C4 Endpoint control 1 */
592 u32 eptctrl2; /* 0x1C8 Endpoint control 2 */
593 u32 eptctrl3; /* 0x1CC Endpoint control 3 */
594} usbotg_t;
595
596/* USB Host module registers */
597typedef struct usb_host {
598 u32 id; /* 0x000 Identification Register */
599 u32 hwgeneral; /* 0x004 General HW Parameters */
600 u32 hwhost; /* 0x008 Host HW Parameters */
601 u32 res1; /* 0x0C */
602 u32 hwtxbuf; /* 0x010 TX Buffer HW Parameters */
603 u32 hwrxbuf; /* 0x014 RX Buffer HW Parameters */
604 u32 res2[58]; /* 0x18 - 0xFF */
605
606 /* Host Controller Capability Register */
607 u8 caplength; /* 0x100 Capability Register Length */
608 u8 res3; /* 0x101 */
609 u16 hciver; /* 0x102 Host Interface Version Number */
610 u32 hcsparams; /* 0x104 Host Structural Parameters */
611 u32 hccparams; /* 0x108 Host Capability Parameters */
612 u32 res4[13]; /* 0x10C - 0x13F */
613
614 /* Host Controller Operational Register */
615 u32 cmd; /* 0x140 USB Command */
616 u32 sts; /* 0x144 USB Status */
617 u32 intr; /* 0x148 USB Interrupt Enable */
618 u32 frindex; /* 0x14C USB Frame Index */
619 u32 res5; /* 0x150 (ctrl segment register in EHCI spec) */
620 u32 prdlst; /* 0x154 Periodic Frame List Base Address */
621 u32 aynclst; /* 0x158 Current Asynchronous List Address */
622 u32 ttctrl; /* 0x15C Host TT Asynchronous Buffer Control (non-ehci) */
623 u32 burstsize; /* 0x160 Master Interface Data Burst Size (non-ehci) */
624 u32 txfill; /* 0x164 Host Transmit FIFO Tuning Control (non-ehci) */
625 u32 res6[6]; /* 0x168 - 0x17F */
626 u32 cfgflag; /* 0x180 Configure Flag Register */
627 u32 portsc1; /* 0x184 Port Status/Control */
628 u32 res7[8]; /* 0x188 - 0x1A7 */
629
630 /* non-ehci registers */
631 u32 mode; /* 0x1A8 USB mode register */
632 u32 eptsetstat; /* 0x1AC Endpoint Setup status */
633 u32 eptprime; /* 0x1B0 Endpoint initialization */
634 u32 eptflush; /* 0x1B4 Endpoint de-initialize */
635 u32 eptstat; /* 0x1B8 Endpoint status */
636 u32 eptcomplete; /* 0x1BC Endpoint Complete */
637 u32 eptctrl0; /* 0x1C0 Endpoint control 0 */
638 u32 eptctrl1; /* 0x1C4 Endpoint control 1 */
639 u32 eptctrl2; /* 0x1C8 Endpoint control 2 */
640 u32 eptctrl3; /* 0x1CC Endpoint control 3 */
641} usbhost_t;
642
643/* SDRAM controller registers */
644typedef struct sdram_ctrl {
645 u32 mode; /* 0x00 Mode/Extended Mode register */
646 u32 ctrl; /* 0x04 Control register */
647 u32 cfg1; /* 0x08 Configuration register 1 */
648 u32 cfg2; /* 0x0C Configuration register 2 */
649 u32 res1[64]; /* 0x10 - 0x10F */
650 u32 cs0; /* 0x110 Chip Select 0 Configuration */
651 u32 cs1; /* 0x114 Chip Select 1 Configuration */
652} sdram_t;
653
TsiChung Liew8e585f02007-06-18 13:50:13 -0500654/* Clock Module registers */
655typedef struct pll_ctrl {
656 u8 podr; /* 0x00 Output Divider Register */
657 u8 res1[3];
658 u8 pcr; /* 0x04 Control Register */
659 u8 res2[3];
660 u8 pmdr; /* 0x08 Modulation Divider Register */
661 u8 res3[3];
662 u8 pfdr; /* 0x0C Feedback Divider Register */
663 u8 res4[3];
664} pll_t;
665
666#endif /* __IMMAP_5329__ */