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stroese13fdf8a2003-09-12 08:55:18 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
stroese13fdf8a2003-09-12 08:55:18 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_405EP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000021#define CONFIG_DP405 1 /* ...on a DP405 board */
stroese13fdf8a2003-09-12 08:55:18 +000022
Wolfgang Denk2ae18242010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
24
wdenkc837dcb2004-01-20 23:12:12 +000025#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
26#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroese13fdf8a2003-09-12 08:55:18 +000027
stroesea20b27a2004-12-16 18:05:42 +000028#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */
stroese13fdf8a2003-09-12 08:55:18 +000029
30#define CONFIG_BAUDRATE 9600
31#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
32
33#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000034#undef CONFIG_BOOTCOMMAND
stroese13fdf8a2003-09-12 08:55:18 +000035
stroesea20b27a2004-12-16 18:05:42 +000036#define CONFIG_PREBOOT /* enable preboot variable */
37
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroese13fdf8a2003-09-12 08:55:18 +000039
Jon Loeliger11799432007-07-10 09:02:57 -050040/*
Jon Loeliger3c3227f2007-07-07 20:40:43 -050041 * Command line configuration.
42 */
43#include <config_cmd_default.h>
44
45#define CONFIG_CMD_BSP
Jon Loeliger3c3227f2007-07-07 20:40:43 -050046#define CONFIG_CMD_ELF
Jon Loeliger3c3227f2007-07-07 20:40:43 -050047#define CONFIG_CMD_I2C
48#define CONFIG_CMD_EEPROM
49
Matthias Fuchsde47a342009-04-29 09:51:00 +020050#undef CONFIG_CMD_NET
Wolfgang Denkee8028b2010-11-21 20:55:42 +010051#undef CONFIG_CMD_NFS
stroese13fdf8a2003-09-12 08:55:18 +000052
wdenkc837dcb2004-01-20 23:12:12 +000053#undef CONFIG_WATCHDOG /* watchdog disabled */
stroese13fdf8a2003-09-12 08:55:18 +000054
wdenkc837dcb2004-01-20 23:12:12 +000055#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
stroese13fdf8a2003-09-12 08:55:18 +000056
stroesea20b27a2004-12-16 18:05:42 +000057#define CONFIG_PRAM 2 /* reserve 2 kB "protected RAM" */
58
stroese13fdf8a2003-09-12 08:55:18 +000059/*
60 * Miscellaneous configurable options
61 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_LONGHELP /* undef to save memory */
stroese13fdf8a2003-09-12 08:55:18 +000063
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
stroese13fdf8a2003-09-12 08:55:18 +000065
Jon Loeliger3c3227f2007-07-07 20:40:43 -050066#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +000068#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +000070#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
72#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
73#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +000074
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroese13fdf8a2003-09-12 08:55:18 +000076
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroese13fdf8a2003-09-12 08:55:18 +000078
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
80#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroese13fdf8a2003-09-12 08:55:18 +000081
Stefan Roese550650d2010-09-20 16:05:31 +020082#define CONFIG_CONS_INDEX 1 /* Use UART0 */
83#define CONFIG_SYS_NS16550
84#define CONFIG_SYS_NS16550_SERIAL
85#define CONFIG_SYS_NS16550_REG_SIZE 1
86#define CONFIG_SYS_NS16550_CLK get_serial_clock()
87
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_BASE_BAUD 691200
stroese13fdf8a2003-09-12 08:55:18 +000090
91/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_BAUDRATE_TABLE \
stroese13fdf8a2003-09-12 08:55:18 +000093 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
94 57600, 115200, 230400, 460800, 921600 }
95
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
97#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroese13fdf8a2003-09-12 08:55:18 +000098
stroese13fdf8a2003-09-12 08:55:18 +000099#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
100
wdenkc837dcb2004-01-20 23:12:12 +0000101#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese13fdf8a2003-09-12 08:55:18 +0000102
stroese13fdf8a2003-09-12 08:55:18 +0000103/*
104 * For booting Linux, the board info and command line data
105 * have to be in the first 8 MB of memory, since this is
106 * the maximum mapped by the Linux kernel during initialization.
107 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
stroese13fdf8a2003-09-12 08:55:18 +0000109/*-----------------------------------------------------------------------
110 * FLASH organization
111 */
112#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
115#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
stroese13fdf8a2003-09-12 08:55:18 +0000116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
118#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
stroese13fdf8a2003-09-12 08:55:18 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
121#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
122#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroese13fdf8a2003-09-12 08:55:18 +0000123/*
124 * The following defines are added for buggy IOP480 byte interface.
125 * All other boards should use the standard values (CPCI405 etc.)
126 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
128#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
129#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
stroese13fdf8a2003-09-12 08:55:18 +0000130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroese13fdf8a2003-09-12 08:55:18 +0000132
stroese13fdf8a2003-09-12 08:55:18 +0000133/*-----------------------------------------------------------------------
134 * Start addresses for the final memory configuration
135 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroese13fdf8a2003-09-12 08:55:18 +0000137 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_SDRAM_BASE 0x00000000
Matthias Fuchsde47a342009-04-29 09:51:00 +0200139#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200140#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
141#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
Matthias Fuchsde47a342009-04-29 09:51:00 +0200142#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
stroese13fdf8a2003-09-12 08:55:18 +0000143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
145# define CONFIG_SYS_RAMBOOT 1
stroese13fdf8a2003-09-12 08:55:18 +0000146#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147# undef CONFIG_SYS_RAMBOOT
stroese13fdf8a2003-09-12 08:55:18 +0000148#endif
149
150/*-----------------------------------------------------------------------
151 * Environment Variable setup
152 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200153#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200154#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
155#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
stroese13fdf8a2003-09-12 08:55:18 +0000156 /* total size of a CAT24WC16 is 2048 bytes */
157
stroese13fdf8a2003-09-12 08:55:18 +0000158/*-----------------------------------------------------------------------
159 * I2C EEPROM (CAT24WC16) for environment
160 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000161#define CONFIG_SYS_I2C
162#define CONFIG_SYS_I2C_PPC4XX
163#define CONFIG_SYS_I2C_PPC4XX_CH0
164#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
165#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
stroese13fdf8a2003-09-12 08:55:18 +0000166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
168#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +0000169/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
171#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
stroese13fdf8a2003-09-12 08:55:18 +0000172 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000173 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroese13fdf8a2003-09-12 08:55:18 +0000175
176/*-----------------------------------------------------------------------
stroese13fdf8a2003-09-12 08:55:18 +0000177 * External Bus Controller (EBC) Setup
178 */
179
wdenkc837dcb2004-01-20 23:12:12 +0000180#define CAN_BA 0xF0000000 /* CAN Base Address */
stroese13fdf8a2003-09-12 08:55:18 +0000181
wdenkc837dcb2004-01-20 23:12:12 +0000182/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_EBC_PB0AP 0x92015480
184#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroese13fdf8a2003-09-12 08:55:18 +0000185
wdenkc837dcb2004-01-20 23:12:12 +0000186/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
188#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000189
190/*-----------------------------------------------------------------------
191 * FPGA stuff
192 */
stroese13fdf8a2003-09-12 08:55:18 +0000193/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
195#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
196#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
197#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
198#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
stroese13fdf8a2003-09-12 08:55:18 +0000199
200/*-----------------------------------------------------------------------
201 * Definitions for initial stack pointer and data area (in data cache)
202 */
203/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_TEMP_STACK_OCM 1
stroese13fdf8a2003-09-12 08:55:18 +0000205
206/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
208#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
209#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200210#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
stroese13fdf8a2003-09-12 08:55:18 +0000211
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200212#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroese13fdf8a2003-09-12 08:55:18 +0000214
215/*-----------------------------------------------------------------------
216 * Definitions for GPIO setup (PPC405EP specific)
217 *
wdenkc837dcb2004-01-20 23:12:12 +0000218 * GPIO0[0] - External Bus Controller BLAST output
219 * GPIO0[1-9] - Instruction trace outputs -> GPIO
stroese13fdf8a2003-09-12 08:55:18 +0000220 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
221 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
222 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
223 * GPIO0[24-27] - UART0 control signal inputs/outputs
224 * GPIO0[28-29] - UART1 data signal input/output
225 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
226 */
wdenkc837dcb2004-01-20 23:12:12 +0000227/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
228/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
229/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
stroese13fdf8a2003-09-12 08:55:18 +0000230/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200231#define CONFIG_SYS_GPIO0_OSRL 0x40000540 /* 0 ... 15 */
232#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */
233#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */
234#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */
235#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */
236#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */
Matthias Fuchsde47a342009-04-29 09:51:00 +0200237#define CONFIG_SYS_GPIO0_TCR 0xB7FE0014 /* 0 ... 31 */
stroese13fdf8a2003-09-12 08:55:18 +0000238
239/*
stroese13fdf8a2003-09-12 08:55:18 +0000240 * Default speed selection (cpu_plb_opb_ebc) in mhz.
241 * This value will be set if iic boot eprom is disabled.
242 */
wdenkc837dcb2004-01-20 23:12:12 +0000243#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
244#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000245
246#endif /* __CONFIG_H */