blob: 94c89c762b6ffe47c210946235c567f00f59ed7c [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01002/*
3 * Copyright (C) 2005-2006 Atmel Corporation
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01004 */
5#include <common.h>
Wenyou Yang577aa3b2016-11-02 10:06:56 +08006#include <clk.h>
Simon Glassf1dcc192016-05-05 07:28:11 -06007#include <dm.h>
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01008
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01009/*
10 * The u-boot networking stack is a little weird. It seems like the
11 * networking core allocates receive buffers up front without any
12 * regard to the hardware that's supposed to actually receive those
13 * packets.
14 *
15 * The MACB receives packets into 128-byte receive buffers, so the
16 * buffers allocated by the core isn't very practical to use. We'll
17 * allocate our own, but we need one such buffer in case a packet
18 * wraps around the DMA ring so that we have to copy it.
19 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020020 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010021 * configuration header. This way, the core allocates one RX buffer
22 * and one TX buffer, each of which can hold a ethernet packet of
23 * maximum size.
24 *
25 * For some reason, the networking core unconditionally specifies a
26 * 32-byte packet "alignment" (which really should be called
27 * "padding"). MACB shouldn't need that, but we'll refrain from any
28 * core modifications here...
29 */
30
31#include <net.h>
Simon Glassf1dcc192016-05-05 07:28:11 -060032#ifndef CONFIG_DM_ETH
Ben Warren89973f82008-08-31 22:22:04 -070033#include <netdev.h>
Simon Glassf1dcc192016-05-05 07:28:11 -060034#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010035#include <malloc.h>
Semih Hazar0f751d62009-12-17 15:07:15 +020036#include <miiphy.h>
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010037
38#include <linux/mii.h>
39#include <asm/io.h>
40#include <asm/dma-mapping.h>
41#include <asm/arch/clk.h>
Masahiro Yamada5d97dff2016-09-21 11:28:57 +090042#include <linux/errno.h>
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010043
44#include "macb.h"
45
Wenyou Yanga212b662016-05-17 13:11:35 +080046DECLARE_GLOBAL_DATA_PTR;
47
Andreas Bießmannceef9832014-05-26 22:55:18 +020048#define MACB_RX_BUFFER_SIZE 4096
49#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
50#define MACB_TX_RING_SIZE 16
51#define MACB_TX_TIMEOUT 1000
52#define MACB_AUTONEG_TIMEOUT 5000000
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010053
Wilson Lee4bf56912017-08-22 20:25:07 -070054#ifdef CONFIG_MACB_ZYNQ
55/* INCR4 AHB bursts */
56#define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
57/* Use full configured addressable space (8 Kb) */
58#define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
59/* Use full configured addressable space (4 Kb) */
60#define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
61/* Set RXBUF with use of 128 byte */
62#define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
63#define MACB_ZYNQ_GEM_DMACR_INIT \
64 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
65 MACB_ZYNQ_GEM_DMACR_RXSIZE | \
66 MACB_ZYNQ_GEM_DMACR_TXSIZE | \
67 MACB_ZYNQ_GEM_DMACR_RXBUF)
68#endif
69
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010070struct macb_dma_desc {
71 u32 addr;
72 u32 ctrl;
73};
74
Wu, Josh5ae0e382014-05-27 16:31:05 +080075#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
76#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
77#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
Wu, Joshade4ea42015-06-03 16:45:44 +080078#define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
Wu, Josh5ae0e382014-05-27 16:31:05 +080079
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010080#define RXADDR_USED 0x00000001
81#define RXADDR_WRAP 0x00000002
82
83#define RXBUF_FRMLEN_MASK 0x00000fff
84#define RXBUF_FRAME_START 0x00004000
85#define RXBUF_FRAME_END 0x00008000
86#define RXBUF_TYPEID_MATCH 0x00400000
87#define RXBUF_ADDR4_MATCH 0x00800000
88#define RXBUF_ADDR3_MATCH 0x01000000
89#define RXBUF_ADDR2_MATCH 0x02000000
90#define RXBUF_ADDR1_MATCH 0x04000000
91#define RXBUF_BROADCAST 0x80000000
92
93#define TXBUF_FRMLEN_MASK 0x000007ff
94#define TXBUF_FRAME_END 0x00008000
95#define TXBUF_NOCRC 0x00010000
96#define TXBUF_EXHAUSTED 0x08000000
97#define TXBUF_UNDERRUN 0x10000000
98#define TXBUF_MAXRETRY 0x20000000
99#define TXBUF_WRAP 0x40000000
100#define TXBUF_USED 0x80000000
101
102struct macb_device {
103 void *regs;
104
105 unsigned int rx_tail;
106 unsigned int tx_head;
107 unsigned int tx_tail;
Simon Glassd5555b72016-05-05 07:28:09 -0600108 unsigned int next_rx_tail;
109 bool wrapped;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100110
111 void *rx_buffer;
112 void *tx_buffer;
113 struct macb_dma_desc *rx_ring;
114 struct macb_dma_desc *tx_ring;
115
116 unsigned long rx_buffer_dma;
117 unsigned long rx_ring_dma;
118 unsigned long tx_ring_dma;
119
Wu, Joshade4ea42015-06-03 16:45:44 +0800120 struct macb_dma_desc *dummy_desc;
121 unsigned long dummy_desc_dma;
122
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100123 const struct device *dev;
Simon Glassf1dcc192016-05-05 07:28:11 -0600124#ifndef CONFIG_DM_ETH
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100125 struct eth_device netdev;
Simon Glassf1dcc192016-05-05 07:28:11 -0600126#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100127 unsigned short phy_addr;
Bo Shenb1a00062013-04-24 15:59:27 +0800128 struct mii_dev *bus;
Wenyou Yang1870d4d2017-04-14 14:36:04 +0800129#ifdef CONFIG_PHYLIB
130 struct phy_device *phydev;
131#endif
Wenyou Yanga212b662016-05-17 13:11:35 +0800132
133#ifdef CONFIG_DM_ETH
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +0800134#ifdef CONFIG_CLK
Wenyou Yang577aa3b2016-11-02 10:06:56 +0800135 unsigned long pclk_rate;
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +0800136#endif
Wenyou Yanga212b662016-05-17 13:11:35 +0800137 phy_interface_t phy_interface;
138#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100139};
Simon Glassf1dcc192016-05-05 07:28:11 -0600140#ifndef CONFIG_DM_ETH
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100141#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
Simon Glassf1dcc192016-05-05 07:28:11 -0600142#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100143
Bo Shend256be22013-04-24 15:59:28 +0800144static int macb_is_gem(struct macb_device *macb)
145{
146 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
147}
148
Gregory CLEMENT75b03cf2015-12-16 14:50:34 +0100149#ifndef cpu_is_sama5d2
150#define cpu_is_sama5d2() 0
151#endif
152
153#ifndef cpu_is_sama5d4
154#define cpu_is_sama5d4() 0
155#endif
156
157static int gem_is_gigabit_capable(struct macb_device *macb)
158{
159 /*
Robert P. J. Day1cc0a9f2016-05-04 04:47:31 -0400160 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
Gregory CLEMENT75b03cf2015-12-16 14:50:34 +0100161 * configured to support only 10/100.
162 */
163 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
164}
165
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100166static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
167{
168 unsigned long netctl;
169 unsigned long netstat;
170 unsigned long frame;
171
172 netctl = macb_readl(macb, NCR);
173 netctl |= MACB_BIT(MPE);
174 macb_writel(macb, NCR, netctl);
175
176 frame = (MACB_BF(SOF, 1)
177 | MACB_BF(RW, 1)
178 | MACB_BF(PHYA, macb->phy_addr)
179 | MACB_BF(REGA, reg)
180 | MACB_BF(CODE, 2)
181 | MACB_BF(DATA, value));
182 macb_writel(macb, MAN, frame);
183
184 do {
185 netstat = macb_readl(macb, NSR);
186 } while (!(netstat & MACB_BIT(IDLE)));
187
188 netctl = macb_readl(macb, NCR);
189 netctl &= ~MACB_BIT(MPE);
190 macb_writel(macb, NCR, netctl);
191}
192
193static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
194{
195 unsigned long netctl;
196 unsigned long netstat;
197 unsigned long frame;
198
199 netctl = macb_readl(macb, NCR);
200 netctl |= MACB_BIT(MPE);
201 macb_writel(macb, NCR, netctl);
202
203 frame = (MACB_BF(SOF, 1)
204 | MACB_BF(RW, 2)
205 | MACB_BF(PHYA, macb->phy_addr)
206 | MACB_BF(REGA, reg)
207 | MACB_BF(CODE, 2));
208 macb_writel(macb, MAN, frame);
209
210 do {
211 netstat = macb_readl(macb, NSR);
212 } while (!(netstat & MACB_BIT(IDLE)));
213
214 frame = macb_readl(macb, MAN);
215
216 netctl = macb_readl(macb, NCR);
217 netctl &= ~MACB_BIT(MPE);
218 macb_writel(macb, NCR, netctl);
219
220 return MACB_BFEXT(DATA, frame);
221}
222
Joe Hershberger1b8c18b2013-06-24 19:06:38 -0500223void __weak arch_get_mdio_control(const char *name)
Shiraz Hashim416ce622012-12-13 17:22:52 +0530224{
225 return;
226}
227
Bo Shenb1a00062013-04-24 15:59:27 +0800228#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
Semih Hazar0f751d62009-12-17 15:07:15 +0200229
Joe Hershberger5a49f172016-08-08 11:28:38 -0500230int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
Semih Hazar0f751d62009-12-17 15:07:15 +0200231{
Joe Hershberger5a49f172016-08-08 11:28:38 -0500232 u16 value = 0;
Simon Glassf1dcc192016-05-05 07:28:11 -0600233#ifdef CONFIG_DM_ETH
Joe Hershberger5a49f172016-08-08 11:28:38 -0500234 struct udevice *dev = eth_get_dev_by_name(bus->name);
Simon Glassf1dcc192016-05-05 07:28:11 -0600235 struct macb_device *macb = dev_get_priv(dev);
236#else
Joe Hershberger5a49f172016-08-08 11:28:38 -0500237 struct eth_device *dev = eth_get_dev_by_name(bus->name);
Semih Hazar0f751d62009-12-17 15:07:15 +0200238 struct macb_device *macb = to_macb(dev);
Simon Glassf1dcc192016-05-05 07:28:11 -0600239#endif
Semih Hazar0f751d62009-12-17 15:07:15 +0200240
Andreas Bießmannceef9832014-05-26 22:55:18 +0200241 if (macb->phy_addr != phy_adr)
Semih Hazar0f751d62009-12-17 15:07:15 +0200242 return -1;
243
Joe Hershberger5a49f172016-08-08 11:28:38 -0500244 arch_get_mdio_control(bus->name);
245 value = macb_mdio_read(macb, reg);
Semih Hazar0f751d62009-12-17 15:07:15 +0200246
Joe Hershberger5a49f172016-08-08 11:28:38 -0500247 return value;
Semih Hazar0f751d62009-12-17 15:07:15 +0200248}
249
Joe Hershberger5a49f172016-08-08 11:28:38 -0500250int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
251 u16 value)
Semih Hazar0f751d62009-12-17 15:07:15 +0200252{
Simon Glassf1dcc192016-05-05 07:28:11 -0600253#ifdef CONFIG_DM_ETH
Joe Hershberger5a49f172016-08-08 11:28:38 -0500254 struct udevice *dev = eth_get_dev_by_name(bus->name);
Simon Glassf1dcc192016-05-05 07:28:11 -0600255 struct macb_device *macb = dev_get_priv(dev);
256#else
Joe Hershberger5a49f172016-08-08 11:28:38 -0500257 struct eth_device *dev = eth_get_dev_by_name(bus->name);
Semih Hazar0f751d62009-12-17 15:07:15 +0200258 struct macb_device *macb = to_macb(dev);
Simon Glassf1dcc192016-05-05 07:28:11 -0600259#endif
Semih Hazar0f751d62009-12-17 15:07:15 +0200260
Andreas Bießmannceef9832014-05-26 22:55:18 +0200261 if (macb->phy_addr != phy_adr)
Semih Hazar0f751d62009-12-17 15:07:15 +0200262 return -1;
263
Joe Hershberger5a49f172016-08-08 11:28:38 -0500264 arch_get_mdio_control(bus->name);
Semih Hazar0f751d62009-12-17 15:07:15 +0200265 macb_mdio_write(macb, reg, value);
266
267 return 0;
268}
269#endif
270
Wu, Josh5ae0e382014-05-27 16:31:05 +0800271#define RX 1
272#define TX 0
273static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
274{
275 if (rx)
Heiko Schocher592a7492016-08-29 07:46:11 +0200276 invalidate_dcache_range(macb->rx_ring_dma,
277 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
278 PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800279 else
Heiko Schocher592a7492016-08-29 07:46:11 +0200280 invalidate_dcache_range(macb->tx_ring_dma,
281 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
282 PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800283}
284
285static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
286{
287 if (rx)
288 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
Heiko Schocher592a7492016-08-29 07:46:11 +0200289 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800290 else
291 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
Heiko Schocher592a7492016-08-29 07:46:11 +0200292 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800293}
294
295static inline void macb_flush_rx_buffer(struct macb_device *macb)
296{
297 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
Heiko Schocher592a7492016-08-29 07:46:11 +0200298 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800299}
300
301static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
302{
303 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
Heiko Schocher592a7492016-08-29 07:46:11 +0200304 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800305}
Semih Hazar0f751d62009-12-17 15:07:15 +0200306
Jon Loeliger07d38a12007-07-09 17:30:01 -0500307#if defined(CONFIG_CMD_NET)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100308
Simon Glassd5555b72016-05-05 07:28:09 -0600309static int _macb_send(struct macb_device *macb, const char *name, void *packet,
310 int length)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100311{
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100312 unsigned long paddr, ctrl;
313 unsigned int tx_head = macb->tx_head;
314 int i;
315
316 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
317
318 ctrl = length & TXBUF_FRMLEN_MASK;
319 ctrl |= TXBUF_FRAME_END;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200320 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100321 ctrl |= TXBUF_WRAP;
322 macb->tx_head = 0;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200323 } else {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100324 macb->tx_head++;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200325 }
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100326
327 macb->tx_ring[tx_head].ctrl = ctrl;
328 macb->tx_ring[tx_head].addr = paddr;
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200329 barrier();
Wu, Josh5ae0e382014-05-27 16:31:05 +0800330 macb_flush_ring_desc(macb, TX);
331 /* Do we need check paddr and length is dcache line aligned? */
Simon Glassf589f8c2016-05-05 07:28:10 -0600332 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100333 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
334
335 /*
336 * I guess this is necessary because the networking core may
337 * re-use the transmit buffer as soon as we return...
338 */
Andreas Bießmannceef9832014-05-26 22:55:18 +0200339 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200340 barrier();
Wu, Josh5ae0e382014-05-27 16:31:05 +0800341 macb_invalidate_ring_desc(macb, TX);
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200342 ctrl = macb->tx_ring[tx_head].ctrl;
343 if (ctrl & TXBUF_USED)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100344 break;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100345 udelay(1);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100346 }
347
348 dma_unmap_single(packet, length, paddr);
349
Andreas Bießmannceef9832014-05-26 22:55:18 +0200350 if (i <= MACB_TX_TIMEOUT) {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100351 if (ctrl & TXBUF_UNDERRUN)
Simon Glassd5555b72016-05-05 07:28:09 -0600352 printf("%s: TX underrun\n", name);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100353 if (ctrl & TXBUF_EXHAUSTED)
Simon Glassd5555b72016-05-05 07:28:09 -0600354 printf("%s: TX buffers exhausted in mid frame\n", name);
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200355 } else {
Simon Glassd5555b72016-05-05 07:28:09 -0600356 printf("%s: TX timeout\n", name);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100357 }
358
359 /* No one cares anyway */
360 return 0;
361}
362
363static void reclaim_rx_buffers(struct macb_device *macb,
364 unsigned int new_tail)
365{
366 unsigned int i;
367
368 i = macb->rx_tail;
Wu, Josh5ae0e382014-05-27 16:31:05 +0800369
370 macb_invalidate_ring_desc(macb, RX);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100371 while (i > new_tail) {
372 macb->rx_ring[i].addr &= ~RXADDR_USED;
373 i++;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200374 if (i > MACB_RX_RING_SIZE)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100375 i = 0;
376 }
377
378 while (i < new_tail) {
379 macb->rx_ring[i].addr &= ~RXADDR_USED;
380 i++;
381 }
382
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200383 barrier();
Wu, Josh5ae0e382014-05-27 16:31:05 +0800384 macb_flush_ring_desc(macb, RX);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100385 macb->rx_tail = new_tail;
386}
387
Simon Glassd5555b72016-05-05 07:28:09 -0600388static int _macb_recv(struct macb_device *macb, uchar **packetp)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100389{
Simon Glassd5555b72016-05-05 07:28:09 -0600390 unsigned int next_rx_tail = macb->next_rx_tail;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100391 void *buffer;
392 int length;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100393 u32 status;
394
Simon Glassd5555b72016-05-05 07:28:09 -0600395 macb->wrapped = false;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100396 for (;;) {
Wu, Josh5ae0e382014-05-27 16:31:05 +0800397 macb_invalidate_ring_desc(macb, RX);
398
Simon Glassd5555b72016-05-05 07:28:09 -0600399 if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
400 return -EAGAIN;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100401
Simon Glassd5555b72016-05-05 07:28:09 -0600402 status = macb->rx_ring[next_rx_tail].ctrl;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100403 if (status & RXBUF_FRAME_START) {
Simon Glassd5555b72016-05-05 07:28:09 -0600404 if (next_rx_tail != macb->rx_tail)
405 reclaim_rx_buffers(macb, next_rx_tail);
406 macb->wrapped = false;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100407 }
408
409 if (status & RXBUF_FRAME_END) {
410 buffer = macb->rx_buffer + 128 * macb->rx_tail;
411 length = status & RXBUF_FRMLEN_MASK;
Wu, Josh5ae0e382014-05-27 16:31:05 +0800412
413 macb_invalidate_rx_buffer(macb);
Simon Glassd5555b72016-05-05 07:28:09 -0600414 if (macb->wrapped) {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100415 unsigned int headlen, taillen;
416
Andreas Bießmannceef9832014-05-26 22:55:18 +0200417 headlen = 128 * (MACB_RX_RING_SIZE
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100418 - macb->rx_tail);
419 taillen = length - headlen;
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500420 memcpy((void *)net_rx_packets[0],
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100421 buffer, headlen);
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500422 memcpy((void *)net_rx_packets[0] + headlen,
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100423 macb->rx_buffer, taillen);
Simon Glassd5555b72016-05-05 07:28:09 -0600424 *packetp = (void *)net_rx_packets[0];
425 } else {
426 *packetp = buffer;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100427 }
428
Simon Glassd5555b72016-05-05 07:28:09 -0600429 if (++next_rx_tail >= MACB_RX_RING_SIZE)
430 next_rx_tail = 0;
431 macb->next_rx_tail = next_rx_tail;
432 return length;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100433 } else {
Simon Glassd5555b72016-05-05 07:28:09 -0600434 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
435 macb->wrapped = true;
436 next_rx_tail = 0;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100437 }
438 }
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200439 barrier();
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100440 }
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100441}
442
Simon Glassd5555b72016-05-05 07:28:09 -0600443static void macb_phy_reset(struct macb_device *macb, const char *name)
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200444{
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200445 int i;
446 u16 status, adv;
447
448 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
449 macb_mdio_write(macb, MII_ADVERTISE, adv);
Simon Glassd5555b72016-05-05 07:28:09 -0600450 printf("%s: Starting autonegotiation...\n", name);
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200451 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
452 | BMCR_ANRESTART));
453
Andreas Bießmannceef9832014-05-26 22:55:18 +0200454 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200455 status = macb_mdio_read(macb, MII_BMSR);
456 if (status & BMSR_ANEGCOMPLETE)
457 break;
458 udelay(100);
459 }
460
461 if (status & BMSR_ANEGCOMPLETE)
Simon Glassd5555b72016-05-05 07:28:09 -0600462 printf("%s: Autonegotiation complete\n", name);
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200463 else
464 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
Simon Glassd5555b72016-05-05 07:28:09 -0600465 name, status);
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200466}
467
Wenyou Yanga212b662016-05-17 13:11:35 +0800468static int macb_phy_find(struct macb_device *macb, const char *name)
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100469{
470 int i;
471 u16 phy_id;
472
473 /* Search for PHY... */
474 for (i = 0; i < 32; i++) {
475 macb->phy_addr = i;
476 phy_id = macb_mdio_read(macb, MII_PHYSID1);
477 if (phy_id != 0xffff) {
Wenyou Yanga212b662016-05-17 13:11:35 +0800478 printf("%s: PHY present at %d\n", name, i);
Wilson Lee4bf56912017-08-22 20:25:07 -0700479 return 0;
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100480 }
481 }
482
483 /* PHY isn't up to snuff */
Wenyou Yanga212b662016-05-17 13:11:35 +0800484 printf("%s: PHY not found\n", name);
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100485
Wilson Lee4bf56912017-08-22 20:25:07 -0700486 return -ENODEV;
487}
488
489/**
490 * macb_linkspd_cb - Linkspeed change callback function
491 * @regs: Base Register of MACB devices
492 * @speed: Linkspeed
493 * Returns 0 when operation success and negative errno number
494 * when operation failed.
495 */
496int __weak macb_linkspd_cb(void *regs, unsigned int speed)
497{
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100498 return 0;
499}
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100500
Wenyou Yanga212b662016-05-17 13:11:35 +0800501#ifdef CONFIG_DM_ETH
502static int macb_phy_init(struct udevice *dev, const char *name)
503#else
Simon Glassd5555b72016-05-05 07:28:09 -0600504static int macb_phy_init(struct macb_device *macb, const char *name)
Wenyou Yanga212b662016-05-17 13:11:35 +0800505#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100506{
Wenyou Yanga212b662016-05-17 13:11:35 +0800507#ifdef CONFIG_DM_ETH
508 struct macb_device *macb = dev_get_priv(dev);
509#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100510 u32 ncfgr;
511 u16 phy_id, status, adv, lpa;
512 int media, speed, duplex;
Wilson Lee4bf56912017-08-22 20:25:07 -0700513 int ret;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100514 int i;
515
Simon Glassd5555b72016-05-05 07:28:09 -0600516 arch_get_mdio_control(name);
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100517 /* Auto-detect phy_addr */
Wilson Lee4bf56912017-08-22 20:25:07 -0700518 ret = macb_phy_find(macb, name);
519 if (ret)
520 return ret;
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100521
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100522 /* Check if the PHY is up to snuff... */
523 phy_id = macb_mdio_read(macb, MII_PHYSID1);
524 if (phy_id == 0xffff) {
Simon Glassd5555b72016-05-05 07:28:09 -0600525 printf("%s: No PHY present\n", name);
Wilson Lee4bf56912017-08-22 20:25:07 -0700526 return -ENODEV;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100527 }
528
Bo Shenb1a00062013-04-24 15:59:27 +0800529#ifdef CONFIG_PHYLIB
Wenyou Yanga212b662016-05-17 13:11:35 +0800530#ifdef CONFIG_DM_ETH
Wenyou Yang1870d4d2017-04-14 14:36:04 +0800531 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
Wenyou Yanga212b662016-05-17 13:11:35 +0800532 macb->phy_interface);
533#else
Bo Shen8314ccd2013-08-19 10:35:47 +0800534 /* need to consider other phy interface mode */
Wenyou Yang1870d4d2017-04-14 14:36:04 +0800535 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
Bo Shen8314ccd2013-08-19 10:35:47 +0800536 PHY_INTERFACE_MODE_RGMII);
Wenyou Yanga212b662016-05-17 13:11:35 +0800537#endif
Wenyou Yang1870d4d2017-04-14 14:36:04 +0800538 if (!macb->phydev) {
Bo Shen8314ccd2013-08-19 10:35:47 +0800539 printf("phy_connect failed\n");
540 return -ENODEV;
541 }
542
Wenyou Yang1870d4d2017-04-14 14:36:04 +0800543 phy_config(macb->phydev);
Bo Shenb1a00062013-04-24 15:59:27 +0800544#endif
545
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200546 status = macb_mdio_read(macb, MII_BMSR);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100547 if (!(status & BMSR_LSTATUS)) {
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200548 /* Try to re-negotiate if we don't have link already. */
Simon Glassd5555b72016-05-05 07:28:09 -0600549 macb_phy_reset(macb, name);
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200550
Andreas Bießmannceef9832014-05-26 22:55:18 +0200551 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100552 status = macb_mdio_read(macb, MII_BMSR);
553 if (status & BMSR_LSTATUS)
554 break;
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200555 udelay(100);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100556 }
557 }
558
559 if (!(status & BMSR_LSTATUS)) {
560 printf("%s: link down (status: 0x%04x)\n",
Simon Glassd5555b72016-05-05 07:28:09 -0600561 name, status);
Wilson Lee4bf56912017-08-22 20:25:07 -0700562 return -ENETDOWN;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100563 }
Bo Shend256be22013-04-24 15:59:28 +0800564
Gregory CLEMENT75b03cf2015-12-16 14:50:34 +0100565 /* First check for GMAC and that it is GiB capable */
566 if (gem_is_gigabit_capable(macb)) {
Bo Shend256be22013-04-24 15:59:28 +0800567 lpa = macb_mdio_read(macb, MII_STAT1000);
Bo Shend256be22013-04-24 15:59:28 +0800568
Andreas Bießmann47609572014-09-18 23:46:48 +0200569 if (lpa & (LPA_1000FULL | LPA_1000HALF)) {
570 duplex = ((lpa & LPA_1000FULL) ? 1 : 0);
571
572 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
Simon Glassd5555b72016-05-05 07:28:09 -0600573 name,
Bo Shend256be22013-04-24 15:59:28 +0800574 duplex ? "full" : "half",
575 lpa);
576
577 ncfgr = macb_readl(macb, NCFGR);
Andreas Bießmann47609572014-09-18 23:46:48 +0200578 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
579 ncfgr |= GEM_BIT(GBE);
580
Bo Shend256be22013-04-24 15:59:28 +0800581 if (duplex)
582 ncfgr |= MACB_BIT(FD);
Andreas Bießmann47609572014-09-18 23:46:48 +0200583
Bo Shend256be22013-04-24 15:59:28 +0800584 macb_writel(macb, NCFGR, ncfgr);
585
Wilson Lee4bf56912017-08-22 20:25:07 -0700586 ret = macb_linkspd_cb(macb->regs, _1000BASET);
587 if (ret)
588 return ret;
589
590 return 0;
Bo Shend256be22013-04-24 15:59:28 +0800591 }
592 }
593
594 /* fall back for EMAC checking */
595 adv = macb_mdio_read(macb, MII_ADVERTISE);
596 lpa = macb_mdio_read(macb, MII_LPA);
597 media = mii_nway_result(lpa & adv);
598 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
599 ? 1 : 0);
600 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
601 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
Simon Glassd5555b72016-05-05 07:28:09 -0600602 name,
Bo Shend256be22013-04-24 15:59:28 +0800603 speed ? "100" : "10",
604 duplex ? "full" : "half",
605 lpa);
606
607 ncfgr = macb_readl(macb, NCFGR);
Bo Shenc83cb5f2015-03-04 13:35:16 +0800608 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
Wilson Lee4bf56912017-08-22 20:25:07 -0700609 if (speed) {
Bo Shend256be22013-04-24 15:59:28 +0800610 ncfgr |= MACB_BIT(SPD);
Wilson Lee4bf56912017-08-22 20:25:07 -0700611 ret = macb_linkspd_cb(macb->regs, _100BASET);
612 } else {
613 ret = macb_linkspd_cb(macb->regs, _10BASET);
614 }
615
616 if (ret)
617 return ret;
618
Bo Shend256be22013-04-24 15:59:28 +0800619 if (duplex)
620 ncfgr |= MACB_BIT(FD);
621 macb_writel(macb, NCFGR, ncfgr);
622
Wilson Lee4bf56912017-08-22 20:25:07 -0700623 return 0;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100624}
625
Wu, Joshade4ea42015-06-03 16:45:44 +0800626static int gmac_init_multi_queues(struct macb_device *macb)
627{
628 int i, num_queues = 1;
629 u32 queue_mask;
630
631 /* bit 0 is never set but queue 0 always exists */
632 queue_mask = gem_readl(macb, DCFG6) & 0xff;
633 queue_mask |= 0x1;
634
635 for (i = 1; i < MACB_MAX_QUEUES; i++)
636 if (queue_mask & (1 << i))
637 num_queues++;
638
639 macb->dummy_desc->ctrl = TXBUF_USED;
640 macb->dummy_desc->addr = 0;
641 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
Heiko Schocher592a7492016-08-29 07:46:11 +0200642 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
Wu, Joshade4ea42015-06-03 16:45:44 +0800643
644 for (i = 1; i < num_queues; i++)
645 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
646
647 return 0;
648}
649
Wenyou Yanga212b662016-05-17 13:11:35 +0800650#ifdef CONFIG_DM_ETH
651static int _macb_init(struct udevice *dev, const char *name)
652#else
Simon Glassd5555b72016-05-05 07:28:09 -0600653static int _macb_init(struct macb_device *macb, const char *name)
Wenyou Yanga212b662016-05-17 13:11:35 +0800654#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100655{
Wenyou Yanga212b662016-05-17 13:11:35 +0800656#ifdef CONFIG_DM_ETH
657 struct macb_device *macb = dev_get_priv(dev);
658#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100659 unsigned long paddr;
Wilson Lee4bf56912017-08-22 20:25:07 -0700660 int ret;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100661 int i;
662
663 /*
664 * macb_halt should have been called at some point before now,
665 * so we'll assume the controller is idle.
666 */
667
668 /* initialize DMA descriptors */
669 paddr = macb->rx_buffer_dma;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200670 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
671 if (i == (MACB_RX_RING_SIZE - 1))
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100672 paddr |= RXADDR_WRAP;
673 macb->rx_ring[i].addr = paddr;
674 macb->rx_ring[i].ctrl = 0;
675 paddr += 128;
676 }
Wu, Josh5ae0e382014-05-27 16:31:05 +0800677 macb_flush_ring_desc(macb, RX);
678 macb_flush_rx_buffer(macb);
679
Andreas Bießmannceef9832014-05-26 22:55:18 +0200680 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100681 macb->tx_ring[i].addr = 0;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200682 if (i == (MACB_TX_RING_SIZE - 1))
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100683 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
684 else
685 macb->tx_ring[i].ctrl = TXBUF_USED;
686 }
Wu, Josh5ae0e382014-05-27 16:31:05 +0800687 macb_flush_ring_desc(macb, TX);
688
Andreas Bießmannceef9832014-05-26 22:55:18 +0200689 macb->rx_tail = 0;
690 macb->tx_head = 0;
691 macb->tx_tail = 0;
Simon Glassd5555b72016-05-05 07:28:09 -0600692 macb->next_rx_tail = 0;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100693
Wilson Lee4bf56912017-08-22 20:25:07 -0700694#ifdef CONFIG_MACB_ZYNQ
695 macb_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
696#endif
697
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100698 macb_writel(macb, RBQP, macb->rx_ring_dma);
699 macb_writel(macb, TBQP, macb->tx_ring_dma);
700
Bo Shend256be22013-04-24 15:59:28 +0800701 if (macb_is_gem(macb)) {
Wu, Joshade4ea42015-06-03 16:45:44 +0800702 /* Check the multi queue and initialize the queue for tx */
703 gmac_init_multi_queues(macb);
704
Bo Shencabf61c2014-11-10 15:24:01 +0800705 /*
706 * When the GMAC IP with GE feature, this bit is used to
707 * select interface between RGMII and GMII.
708 * When the GMAC IP without GE feature, this bit is used
709 * to select interface between RMII and MII.
710 */
Wenyou Yanga212b662016-05-17 13:11:35 +0800711#ifdef CONFIG_DM_ETH
Wenyou Yang6de046e2017-04-20 11:13:13 +0800712 if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) ||
713 (macb->phy_interface == PHY_INTERFACE_MODE_RGMII))
Wenyou Yanga212b662016-05-17 13:11:35 +0800714 gem_writel(macb, UR, GEM_BIT(RGMII));
715 else
716 gem_writel(macb, UR, 0);
717#else
Bo Shencabf61c2014-11-10 15:24:01 +0800718#if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
Bo Shend256be22013-04-24 15:59:28 +0800719 gem_writel(macb, UR, GEM_BIT(RGMII));
720#else
721 gem_writel(macb, UR, 0);
722#endif
Wenyou Yanga212b662016-05-17 13:11:35 +0800723#endif
Bo Shend256be22013-04-24 15:59:28 +0800724 } else {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100725 /* choose RMII or MII mode. This depends on the board */
Wenyou Yanga212b662016-05-17 13:11:35 +0800726#ifdef CONFIG_DM_ETH
727#ifdef CONFIG_AT91FAMILY
728 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
729 macb_writel(macb, USRIO,
730 MACB_BIT(RMII) | MACB_BIT(CLKEN));
731 } else {
732 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
733 }
734#else
735 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
736 macb_writel(macb, USRIO, 0);
737 else
738 macb_writel(macb, USRIO, MACB_BIT(MII));
739#endif
740#else
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100741#ifdef CONFIG_RMII
Bo Shend8f64b42013-04-24 15:59:26 +0800742#ifdef CONFIG_AT91FAMILY
Stelian Pop7263ef12008-01-03 21:15:56 +0000743 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
744#else
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100745 macb_writel(macb, USRIO, 0);
Stelian Pop7263ef12008-01-03 21:15:56 +0000746#endif
747#else
Bo Shend8f64b42013-04-24 15:59:26 +0800748#ifdef CONFIG_AT91FAMILY
Stelian Pop7263ef12008-01-03 21:15:56 +0000749 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100750#else
751 macb_writel(macb, USRIO, MACB_BIT(MII));
752#endif
Stelian Pop7263ef12008-01-03 21:15:56 +0000753#endif /* CONFIG_RMII */
Wenyou Yanga212b662016-05-17 13:11:35 +0800754#endif
Bo Shend256be22013-04-24 15:59:28 +0800755 }
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100756
Wenyou Yanga212b662016-05-17 13:11:35 +0800757#ifdef CONFIG_DM_ETH
Wilson Lee4bf56912017-08-22 20:25:07 -0700758 ret = macb_phy_init(dev, name);
Wenyou Yanga212b662016-05-17 13:11:35 +0800759#else
Wilson Lee4bf56912017-08-22 20:25:07 -0700760 ret = macb_phy_init(macb, name);
Wenyou Yanga212b662016-05-17 13:11:35 +0800761#endif
Wilson Lee4bf56912017-08-22 20:25:07 -0700762 if (ret)
763 return ret;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100764
765 /* Enable TX and RX */
766 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
767
Ben Warren422b1a02008-01-09 18:15:53 -0500768 return 0;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100769}
770
Simon Glassd5555b72016-05-05 07:28:09 -0600771static void _macb_halt(struct macb_device *macb)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100772{
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100773 u32 ncr, tsr;
774
775 /* Halt the controller and wait for any ongoing transmission to end. */
776 ncr = macb_readl(macb, NCR);
777 ncr |= MACB_BIT(THALT);
778 macb_writel(macb, NCR, ncr);
779
780 do {
781 tsr = macb_readl(macb, TSR);
782 } while (tsr & MACB_BIT(TGO));
783
784 /* Disable TX and RX, and clear statistics */
785 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
786}
787
Simon Glassd5555b72016-05-05 07:28:09 -0600788static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
Ben Warren6bb46792010-06-01 11:55:42 -0700789{
Ben Warren6bb46792010-06-01 11:55:42 -0700790 u32 hwaddr_bottom;
791 u16 hwaddr_top;
792
793 /* set hardware address */
Simon Glassd5555b72016-05-05 07:28:09 -0600794 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
795 enetaddr[2] << 16 | enetaddr[3] << 24;
Ben Warren6bb46792010-06-01 11:55:42 -0700796 macb_writel(macb, SA1B, hwaddr_bottom);
Simon Glassd5555b72016-05-05 07:28:09 -0600797 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
Ben Warren6bb46792010-06-01 11:55:42 -0700798 macb_writel(macb, SA1T, hwaddr_top);
799 return 0;
800}
801
Bo Shend256be22013-04-24 15:59:28 +0800802static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
803{
804 u32 config;
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +0800805#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
Wenyou Yang577aa3b2016-11-02 10:06:56 +0800806 unsigned long macb_hz = macb->pclk_rate;
807#else
Bo Shend256be22013-04-24 15:59:28 +0800808 unsigned long macb_hz = get_macb_pclk_rate(id);
Wenyou Yang577aa3b2016-11-02 10:06:56 +0800809#endif
Bo Shend256be22013-04-24 15:59:28 +0800810
811 if (macb_hz < 20000000)
812 config = MACB_BF(CLK, MACB_CLK_DIV8);
813 else if (macb_hz < 40000000)
814 config = MACB_BF(CLK, MACB_CLK_DIV16);
815 else if (macb_hz < 80000000)
816 config = MACB_BF(CLK, MACB_CLK_DIV32);
817 else
818 config = MACB_BF(CLK, MACB_CLK_DIV64);
819
820 return config;
821}
822
823static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
824{
825 u32 config;
Wenyou Yang577aa3b2016-11-02 10:06:56 +0800826
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +0800827#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
Wenyou Yang577aa3b2016-11-02 10:06:56 +0800828 unsigned long macb_hz = macb->pclk_rate;
829#else
Bo Shend256be22013-04-24 15:59:28 +0800830 unsigned long macb_hz = get_macb_pclk_rate(id);
Wenyou Yang577aa3b2016-11-02 10:06:56 +0800831#endif
Bo Shend256be22013-04-24 15:59:28 +0800832
833 if (macb_hz < 20000000)
834 config = GEM_BF(CLK, GEM_CLK_DIV8);
835 else if (macb_hz < 40000000)
836 config = GEM_BF(CLK, GEM_CLK_DIV16);
837 else if (macb_hz < 80000000)
838 config = GEM_BF(CLK, GEM_CLK_DIV32);
839 else if (macb_hz < 120000000)
840 config = GEM_BF(CLK, GEM_CLK_DIV48);
841 else if (macb_hz < 160000000)
842 config = GEM_BF(CLK, GEM_CLK_DIV64);
843 else
844 config = GEM_BF(CLK, GEM_CLK_DIV96);
845
846 return config;
847}
848
Bo Shen32e4f6b2013-09-18 15:07:44 +0800849/*
850 * Get the DMA bus width field of the network configuration register that we
851 * should program. We find the width from decoding the design configuration
852 * register to find the maximum supported data bus width.
853 */
854static u32 macb_dbw(struct macb_device *macb)
855{
856 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
857 case 4:
858 return GEM_BF(DBW, GEM_DBW128);
859 case 2:
860 return GEM_BF(DBW, GEM_DBW64);
861 case 1:
862 default:
863 return GEM_BF(DBW, GEM_DBW32);
864 }
865}
866
Simon Glassd5555b72016-05-05 07:28:09 -0600867static void _macb_eth_initialize(struct macb_device *macb)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100868{
Simon Glassd5555b72016-05-05 07:28:09 -0600869 int id = 0; /* This is not used by functions we call */
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100870 u32 ncfgr;
871
Simon Glassd5555b72016-05-05 07:28:09 -0600872 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
Andreas Bießmannceef9832014-05-26 22:55:18 +0200873 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100874 &macb->rx_buffer_dma);
Wu, Josh5ae0e382014-05-27 16:31:05 +0800875 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100876 &macb->rx_ring_dma);
Wu, Josh5ae0e382014-05-27 16:31:05 +0800877 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100878 &macb->tx_ring_dma);
Wu, Joshade4ea42015-06-03 16:45:44 +0800879 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
880 &macb->dummy_desc_dma);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100881
Simon Glassd5555b72016-05-05 07:28:09 -0600882 /*
883 * Do some basic initialization so that we at least can talk
884 * to the PHY
885 */
886 if (macb_is_gem(macb)) {
887 ncfgr = gem_mdc_clk_div(id, macb);
888 ncfgr |= macb_dbw(macb);
889 } else {
890 ncfgr = macb_mdc_clk_div(id, macb);
891 }
892
893 macb_writel(macb, NCFGR, ncfgr);
894}
895
Simon Glassf1dcc192016-05-05 07:28:11 -0600896#ifndef CONFIG_DM_ETH
Simon Glassd5555b72016-05-05 07:28:09 -0600897static int macb_send(struct eth_device *netdev, void *packet, int length)
898{
899 struct macb_device *macb = to_macb(netdev);
900
901 return _macb_send(macb, netdev->name, packet, length);
902}
903
904static int macb_recv(struct eth_device *netdev)
905{
906 struct macb_device *macb = to_macb(netdev);
907 uchar *packet;
908 int length;
909
910 macb->wrapped = false;
911 for (;;) {
912 macb->next_rx_tail = macb->rx_tail;
913 length = _macb_recv(macb, &packet);
914 if (length >= 0) {
915 net_process_received_packet(packet, length);
916 reclaim_rx_buffers(macb, macb->next_rx_tail);
Heinrich Schuchardt6cdf0722018-03-18 11:32:53 +0100917 } else {
Simon Glassd5555b72016-05-05 07:28:09 -0600918 return length;
919 }
920 }
921}
922
923static int macb_init(struct eth_device *netdev, bd_t *bd)
924{
925 struct macb_device *macb = to_macb(netdev);
926
927 return _macb_init(macb, netdev->name);
928}
929
930static void macb_halt(struct eth_device *netdev)
931{
932 struct macb_device *macb = to_macb(netdev);
933
934 return _macb_halt(macb);
935}
936
937static int macb_write_hwaddr(struct eth_device *netdev)
938{
939 struct macb_device *macb = to_macb(netdev);
940
941 return _macb_write_hwaddr(macb, netdev->enetaddr);
942}
943
944int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
945{
946 struct macb_device *macb;
947 struct eth_device *netdev;
948
949 macb = malloc(sizeof(struct macb_device));
950 if (!macb) {
951 printf("Error: Failed to allocate memory for MACB%d\n", id);
952 return -1;
953 }
954 memset(macb, 0, sizeof(struct macb_device));
955
956 netdev = &macb->netdev;
Wu, Josh5ae0e382014-05-27 16:31:05 +0800957
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100958 macb->regs = regs;
959 macb->phy_addr = phy_addr;
960
Bo Shend256be22013-04-24 15:59:28 +0800961 if (macb_is_gem(macb))
962 sprintf(netdev->name, "gmac%d", id);
963 else
964 sprintf(netdev->name, "macb%d", id);
965
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100966 netdev->init = macb_init;
967 netdev->halt = macb_halt;
968 netdev->send = macb_send;
969 netdev->recv = macb_recv;
Ben Warren6bb46792010-06-01 11:55:42 -0700970 netdev->write_hwaddr = macb_write_hwaddr;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100971
Simon Glassd5555b72016-05-05 07:28:09 -0600972 _macb_eth_initialize(macb);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100973
974 eth_register(netdev);
975
Bo Shenb1a00062013-04-24 15:59:27 +0800976#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
Joe Hershberger5a49f172016-08-08 11:28:38 -0500977 int retval;
978 struct mii_dev *mdiodev = mdio_alloc();
979 if (!mdiodev)
980 return -ENOMEM;
981 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
982 mdiodev->read = macb_miiphy_read;
983 mdiodev->write = macb_miiphy_write;
984
985 retval = mdio_register(mdiodev);
986 if (retval < 0)
987 return retval;
Bo Shenb1a00062013-04-24 15:59:27 +0800988 macb->bus = miiphy_get_dev_by_name(netdev->name);
Semih Hazar0f751d62009-12-17 15:07:15 +0200989#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100990 return 0;
991}
Simon Glassf1dcc192016-05-05 07:28:11 -0600992#endif /* !CONFIG_DM_ETH */
993
994#ifdef CONFIG_DM_ETH
995
996static int macb_start(struct udevice *dev)
997{
Wenyou Yanga212b662016-05-17 13:11:35 +0800998 return _macb_init(dev, dev->name);
Simon Glassf1dcc192016-05-05 07:28:11 -0600999}
1000
1001static int macb_send(struct udevice *dev, void *packet, int length)
1002{
1003 struct macb_device *macb = dev_get_priv(dev);
1004
1005 return _macb_send(macb, dev->name, packet, length);
1006}
1007
1008static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
1009{
1010 struct macb_device *macb = dev_get_priv(dev);
1011
1012 macb->next_rx_tail = macb->rx_tail;
1013 macb->wrapped = false;
1014
1015 return _macb_recv(macb, packetp);
1016}
1017
1018static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
1019{
1020 struct macb_device *macb = dev_get_priv(dev);
1021
1022 reclaim_rx_buffers(macb, macb->next_rx_tail);
1023
1024 return 0;
1025}
1026
1027static void macb_stop(struct udevice *dev)
1028{
1029 struct macb_device *macb = dev_get_priv(dev);
1030
1031 _macb_halt(macb);
1032}
1033
1034static int macb_write_hwaddr(struct udevice *dev)
1035{
1036 struct eth_pdata *plat = dev_get_platdata(dev);
1037 struct macb_device *macb = dev_get_priv(dev);
1038
1039 return _macb_write_hwaddr(macb, plat->enetaddr);
1040}
1041
1042static const struct eth_ops macb_eth_ops = {
1043 .start = macb_start,
1044 .send = macb_send,
1045 .recv = macb_recv,
1046 .stop = macb_stop,
1047 .free_pkt = macb_free_pkt,
1048 .write_hwaddr = macb_write_hwaddr,
1049};
1050
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +08001051#ifdef CONFIG_CLK
Wenyou Yang577aa3b2016-11-02 10:06:56 +08001052static int macb_enable_clk(struct udevice *dev)
1053{
1054 struct macb_device *macb = dev_get_priv(dev);
1055 struct clk clk;
1056 ulong clk_rate;
1057 int ret;
1058
1059 ret = clk_get_by_index(dev, 0, &clk);
1060 if (ret)
1061 return -EINVAL;
1062
Wilson Lee4bf56912017-08-22 20:25:07 -07001063 /*
1064 * Zynq clock driver didn't support for enable or disable
1065 * clock. Hence, clk_enable() didn't apply for Zynq
1066 */
1067#ifndef CONFIG_MACB_ZYNQ
Wenyou Yang577aa3b2016-11-02 10:06:56 +08001068 ret = clk_enable(&clk);
1069 if (ret)
1070 return ret;
Wilson Lee4bf56912017-08-22 20:25:07 -07001071#endif
Wenyou Yang577aa3b2016-11-02 10:06:56 +08001072
1073 clk_rate = clk_get_rate(&clk);
1074 if (!clk_rate)
1075 return -EINVAL;
1076
1077 macb->pclk_rate = clk_rate;
1078
1079 return 0;
1080}
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +08001081#endif
Wenyou Yang577aa3b2016-11-02 10:06:56 +08001082
Simon Glassf1dcc192016-05-05 07:28:11 -06001083static int macb_eth_probe(struct udevice *dev)
1084{
1085 struct eth_pdata *pdata = dev_get_platdata(dev);
1086 struct macb_device *macb = dev_get_priv(dev);
Wenyou Yanga212b662016-05-17 13:11:35 +08001087 const char *phy_mode;
Wenyou Yang1870d4d2017-04-14 14:36:04 +08001088 __maybe_unused int ret;
Wenyou Yanga212b662016-05-17 13:11:35 +08001089
Simon Glasse160f7d2017-01-17 16:52:55 -07001090 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1091 NULL);
Wenyou Yanga212b662016-05-17 13:11:35 +08001092 if (phy_mode)
1093 macb->phy_interface = phy_get_interface_by_name(phy_mode);
1094 if (macb->phy_interface == -1) {
1095 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1096 return -EINVAL;
1097 }
Wenyou Yanga212b662016-05-17 13:11:35 +08001098
Simon Glassf1dcc192016-05-05 07:28:11 -06001099 macb->regs = (void *)pdata->iobase;
1100
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +08001101#ifdef CONFIG_CLK
Wenyou Yang1870d4d2017-04-14 14:36:04 +08001102 ret = macb_enable_clk(dev);
Wenyou Yang577aa3b2016-11-02 10:06:56 +08001103 if (ret)
1104 return ret;
Wenyou Yang3fd2b3a2017-02-14 16:24:40 +08001105#endif
Wenyou Yang577aa3b2016-11-02 10:06:56 +08001106
Simon Glassf1dcc192016-05-05 07:28:11 -06001107 _macb_eth_initialize(macb);
Wenyou Yang577aa3b2016-11-02 10:06:56 +08001108
Simon Glassf1dcc192016-05-05 07:28:11 -06001109#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
Wenyou Yang1870d4d2017-04-14 14:36:04 +08001110 macb->bus = mdio_alloc();
1111 if (!macb->bus)
Joe Hershberger5a49f172016-08-08 11:28:38 -05001112 return -ENOMEM;
Wenyou Yang1870d4d2017-04-14 14:36:04 +08001113 strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
1114 macb->bus->read = macb_miiphy_read;
1115 macb->bus->write = macb_miiphy_write;
Joe Hershberger5a49f172016-08-08 11:28:38 -05001116
Wenyou Yang1870d4d2017-04-14 14:36:04 +08001117 ret = mdio_register(macb->bus);
1118 if (ret < 0)
1119 return ret;
Simon Glassf1dcc192016-05-05 07:28:11 -06001120 macb->bus = miiphy_get_dev_by_name(dev->name);
1121#endif
1122
1123 return 0;
1124}
1125
Wenyou Yang1870d4d2017-04-14 14:36:04 +08001126static int macb_eth_remove(struct udevice *dev)
1127{
1128 struct macb_device *macb = dev_get_priv(dev);
1129
1130#ifdef CONFIG_PHYLIB
1131 free(macb->phydev);
1132#endif
1133 mdio_unregister(macb->bus);
1134 mdio_free(macb->bus);
1135
1136 return 0;
1137}
1138
Wilson Lee4bf56912017-08-22 20:25:07 -07001139/**
1140 * macb_late_eth_ofdata_to_platdata
1141 * @dev: udevice struct
1142 * Returns 0 when operation success and negative errno number
1143 * when operation failed.
1144 */
1145int __weak macb_late_eth_ofdata_to_platdata(struct udevice *dev)
1146{
1147 return 0;
1148}
1149
Simon Glassf1dcc192016-05-05 07:28:11 -06001150static int macb_eth_ofdata_to_platdata(struct udevice *dev)
1151{
1152 struct eth_pdata *pdata = dev_get_platdata(dev);
1153
Simon Glassa821c4a2017-05-17 17:18:05 -06001154 pdata->iobase = devfdt_get_addr(dev);
Wilson Lee4bf56912017-08-22 20:25:07 -07001155
1156 return macb_late_eth_ofdata_to_platdata(dev);
Simon Glassf1dcc192016-05-05 07:28:11 -06001157}
1158
1159static const struct udevice_id macb_eth_ids[] = {
1160 { .compatible = "cdns,macb" },
Wenyou Yang75460252017-04-14 14:36:05 +08001161 { .compatible = "cdns,at91sam9260-macb" },
1162 { .compatible = "atmel,sama5d2-gem" },
1163 { .compatible = "atmel,sama5d3-gem" },
1164 { .compatible = "atmel,sama5d4-gem" },
Wilson Lee4bf56912017-08-22 20:25:07 -07001165 { .compatible = "cdns,zynq-gem" },
Simon Glassf1dcc192016-05-05 07:28:11 -06001166 { }
1167};
1168
1169U_BOOT_DRIVER(eth_macb) = {
1170 .name = "eth_macb",
1171 .id = UCLASS_ETH,
1172 .of_match = macb_eth_ids,
1173 .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
1174 .probe = macb_eth_probe,
Wenyou Yang1870d4d2017-04-14 14:36:04 +08001175 .remove = macb_eth_remove,
Simon Glassf1dcc192016-05-05 07:28:11 -06001176 .ops = &macb_eth_ops,
1177 .priv_auto_alloc_size = sizeof(struct macb_device),
1178 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1179};
1180#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01001181
Jon Loeliger07d38a12007-07-09 17:30:01 -05001182#endif