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wdenk5d3207d2002-08-21 22:08:56 +00001/*
Michal Simekd5dae852013-04-22 15:43:02 +02002 * (C) Copyright 2012-2013, Xilinx, Michal Simek
3 *
wdenk5d3207d2002-08-21 22:08:56 +00004 * (C) Copyright 2002
5 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
6 * Keith Outwater, keith_outwater@mvis.com
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenk5d3207d2002-08-21 22:08:56 +00009 */
10
11/*
12 * Xilinx FPGA support
13 */
14
15#include <common.h>
Michal Simek6631db42013-04-26 15:04:48 +020016#include <fpga.h>
wdenk5d3207d2002-08-21 22:08:56 +000017#include <virtex2.h>
18#include <spartan2.h>
Wolfgang Denk875c7892005-09-25 16:44:21 +020019#include <spartan3.h>
Michal Simekd5dae852013-04-22 15:43:02 +020020#include <zynqpl.h>
wdenk5d3207d2002-08-21 22:08:56 +000021
wdenk5d3207d2002-08-21 22:08:56 +000022/* Local Static Functions */
Michal Simekf8c1be92014-03-13 12:49:21 +010023static int xilinx_validate(xilinx_desc *desc, char *fn);
wdenk5d3207d2002-08-21 22:08:56 +000024
25/* ------------------------------------------------------------------------- */
26
Michal Simek7a78bd22014-05-02 14:09:30 +020027int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
28 bitstream_type bstype)
Michal Simek52c20642013-04-26 13:12:07 +020029{
30 unsigned int length;
31 unsigned int swapsize;
32 char buffer[80];
33 unsigned char *dataptr;
34 unsigned int i;
Michal Simek6631db42013-04-26 15:04:48 +020035 const fpga_desc *desc;
Michal Simekf8c1be92014-03-13 12:49:21 +010036 xilinx_desc *xdesc;
Michal Simek52c20642013-04-26 13:12:07 +020037
38 dataptr = (unsigned char *)fpgadata;
Michal Simek6631db42013-04-26 15:04:48 +020039 /* Find out fpga_description */
40 desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
41 /* Assign xilinx device description */
42 xdesc = desc->devdesc;
Michal Simek52c20642013-04-26 13:12:07 +020043
44 /* skip the first bytes of the bitsteam, their meaning is unknown */
45 length = (*dataptr << 8) + *(dataptr + 1);
46 dataptr += 2;
47 dataptr += length;
48
49 /* get design name (identifier, length, string) */
50 length = (*dataptr << 8) + *(dataptr + 1);
51 dataptr += 2;
52 if (*dataptr++ != 0x61) {
53 debug("%s: Design name id not recognized in bitstream\n",
54 __func__);
55 return FPGA_FAIL;
56 }
57
58 length = (*dataptr << 8) + *(dataptr + 1);
59 dataptr += 2;
60 for (i = 0; i < length; i++)
61 buffer[i] = *dataptr++;
62
63 printf(" design filename = \"%s\"\n", buffer);
64
65 /* get part number (identifier, length, string) */
66 if (*dataptr++ != 0x62) {
67 printf("%s: Part number id not recognized in bitstream\n",
68 __func__);
69 return FPGA_FAIL;
70 }
71
72 length = (*dataptr << 8) + *(dataptr + 1);
73 dataptr += 2;
74 for (i = 0; i < length; i++)
75 buffer[i] = *dataptr++;
Michal Simek6631db42013-04-26 15:04:48 +020076
77 if (xdesc->name) {
Siva Durga Prasad Paladuguf7213262016-01-11 12:30:41 +053078 i = (ulong)strstr(buffer, xdesc->name);
79 if (!i) {
Michal Simek6631db42013-04-26 15:04:48 +020080 printf("%s: Wrong bitstream ID for this device\n",
81 __func__);
82 printf("%s: Bitstream ID %s, current device ID %d/%s\n",
83 __func__, buffer, devnum, xdesc->name);
84 return FPGA_FAIL;
85 }
86 } else {
Michal Simekf8c1be92014-03-13 12:49:21 +010087 printf("%s: Please fill correct device ID to xilinx_desc\n",
Michal Simek6631db42013-04-26 15:04:48 +020088 __func__);
89 }
Michal Simek52c20642013-04-26 13:12:07 +020090 printf(" part number = \"%s\"\n", buffer);
91
92 /* get date (identifier, length, string) */
93 if (*dataptr++ != 0x63) {
94 printf("%s: Date identifier not recognized in bitstream\n",
95 __func__);
96 return FPGA_FAIL;
97 }
98
99 length = (*dataptr << 8) + *(dataptr+1);
100 dataptr += 2;
101 for (i = 0; i < length; i++)
102 buffer[i] = *dataptr++;
103 printf(" date = \"%s\"\n", buffer);
104
105 /* get time (identifier, length, string) */
106 if (*dataptr++ != 0x64) {
107 printf("%s: Time identifier not recognized in bitstream\n",
108 __func__);
109 return FPGA_FAIL;
110 }
111
112 length = (*dataptr << 8) + *(dataptr+1);
113 dataptr += 2;
114 for (i = 0; i < length; i++)
115 buffer[i] = *dataptr++;
116 printf(" time = \"%s\"\n", buffer);
117
118 /* get fpga data length (identifier, length) */
119 if (*dataptr++ != 0x65) {
120 printf("%s: Data length id not recognized in bitstream\n",
121 __func__);
122 return FPGA_FAIL;
123 }
124 swapsize = ((unsigned int) *dataptr << 24) +
125 ((unsigned int) *(dataptr + 1) << 16) +
126 ((unsigned int) *(dataptr + 2) << 8) +
127 ((unsigned int) *(dataptr + 3));
128 dataptr += 4;
129 printf(" bytes in bitstream = %d\n", swapsize);
130
Michal Simek7a78bd22014-05-02 14:09:30 +0200131 return fpga_load(devnum, dataptr, swapsize, bstype);
Michal Simek52c20642013-04-26 13:12:07 +0200132}
133
Michal Simek7a78bd22014-05-02 14:09:30 +0200134int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
135 bitstream_type bstype)
wdenk5d3207d2002-08-21 22:08:56 +0000136{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200137 if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
wdenk5d3207d2002-08-21 22:08:56 +0000138 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
Michal Simek14cfc4f2014-03-13 13:07:57 +0100139 return FPGA_FAIL;
140 }
wdenk5d3207d2002-08-21 22:08:56 +0000141
Michal Simek6cd68c82014-07-16 10:31:21 +0200142 if (!desc->operations || !desc->operations->load) {
143 printf("%s: Missing load operation\n", __func__);
144 return FPGA_FAIL;
145 }
146
Michal Simek7a78bd22014-05-02 14:09:30 +0200147 return desc->operations->load(desc, buf, bsize, bstype);
wdenk5d3207d2002-08-21 22:08:56 +0000148}
149
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530150#if defined(CONFIG_CMD_FPGA_LOADFS)
151int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
152 fpga_fs_info *fpga_fsinfo)
153{
154 if (!xilinx_validate(desc, (char *)__func__)) {
155 printf("%s: Invalid device descriptor\n", __func__);
156 return FPGA_FAIL;
157 }
158
Michal Simek6cd68c82014-07-16 10:31:21 +0200159 if (!desc->operations || !desc->operations->loadfs) {
160 printf("%s: Missing loadfs operation\n", __func__);
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530161 return FPGA_FAIL;
Michal Simek6cd68c82014-07-16 10:31:21 +0200162 }
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530163
164 return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
165}
166#endif
167
Michal Simekf8c1be92014-03-13 12:49:21 +0100168int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
wdenk5d3207d2002-08-21 22:08:56 +0000169{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200170 if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
wdenk5d3207d2002-08-21 22:08:56 +0000171 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
Michal Simek14cfc4f2014-03-13 13:07:57 +0100172 return FPGA_FAIL;
173 }
wdenk5d3207d2002-08-21 22:08:56 +0000174
Michal Simek6cd68c82014-07-16 10:31:21 +0200175 if (!desc->operations || !desc->operations->dump) {
176 printf("%s: Missing dump operation\n", __func__);
177 return FPGA_FAIL;
178 }
179
Michal Simek14cfc4f2014-03-13 13:07:57 +0100180 return desc->operations->dump(desc, buf, bsize);
wdenk5d3207d2002-08-21 22:08:56 +0000181}
182
Michal Simekf8c1be92014-03-13 12:49:21 +0100183int xilinx_info(xilinx_desc *desc)
wdenk5d3207d2002-08-21 22:08:56 +0000184{
185 int ret_val = FPGA_FAIL;
186
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200187 if (xilinx_validate (desc, (char *)__FUNCTION__)) {
wdenk5d3207d2002-08-21 22:08:56 +0000188 printf ("Family: \t");
189 switch (desc->family) {
Michal Simekb625b9a2014-03-13 11:23:43 +0100190 case xilinx_spartan2:
wdenk5d3207d2002-08-21 22:08:56 +0000191 printf ("Spartan-II\n");
192 break;
Michal Simek2a6e3862014-03-13 11:28:42 +0100193 case xilinx_spartan3:
Wolfgang Denk875c7892005-09-25 16:44:21 +0200194 printf ("Spartan-III\n");
195 break;
Michal Simekd9071ce2014-03-13 11:33:36 +0100196 case xilinx_virtex2:
wdenk5d3207d2002-08-21 22:08:56 +0000197 printf ("Virtex-II\n");
198 break;
Michal Simekd5dae852013-04-22 15:43:02 +0200199 case xilinx_zynq:
200 printf("Zynq PL\n");
201 break;
wdenk5d3207d2002-08-21 22:08:56 +0000202 /* Add new family types here */
203 default:
204 printf ("Unknown family type, %d\n", desc->family);
205 }
206
207 printf ("Interface type:\t");
208 switch (desc->iface) {
209 case slave_serial:
210 printf ("Slave Serial\n");
211 break;
212 case master_serial: /* Not used */
213 printf ("Master Serial\n");
214 break;
215 case slave_parallel:
216 printf ("Slave Parallel\n");
217 break;
218 case jtag_mode: /* Not used */
219 printf ("JTAG Mode\n");
220 break;
221 case slave_selectmap:
222 printf ("Slave SelectMap Mode\n");
223 break;
224 case master_selectmap:
225 printf ("Master SelectMap Mode\n");
226 break;
Michal Simekd5dae852013-04-22 15:43:02 +0200227 case devcfg:
228 printf("Device configuration interface (Zynq)\n");
229 break;
wdenk5d3207d2002-08-21 22:08:56 +0000230 /* Add new interface types here */
231 default:
232 printf ("Unsupported interface type, %d\n", desc->iface);
233 }
234
Simon Glassddc94372014-06-07 22:07:58 -0600235 printf("Device Size: \t%zd bytes\n"
236 "Cookie: \t0x%x (%d)\n",
237 desc->size, desc->cookie, desc->cookie);
Michal Simek6631db42013-04-26 15:04:48 +0200238 if (desc->name)
239 printf("Device name: \t%s\n", desc->name);
wdenk5d3207d2002-08-21 22:08:56 +0000240
Michal Simeke136eae2014-07-16 10:36:42 +0200241 if (desc->iface_fns)
wdenk5d3207d2002-08-21 22:08:56 +0000242 printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
Michal Simeke136eae2014-07-16 10:36:42 +0200243 else
wdenk5d3207d2002-08-21 22:08:56 +0000244 printf ("No Device Function Table.\n");
245
Michal Simeke136eae2014-07-16 10:36:42 +0200246 if (desc->operations && desc->operations->info)
247 desc->operations->info(desc);
248
wdenk5d3207d2002-08-21 22:08:56 +0000249 ret_val = FPGA_SUCCESS;
250 } else {
251 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
252 }
253
254 return ret_val;
255}
256
wdenk5d3207d2002-08-21 22:08:56 +0000257/* ------------------------------------------------------------------------- */
258
Michal Simekf8c1be92014-03-13 12:49:21 +0100259static int xilinx_validate(xilinx_desc *desc, char *fn)
wdenk5d3207d2002-08-21 22:08:56 +0000260{
York Sun472d5462013-04-01 11:29:11 -0700261 int ret_val = false;
wdenk5d3207d2002-08-21 22:08:56 +0000262
263 if (desc) {
264 if ((desc->family > min_xilinx_type) &&
265 (desc->family < max_xilinx_type)) {
266 if ((desc->iface > min_xilinx_iface_type) &&
267 (desc->iface < max_xilinx_iface_type)) {
268 if (desc->size) {
York Sun472d5462013-04-01 11:29:11 -0700269 ret_val = true;
wdenk5d3207d2002-08-21 22:08:56 +0000270 } else
271 printf ("%s: NULL part size\n", fn);
272 } else
273 printf ("%s: Invalid Interface type, %d\n",
274 fn, desc->iface);
275 } else
276 printf ("%s: Invalid family type, %d\n", fn, desc->family);
277 } else
278 printf ("%s: NULL descriptor!\n", fn);
279
280 return ret_val;
281}