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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / aacf9a49aa1a74d46726fbaee2b8e87e1dad6956 / . / include / configs / SCM.h
blob: 0dd46a0f83dd05444bbc2370114fb15b3a873502 [file] [log] [blame]
wdenk0f8c9762002-08-19 11:57:05 +0000[diff] [blame]1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
37#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */
38#define CONFIG_SCM 1 /* ...on a System Controller Module */
39
40#if (CONFIG_TQM8260 <= 100)
41# error "TQM8260 module revison not supported"
42#endif
43
44/* We use a TQM8260 module with a 300MHz CPU */
45#define CONFIG_300MHz
46
47/* Define 60x busmode only if your TQM8260 has L2 cache! */
48#ifdef CONFIG_L2_CACHE
49# define CONFIG_BUSMODE_60x 1 /* bus mode: 60x */
50#else
51# undef CONFIG_BUSMODE_60x /* bus mode: 8260 */
52#endif
53
54/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */
55#ifdef CONFIG_300MHz
56# define CONFIG_BUSMODE_60x
57#endif
58
59#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
60
61#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
62
63#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
64
65#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
66
67#undef CONFIG_BOOTARGS
68#define CONFIG_BOOTCOMMAND \
69 "bootp; " \
70 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
71 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
72 "bootm"
73
74/* enable I2C and select the hardware/software driver */
75#undef CONFIG_HARD_I2C /* I2C with hardware support */
76#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
77#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
78#define CFG_I2C_SLAVE 0x7F
79
80/*
81 * Software (bit-bang) I2C driver configuration
82 */
83
84#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
85#define I2C_ACTIVE (iop->pdir |= 0x00010000)
86#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
87#define I2C_READ ((iop->pdat & 0x00010000) != 0)
88#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
89 else iop->pdat &= ~0x00010000
90#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
91 else iop->pdat &= ~0x00020000
92#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
93
94#define CFG_I2C_EEPROM_ADDR 0x50
95#define CFG_I2C_EEPROM_ADDR_LEN 2
96#define CFG_EEPROM_PAGE_WRITE_BITS 4
97#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
98
99#define CONFIG_I2C_X
100
101/*
102 * select serial console configuration
103 *
104 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
105 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
106 * for SCC).
107 *
108 * if CONFIG_CONS_NONE is defined, then the serial console routines must
109 * defined elsewhere (for example, on the cogent platform, there are serial
110 * ports on the motherboard which are used for the serial console - see
111 * cogent/cma101/serial.[ch]).
112 */
113#define CONFIG_CONS_ON_SMC /* define if console on SMC */
114#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
115#undef CONFIG_CONS_NONE /* define if console on something else*/
116#ifdef CONFIG_82xx_CONS_SMC1
117#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
118#endif
119#ifdef CONFIG_82xx_CONS_SMC2
120#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
121#endif
122
123#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
124#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
125#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
126
127/*
128 * select ethernet configuration
129 *
130 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
131 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
132 * for FCC)
133 *
134 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
135 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
136 * from CONFIG_COMMANDS to remove support for networking.
137 *
138 * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
139 * X.29 connector, and FCC2 is hardwired to the X.1 connector)
140 */
141#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
142#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
143#undef CONFIG_ETHER_NONE /* define if ether on something else */
144#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
145
146#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
147
148/*
149 * - Rx-CLK is CLK12
150 * - Tx-CLK is CLK11
151 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
152 * - Enable Full Duplex in FSMR
153 */
154# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
155# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11)
156# define CFG_CPMFCR_RAMTYPE 0
157# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
158
159#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
160
161/*
162 * - Rx-CLK is CLK15
163 * - Tx-CLK is CLK16
164 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
165 * - Enable Full Duplex in FSMR
166 */
167# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
168# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
169# define CFG_CPMFCR_RAMTYPE 0
170# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
171
172#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
173
174
175/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
176#ifndef CONFIG_300MHz
177#define CONFIG_8260_CLKIN 66666666 /* in Hz */
178#else
179#define CONFIG_8260_CLKIN 83333000 /* in Hz */
180#endif
181
182#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
183#define CONFIG_BAUDRATE 230400
184#else
185#define CONFIG_BAUDRATE 115200
186#endif
187
188#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
189#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
190
191#undef CONFIG_WATCHDOG /* watchdog disabled */
192
193#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
194
195#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
196 CFG_CMD_DHCP | \
197 CFG_CMD_I2C | \
198 CFG_CMD_EEPROM | \
199 CFG_CMD_BSP)
200
201/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
202#include <cmd_confdefs.h>
203
204/*
205 * Miscellaneous configurable options
206 */
207#define CFG_LONGHELP /* undef to save memory */
208#define CFG_PROMPT "=> " /* Monitor Command Prompt */
209#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
210#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
211#else
212#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
213#endif
214#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
215#define CFG_MAXARGS 16 /* max number of command args */
216#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
217
218#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
219#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
220
221#define CFG_LOAD_ADDR 0x100000 /* default load address */
222
223#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
224
225#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
226
227#define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */
228
229#define CONFIG_MISC_INIT_R /* have misc_init_r() function */
230
231/*
232 * For booting Linux, the board info and command line data
233 * have to be in the first 8 MB of memory, since this is
234 * the maximum mapped by the Linux kernel during initialization.
235 */
236#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
237
238
239/* What should the base address of the main FLASH be and how big is
240 * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
241 * The main FLASH is whichever is connected to *CS0.
242 */
243#define CFG_FLASH0_BASE 0x40000000
244#define CFG_FLASH1_BASE 0x60000000
245#define CFG_FLASH0_SIZE 32
246#define CFG_FLASH1_SIZE 32
247
248/* Flash bank size (for preliminary settings)
249 */
250#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
251
252/*-----------------------------------------------------------------------
253 * FLASH organization
254 */
255#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
256#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
257
258#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
259#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
260
261#if 0
262/* Start port with environment in flash; switch to EEPROM later */
263#define CFG_ENV_IS_IN_FLASH 1
264#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
265#define CFG_ENV_SIZE 0x40000
266#define CFG_ENV_SECT_SIZE 0x40000
267#else
268/* Final version: environment in EEPROM */
269#define CFG_ENV_IS_IN_EEPROM 1
270#define CFG_ENV_OFFSET 0
271#define CFG_ENV_SIZE 2048
272#endif
273
274/*-----------------------------------------------------------------------
275 * Hardware Information Block
276 */
277#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
278#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
279#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
280
281/*-----------------------------------------------------------------------
282 * Hard Reset Configuration Words
283 *
284 * if you change bits in the HRCW, you must also change the CFG_*
285 * defines for the various registers affected by the HRCW e.g. changing
286 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
287 */
288#if defined(CONFIG_266MHz)
289#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
290 HRCW_MODCK_H0111)
291#elif defined(CONFIG_300MHz)
292#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
293 HRCW_MODCK_H0110)
294#else
295#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
296#endif
297
298/* no slaves so just fill with zeros */
299#define CFG_HRCW_SLAVE1 0
300#define CFG_HRCW_SLAVE2 0
301#define CFG_HRCW_SLAVE3 0
302#define CFG_HRCW_SLAVE4 0
303#define CFG_HRCW_SLAVE5 0
304#define CFG_HRCW_SLAVE6 0
305#define CFG_HRCW_SLAVE7 0
306
307/*-----------------------------------------------------------------------
308 * Internal Memory Mapped Register
309 */
310#define CFG_IMMR 0xFFF00000
311
312/*-----------------------------------------------------------------------
313 * Definitions for initial stack pointer and data area (in DPRAM)
314 */
315#define CFG_INIT_RAM_ADDR CFG_IMMR
316#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
317#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
318#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
319#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
320
321/*-----------------------------------------------------------------------
322 * Start addresses for the final memory configuration
323 * (Set up by the startup code)
324 * Please note that CFG_SDRAM_BASE _must_ start at 0
325 *
326 * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
327 * is mapped at SDRAM_BASE2_PRELIM.
328 */
329#define CFG_SDRAM_BASE 0x00000000
330#define CFG_FLASH_BASE CFG_FLASH0_BASE
331#define CFG_MONITOR_BASE TEXT_BASE
332#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
333#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
334
335/*
336 * Internal Definitions
337 *
338 * Boot Flags
339 */
340#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
341#define BOOTFLAG_WARM 0x02 /* Software reboot */
342
343
344/*-----------------------------------------------------------------------
345 * Hardware Information Block
346 */
347#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
348#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
349#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
350
351/*-----------------------------------------------------------------------
352 * Cache Configuration
353 */
354#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
355#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
356# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
357#endif
358
359/*-----------------------------------------------------------------------
360 * HIDx - Hardware Implementation-dependent Registers 2-11
361 *-----------------------------------------------------------------------
362 * HID0 also contains cache control - initially enable both caches and
363 * invalidate contents, then the final state leaves only the instruction
364 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
365 * but Soft reset does not.
366 *
367 * HID1 has only read-only information - nothing to set.
368 */
369#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
370 HID0_IFEM|HID0_ABE)
371#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
372#define CFG_HID2 0
373
374/*-----------------------------------------------------------------------
375 * RMR - Reset Mode Register 5-5
376 *-----------------------------------------------------------------------
377 * turn on Checkstop Reset Enable
378 */
379#define CFG_RMR RMR_CSRE
380
381/*-----------------------------------------------------------------------
382 * BCR - Bus Configuration 4-25
383 *-----------------------------------------------------------------------
384 */
385#ifdef CONFIG_BUSMODE_60x
386#define CFG_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\
387 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */
388#else
389#define BCR_APD01 0x10000000
390#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
391#endif
392
393/*-----------------------------------------------------------------------
394 * SIUMCR - SIU Module Configuration 4-31
395 *-----------------------------------------------------------------------
396 */
397#if 0
398#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
399#else
400#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10)
401#endif
402
403
404/*-----------------------------------------------------------------------
405 * SYPCR - System Protection Control 4-35
406 * SYPCR can only be written once after reset!
407 *-----------------------------------------------------------------------
408 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
409 */
410#if defined(CONFIG_WATCHDOG)
411#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
412 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
413#else
414#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
415 SYPCR_SWRI|SYPCR_SWP)
416#endif /* CONFIG_WATCHDOG */
417
418/*-----------------------------------------------------------------------
419 * TMCNTSC - Time Counter Status and Control 4-40
420 *-----------------------------------------------------------------------
421 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
422 * and enable Time Counter
423 */
424#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
425
426/*-----------------------------------------------------------------------
427 * PISCR - Periodic Interrupt Status and Control 4-42
428 *-----------------------------------------------------------------------
429 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
430 * Periodic timer
431 */
432#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
433
434/*-----------------------------------------------------------------------
435 * SCCR - System Clock Control 9-8
436 *-----------------------------------------------------------------------
437 * Ensure DFBRG is Divide by 16
438 */
439#define CFG_SCCR 0
440
441/*-----------------------------------------------------------------------
442 * RCCR - RISC Controller Configuration 13-7
443 *-----------------------------------------------------------------------
444 */
445#define CFG_RCCR 0
446
447/*
448 * Init Memory Controller:
449 *
450 * Bank Bus Machine PortSz Device
451 * ---- --- ------- ------ ------
452 * 0 60x GPCM 64 bit FLASH
453 * 1 60x SDRAM 64 bit SDRAM
454 * 2 Local SDRAM 32 bit SDRAM
455 *
456 */
457
458 /* Initialize SDRAM on local bus
459 */
460#define CFG_INIT_LOCAL_SDRAM
461
462#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
463
464/* Minimum mask to separate preliminary
465 * address ranges for CS[0:2]
466 */
467#define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
468#define CFG_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */
469
470#define CFG_MPTPR 0x4000
471
472/*-----------------------------------------------------------------------------
473 * Address for Mode Register Set (MRS) command
474 *-----------------------------------------------------------------------------
475 * In fact, the address is rather configuration data presented to the SDRAM on
476 * its address lines. Because the address lines may be mux'ed externally either
477 * for 8 column or 9 column devices, some bits appear twice in the 8260's
478 * address:
479 *
480 * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
481 * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
482 * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
483 * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
484 * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
485 *-----------------------------------------------------------------------------
486 */
487#define CFG_MRS_OFFS 0x00000110
488
489
490/* Bank 0 - FLASH
491 */
492#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
493 BRx_PS_64 |\
494 BRx_MS_GPCM_P |\
495 BRx_V)
496
497#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
498 ORxG_CSNT |\
499 ORxG_ACS_DIV1 |\
500 ORxG_SCY_3_CLK |\
501 ORxG_EHTR |\
502 ORxG_TRLX)
503
504 /* SDRAM on TQM8260 can have either 8 or 9 columns.
505 * The number affects configuration values.
506 */
507
508/* Bank 1 - 60x bus SDRAM
509 */
510#define CFG_PSRT 0x20
511#define CFG_LSRT 0x20
512#ifndef CFG_RAMBOOT
513#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
514 BRx_PS_64 |\
515 BRx_MS_SDRAM_P |\
516 BRx_V)
517
518#define CFG_OR1_PRELIM CFG_OR1_8COL
519
520
521 /* SDRAM initialization values for 8-column chips
522 */
523#define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
524 ORxS_BPD_4 |\
525 ORxS_ROWST_PBI1_A7 |\
526 ORxS_NUMR_12)
527
528#define CFG_PSDMR_8COL (PSDMR_PBI |\
529 PSDMR_SDAM_A15_IS_A5 |\
530 PSDMR_BSMA_A12_A14 |\
531 PSDMR_SDA10_PBI1_A8 |\
532 PSDMR_RFRC_7_CLK |\
533 PSDMR_PRETOACT_2W |\
534 PSDMR_ACTTORW_2W |\
535 PSDMR_LDOTOPRE_1C |\
536 PSDMR_WRC_2C |\
537 PSDMR_EAMUX |\
538 PSDMR_CL_2)
539
540 /* SDRAM initialization values for 9-column chips
541 */
542#define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
543 ORxS_BPD_4 |\
544 ORxS_ROWST_PBI1_A5 |\
545 ORxS_NUMR_13)
546
547#define CFG_PSDMR_9COL (PSDMR_PBI |\
548 PSDMR_SDAM_A16_IS_A5 |\
549 PSDMR_BSMA_A12_A14 |\
550 PSDMR_SDA10_PBI1_A7 |\
551 PSDMR_RFRC_7_CLK |\
552 PSDMR_PRETOACT_2W |\
553 PSDMR_ACTTORW_2W |\
554 PSDMR_LDOTOPRE_1C |\
555 PSDMR_WRC_2C |\
556 PSDMR_EAMUX |\
557 PSDMR_CL_2)
558
559/* Bank 2 - Local bus SDRAM
560 */
561#ifdef CFG_INIT_LOCAL_SDRAM
562#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
563 BRx_PS_32 |\
564 BRx_MS_SDRAM_L |\
565 BRx_V)
566
567#define CFG_OR2_PRELIM CFG_OR2_8COL
568
569#define SDRAM_BASE2_PRELIM 0x80000000
570
571 /* SDRAM initialization values for 8-column chips
572 */
573#define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
574 ORxS_BPD_4 |\
575 ORxS_ROWST_PBI1_A8 |\
576 ORxS_NUMR_12)
577
578#define CFG_LSDMR_8COL (PSDMR_PBI |\
579 PSDMR_SDAM_A15_IS_A5 |\
580 PSDMR_BSMA_A13_A15 |\
581 PSDMR_SDA10_PBI1_A9 |\
582 PSDMR_RFRC_7_CLK |\
583 PSDMR_PRETOACT_2W |\
584 PSDMR_ACTTORW_2W |\
585 PSDMR_BL |\
586 PSDMR_LDOTOPRE_1C |\
587 PSDMR_WRC_2C |\
588 PSDMR_CL_2)
589
590 /* SDRAM initialization values for 9-column chips
591 */
592#define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
593 ORxS_BPD_4 |\
594 ORxS_ROWST_PBI1_A6 |\
595 ORxS_NUMR_13)
596
597#define CFG_LSDMR_9COL (PSDMR_PBI |\
598 PSDMR_SDAM_A16_IS_A5 |\
599 PSDMR_BSMA_A13_A15 |\
600 PSDMR_SDA10_PBI1_A8 |\
601 PSDMR_RFRC_7_CLK |\
602 PSDMR_PRETOACT_2W |\
603 PSDMR_ACTTORW_2W |\
604 PSDMR_BL |\
605 PSDMR_LDOTOPRE_1C |\
606 PSDMR_WRC_2C |\
607 PSDMR_CL_2)
608
609#endif /* CFG_INIT_LOCAL_SDRAM */
610
611#endif /* CFG_RAMBOOT */
612
613#define CFG_CAN0_BASE 0xc0000000
614#define CFG_CAN1_BASE 0xc0008000
615#define CFG_FIOX_BASE 0xc0010000
616#define CFG_FDOHM_BASE 0xc0018000
617#define CFG_EXTPROM_BASE 0xc2000000
618
619#define CFG_CAN_SIZE 0x00000100
620#define CFG_FIOX_SIZE 0x00000020
621#define CFG_FDOHM_SIZE 0x00002000
622#define CFG_EXTPROM_BANK_SIZE 0x01000000
623
624#define EXT_EEPROM_MAX_FLASH_BANKS 0x02
625
626/* CS3 - CAN 0
627 */
628#define CFG_CAN0_BR3 ((CFG_CAN0_BASE & BRx_BA_MSK) |\
629 BRx_PS_8 |\
630 BRx_MS_UPMA |\
631 BRx_V)
632
633#define CFG_CAN0_OR3 (P2SZ_TO_AM(CFG_CAN_SIZE) |\
634 ORxU_BI |\
635 ORxU_EHTR_4IDLE)
636
637/* CS4 - CAN 1
638 */
639#define CFG_CAN1_BR4 ((CFG_CAN1_BASE & BRx_BA_MSK) |\
640 BRx_PS_8 |\
641 BRx_MS_UPMA |\
642 BRx_V)
643
644#define CFG_CAN1_OR4 (P2SZ_TO_AM(CFG_CAN_SIZE) |\
645 ORxU_BI |\
646 ORxU_EHTR_4IDLE)
647
648/* CS5 - Extended PROM (16MB optional)
649 */
650#define CFG_EXTPROM_BR5 ((CFG_EXTPROM_BASE & BRx_BA_MSK)|\
651 BRx_PS_32 |\
652 BRx_MS_GPCM_P |\
653 BRx_V)
654
655#define CFG_EXTPROM_OR5 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
656 ORxG_CSNT |\
657 ORxG_ACS_DIV4 |\
658 ORxG_SCY_5_CLK |\
659 ORxG_TRLX)
660
661/* CS6 - Extended PROM (16MB optional)
662 */
663#define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE + \
664 CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\
665 BRx_PS_32 |\
666 BRx_MS_GPCM_P |\
667 BRx_V)
668
669#define CFG_EXTPROM_OR6 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
670 ORxG_CSNT |\
671 ORxG_ACS_DIV4 |\
672 ORxG_SCY_5_CLK |\
673 ORxG_TRLX)
674
675/* CS7 - FPGA FIOX: Glue Logic
676 */
677#define CFG_FIOX_BR7 ((CFG_FIOX_BASE & BRx_BA_MSK) |\
678 BRx_PS_32 |\
679 BRx_MS_GPCM_P |\
680 BRx_V)
681
682#define CFG_FIOX_OR7 (P2SZ_TO_AM(CFG_FIOX_SIZE) |\
683 ORxG_ACS_DIV4 |\
684 ORxG_SCY_5_CLK |\
685 ORxG_TRLX)
686
687/* CS8 - FPGA DOH Master
688 */
689#define CFG_FDOHM_BR8 ((CFG_FDOHM_BASE & BRx_BA_MSK) |\
690 BRx_PS_16 |\
691 BRx_MS_GPCM_P |\
692 BRx_V)
693
694#define CFG_FDOHM_OR8 (P2SZ_TO_AM(CFG_FDOHM_SIZE) |\
695 ORxG_ACS_DIV4 |\
696 ORxG_SCY_5_CLK |\
697 ORxG_TRLX)
698
699
700/* FPGA configuration */
701#define CFG_PD_FIOX_PROG (1 << (31- 5)) /* PD 5 */
702#define CFG_PD_FIOX_DONE (1 << (31-28)) /* PD 28 */
703#define CFG_PD_FIOX_INIT (1 << (31-29)) /* PD 29 */
704
705#define CFG_PD_FDOHM_PROG (1 << (31- 4)) /* PD 4 */
706#define CFG_PD_FDOHM_DONE (1 << (31-26)) /* PD 26 */
707#define CFG_PD_FDOHM_INIT (1 << (31-27)) /* PD 27 */
708
709
710#endif /* __CONFIG_H */
711