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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
wdenkc6097192002-11-03 00:24:07 +000035#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000036#define CONFIG_4xx 1 /* ...member of PPC4xx family */
37#define CONFIG_DU405 1 /* ...on a DU405 board */
wdenkc6097192002-11-03 00:24:07 +000038
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
40
wdenkc837dcb2004-01-20 23:12:12 +000041#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
Stefan Roese82f4c6a2005-08-12 16:52:47 +020042#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
wdenkc6097192002-11-03 00:24:07 +000043
wdenkc837dcb2004-01-20 23:12:12 +000044#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000045
46#define CONFIG_BAUDRATE 9600
47#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48
49#undef CONFIG_BOOTARGS
50#define CONFIG_BOOTCOMMAND "bootm fff00000"
51
52#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +000054
Ben Warren96e21f82008-10-27 23:50:15 -070055#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +000056#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000057#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000058#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchs09db8f42009-02-20 10:19:15 +010059#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
60#define CONFIG_NET_MULTI 1
61#undef CONFIG_HAS_ETH1
Jon Loeliger3c3227f2007-07-07 20:40:43 -050062
63/*
Jon Loeliger11799432007-07-10 09:02:57 -050064 * BOOTP options
65 */
66#define CONFIG_BOOTP_BOOTFILESIZE
67#define CONFIG_BOOTP_BOOTPATH
68#define CONFIG_BOOTP_GATEWAY
69#define CONFIG_BOOTP_HOSTNAME
70
71
72/*
Jon Loeliger3c3227f2007-07-07 20:40:43 -050073 * Command line configuration.
74 */
75#include <config_cmd_default.h>
76
Matthias Fuchs09db8f42009-02-20 10:19:15 +010077#undef CONFIG_CMD_NFS
Matthias Fuchs5b9144632010-09-21 09:38:04 +020078#undef CONFIG_CMD_EDITENV
79#undef CONFIG_CMD_IMLS
80#undef CONFIG_CMD_CONSOLE
81#undef CONFIG_CMD_LOADB
82#undef CONFIG_CMD_LOADS
Jon Loeliger3c3227f2007-07-07 20:40:43 -050083#define CONFIG_CMD_IDE
84#define CONFIG_CMD_ELF
85#define CONFIG_CMD_MII
86#define CONFIG_CMD_DATE
87#define CONFIG_CMD_EEPROM
Matthias Fuchs09db8f42009-02-20 10:19:15 +010088#define CONFIG_CMD_I2C
wdenkc6097192002-11-03 00:24:07 +000089
90#define CONFIG_MAC_PARTITION
91#define CONFIG_DOS_PARTITION
92
wdenkc6097192002-11-03 00:24:07 +000093#undef CONFIG_WATCHDOG /* watchdog disabled */
94
wdenkc837dcb2004-01-20 23:12:12 +000095#define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000080 /* RTC Base Address */
wdenkc6097192002-11-03 00:24:07 +000097
wdenkc837dcb2004-01-20 23:12:12 +000098#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +000099
100/*
101 * Miscellaneous configurable options
102 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_LONGHELP /* undef to save memory */
104#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger3c3227f2007-07-07 20:40:43 -0500105#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000107#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000109#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
111#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
112#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +0000115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
117#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000118
Stefan Roese550650d2010-09-20 16:05:31 +0200119#define CONFIG_CONS_INDEX 1 /* Use UART0 */
120#define CONFIG_SYS_NS16550
121#define CONFIG_SYS_NS16550_SERIAL
122#define CONFIG_SYS_NS16550_REG_SIZE 1
123#define CONFIG_SYS_NS16550_CLK get_serial_clock()
124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */
wdenkc6097192002-11-03 00:24:07 +0000126
127/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000129 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
130 57600, 115200, 230400, 460800, 921600 }
wdenkc6097192002-11-03 00:24:07 +0000131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
133#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkc6097192002-11-03 00:24:07 +0000134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000136
137#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroesea20b27a2004-12-16 18:05:42 +0000140
wdenkc6097192002-11-03 00:24:07 +0000141/*-----------------------------------------------------------------------
wdenkc6097192002-11-03 00:24:07 +0000142 * IDE/ATA stuff
143 *-----------------------------------------------------------------------
144 */
wdenkc837dcb2004-01-20 23:12:12 +0000145#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
146#undef CONFIG_IDE_LED /* no led for ide supported */
147#undef CONFIG_IDE_RESET /* no reset for ide supported */
wdenkc6097192002-11-03 00:24:07 +0000148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
150#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
153#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkc6097192002-11-03 00:24:07 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
156#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
157#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
wdenkc6097192002-11-03 00:24:07 +0000158
159/*-----------------------------------------------------------------------
160 * Start addresses for the final memory configuration
161 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_SDRAM_BASE 0x00000000
165#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
166#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
167#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
168#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000169
170/*
171 * For booting Linux, the board info and command line data
172 * have to be in the first 8 MB of memory, since this is
173 * the maximum mapped by the Linux kernel during initialization.
174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000176/*-----------------------------------------------------------------------
177 * FLASH organization
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
180#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
183#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
186#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
187#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000188/*
189 * The following defines are added for buggy IOP480 byte interface.
190 * All other boards should use the standard values (CPCI405 etc.)
191 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
193#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
194#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000197
198/*-----------------------------------------------------------------------
199 * I2C EEPROM (CAT24WC08) for environment
200 */
201#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200202#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
204#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkc6097192002-11-03 00:24:07 +0000205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
207#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +0000208/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
210#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenkc6097192002-11-03 00:24:07 +0000211 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000212 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +0000214
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200215#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200216#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
217#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
wdenk8bde7f72003-06-27 21:31:46 +0000218 /* total size of a CAT24WC08 is 1024 bytes */
wdenkc6097192002-11-03 00:24:07 +0000219
wdenkc6097192002-11-03 00:24:07 +0000220/*
221 * Init Memory Controller:
222 *
223 * BR0/1 and OR0/1 (FLASH)
224 */
225
226#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
227#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
228
229/*-----------------------------------------------------------------------
230 * External Bus Controller (EBC) Setup
231 */
232
wdenkc837dcb2004-01-20 23:12:12 +0000233#define FLASH0_BA 0xFFC00000 /* FLASH 0 Base Address */
234#define FLASH1_BA 0xFF800000 /* FLASH 1 Base Address */
235#define CAN_BA 0xF0000000 /* CAN Base Address */
236#define DUART_BA 0xF0300000 /* DUART Base Address */
237#define CF_BA 0xF0100000 /* CompactFlash Base Address */
238#define SRAM_BA 0xF0200000 /* SRAM Base Address */
239#define DURAG_IO_BA 0xF0400000 /* DURAG Bus IO Base Address */
240#define DURAG_MEM_BA 0xF0500000 /* DURAG Bus Mem Base Address */
wdenkc6097192002-11-03 00:24:07 +0000241
wdenkc837dcb2004-01-20 23:12:12 +0000242#define FPGA_MODE_REG (DUART_BA+0x80) /* FPGA Mode Register */
wdenkc6097192002-11-03 00:24:07 +0000243
wdenkc837dcb2004-01-20 23:12:12 +0000244/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_EBC_PB0AP 0x92015480
246#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000247
wdenkc837dcb2004-01-20 23:12:12 +0000248/* Memory Bank 1 (Flash Bank 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_EBC_PB1AP 0x92015480
250#define CONFIG_SYS_EBC_PB1CR FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000251
wdenkc837dcb2004-01-20 23:12:12 +0000252/* Memory Bank 2 (CAN0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
254#define CONFIG_SYS_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000255
wdenkc837dcb2004-01-20 23:12:12 +0000256/* Memory Bank 3 (DUART) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
258#define CONFIG_SYS_EBC_PB3CR DUART_BA | 0x18000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000259
wdenkc837dcb2004-01-20 23:12:12 +0000260/* Memory Bank 4 (CompactFlash IDE) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_EBC_PB4AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
262#define CONFIG_SYS_EBC_PB4CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000263
wdenkc837dcb2004-01-20 23:12:12 +0000264/* Memory Bank 5 (SRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_EBC_PB5AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
266#define CONFIG_SYS_EBC_PB5CR SRAM_BA | 0x1A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000267
wdenkc837dcb2004-01-20 23:12:12 +0000268/* Memory Bank 6 (DURAG Bus IO Space) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
270#define CONFIG_SYS_EBC_PB6CR DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
wdenkc6097192002-11-03 00:24:07 +0000271
wdenkc837dcb2004-01-20 23:12:12 +0000272/* Memory Bank 7 (DURAG Bus Mem Space) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_EBC_PB7AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
274#define CONFIG_SYS_EBC_PB7CR DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000275
276
277/*-----------------------------------------------------------------------
278 * Definitions for initial stack pointer and data area (in DPRAM)
279 */
280
281/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_TEMP_STACK_OCM 1
wdenkc6097192002-11-03 00:24:07 +0000283
284/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
286#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
wdenkc6097192002-11-03 00:24:07 +0000287
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200289#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200290#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000292
wdenkc6097192002-11-03 00:24:07 +0000293#endif /* __CONFIG_H */