blob: 1191eea106c00dcfd66a6db22060ae0e948b6a00 [file] [log] [blame]
Kim Phillips1c274c42007-07-25 19:25:33 -05001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Kim Phillips1c274c42007-07-25 19:25:33 -050012/*
13 * High Level Configuration Options
14 */
15#define CONFIG_E300 1 /* E300 family */
16#define CONFIG_QE 1 /* Has QE */
Peter Tyser0f898602009-05-22 17:23:24 -050017#define CONFIG_MPC83xx 1 /* MPC83xx family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050018#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
Kim Phillips1c274c42007-07-25 19:25:33 -050019
Wolfgang Denk2ae18242010-10-06 09:05:45 +020020#define CONFIG_SYS_TEXT_BASE 0xFE000000
21
Kim Phillips1c274c42007-07-25 19:25:33 -050022#define CONFIG_PCI 1
Kim Phillips1c274c42007-07-25 19:25:33 -050023
24/*
25 * System Clock Setup
26 */
27#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
28
29#ifndef CONFIG_SYS_CLK_FREQ
30#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
31#endif
32
33/*
34 * Hardware Reset Configuration Word
35 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#define CONFIG_SYS_HRCW_LOW (\
Kim Phillips1c274c42007-07-25 19:25:33 -050037 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
38 HRCWL_DDR_TO_SCB_CLK_2X1 |\
39 HRCWL_VCO_1X2 |\
40 HRCWL_CSB_TO_CLKIN_2X1 |\
41 HRCWL_CORE_TO_CSB_2_5X1 |\
42 HRCWL_CE_PLL_VCO_DIV_2 |\
43 HRCWL_CE_PLL_DIV_1X1 |\
44 HRCWL_CE_TO_PLL_1X3)
45
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_HRCW_HIGH (\
Kim Phillips1c274c42007-07-25 19:25:33 -050047 HRCWH_PCI_HOST |\
48 HRCWH_PCI1_ARBITER_ENABLE |\
49 HRCWH_CORE_ENABLE |\
50 HRCWH_FROM_0X00000100 |\
51 HRCWH_BOOTSEQ_DISABLE |\
52 HRCWH_SW_WATCHDOG_DISABLE |\
53 HRCWH_ROM_LOC_LOCAL_16BIT |\
54 HRCWH_BIG_ENDIAN |\
55 HRCWH_LALE_NORMAL)
56
57/*
58 * System IO Config
59 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_SICRL 0x00000000
Kim Phillips1c274c42007-07-25 19:25:33 -050061
62#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
63
64/*
65 * IMMR new address
66 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_IMMR 0xE0000000
Kim Phillips1c274c42007-07-25 19:25:33 -050068
69/*
Michael Barkowski5bbeea82008-03-20 13:15:34 -040070 * System performance
71 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
73#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
74#define CONFIG_SYS_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
Michael Barkowski5bbeea82008-03-20 13:15:34 -040075
76/*
Kim Phillips1c274c42007-07-25 19:25:33 -050077 * DDR Setup
78 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
80#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
81#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
82#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
Kim Phillips1c274c42007-07-25 19:25:33 -050083
84#undef CONFIG_SPD_EEPROM
85#if defined(CONFIG_SPD_EEPROM)
86/* Determine DDR configuration from I2C interface
87 */
88#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
89#else
90/* Manually set up DDR parameters
91 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_DDR_SIZE 64 /* MB */
93#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \
Michael Barkowski5bbeea82008-03-20 13:15:34 -040094 | CSCONFIG_ODT_WR_ACS \
Michael Barkowskifc549c82008-03-20 13:15:28 -040095 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 )
Michael Barkowski5bbeea82008-03-20 13:15:34 -040096 /* 0x80010101 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
Michael Barkowskifc549c82008-03-20 13:15:28 -040098 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
99 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
100 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
101 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
102 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
103 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
104 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
105 /* 0x00220802 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400107 | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
108 | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
Michael Barkowskifc549c82008-03-20 13:15:28 -0400109 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400110 | ( 3 << TIMING_CFG1_REFREC_SHIFT ) \
111 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
Michael Barkowskifc549c82008-03-20 13:15:28 -0400112 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
113 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400114 /* 0x26253222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400116 | (31 << TIMING_CFG2_CPO_SHIFT ) \
Michael Barkowskifc549c82008-03-20 13:15:28 -0400117 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
118 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
119 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
120 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400121 | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
122 /* 0x1f9048c7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_DDR_TIMING_3 0x00000000
124#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Michael Barkowskifc549c82008-03-20 13:15:28 -0400125 /* 0x02000000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
Michael Barkowskifc549c82008-03-20 13:15:28 -0400127 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400128 /* 0x44480232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_DDR_MODE2 0x8000c000
130#define CONFIG_SYS_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
Michael Barkowskifc549c82008-03-20 13:15:28 -0400131 | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
132 /* 0x03200064 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
134#define CONFIG_SYS_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \
Michael Barkowskifc549c82008-03-20 13:15:28 -0400135 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
136 | SDRAM_CFG_32_BE )
137 /* 0x43080000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
Kim Phillips1c274c42007-07-25 19:25:33 -0500139#endif
140
141/*
142 * Memory test
143 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
145#define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
146#define CONFIG_SYS_MEMTEST_END 0x03f00000
Kim Phillips1c274c42007-07-25 19:25:33 -0500147
148/*
149 * The reserved memory
150 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200151#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Kim Phillips1c274c42007-07-25 19:25:33 -0500152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
154#define CONFIG_SYS_RAMBOOT
Kim Phillips1c274c42007-07-25 19:25:33 -0500155#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#undef CONFIG_SYS_RAMBOOT
Kim Phillips1c274c42007-07-25 19:25:33 -0500157#endif
158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Kim Phillips4a9932a2009-07-07 18:04:21 -0500160#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Kim Phillips1c274c42007-07-25 19:25:33 -0500162
163/*
164 * Initial RAM Base Address Setup
165 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_INIT_RAM_LOCK 1
167#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200168#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200169#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Kim Phillips1c274c42007-07-25 19:25:33 -0500170
171/*
172 * Local Bus Configuration & Clock Setup
173 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500174#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
175#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_LBC_LBCR 0x00000000
Kim Phillips1c274c42007-07-25 19:25:33 -0500177
178/*
179 * FLASH on the Local Bus
180 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200182#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
184#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
185#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Kim Phillips1c274c42007-07-25 19:25:33 -0500186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
188#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
Kim Phillips1c274c42007-07-25 19:25:33 -0500189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
Kim Phillips1c274c42007-07-25 19:25:33 -0500191 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
192 BR_V) /* valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
Kim Phillips1c274c42007-07-25 19:25:33 -0500194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
196#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
Kim Phillips1c274c42007-07-25 19:25:33 -0500197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#undef CONFIG_SYS_FLASH_CHECKSUM
Kim Phillips1c274c42007-07-25 19:25:33 -0500199
200/*
201 * SDRAM on the Local Bus
202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */
Kim Phillips1c274c42007-07-25 19:25:33 -0500204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#ifdef CONFIG_SYS_LB_SDRAM
206#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
207#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Kim Phillips1c274c42007-07-25 19:25:33 -0500208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
210#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
Kim Phillips1c274c42007-07-25 19:25:33 -0500211
212/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
213/*
214 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Kim Phillips1c274c42007-07-25 19:25:33 -0500216 *
217 * For BR2, need:
218 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
219 * port size = 32-bits = BR2[19:20] = 11
220 * no parity checking = BR2[21:22] = 00
221 * SDRAM for MSEL = BR2[24:26] = 011
222 * Valid = BR[31] = 1
223 *
224 * 0 4 8 12 16 20 24 28
225 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
226 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227 * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
Kim Phillips1c274c42007-07-25 19:25:33 -0500228 * the top 17 bits of BR2.
229 */
230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
Kim Phillips1c274c42007-07-25 19:25:33 -0500232
233/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Kim Phillips1c274c42007-07-25 19:25:33 -0500235 *
236 * For OR2, need:
237 * 64MB mask for AM, OR2[0:7] = 1111 1100
238 * XAM, OR2[17:18] = 11
239 * 9 columns OR2[19-21] = 010
240 * 13 rows OR2[23-25] = 100
241 * EAD set for extra time OR[31] = 1
242 *
243 * 0 4 8 12 16 20 24 28
244 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
245 */
246
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_OR2_PRELIM 0xfc006901
Kim Phillips1c274c42007-07-25 19:25:33 -0500248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
250#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
Kim Phillips1c274c42007-07-25 19:25:33 -0500251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
Kim Phillips1c274c42007-07-25 19:25:33 -0500253
Kim Phillips1c274c42007-07-25 19:25:33 -0500254#endif
255
256/*
257 * Windows to access PIB via local bus
258 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
260#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
Kim Phillips1c274c42007-07-25 19:25:33 -0500261
262/*
263 * Serial Port
264 */
265#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_NS16550
267#define CONFIG_SYS_NS16550_SERIAL
268#define CONFIG_SYS_NS16550_REG_SIZE 1
269#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kim Phillips1c274c42007-07-25 19:25:33 -0500270
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_BAUDRATE_TABLE \
Kim Phillips1c274c42007-07-25 19:25:33 -0500272 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
273
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
275#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Kim Phillips1c274c42007-07-25 19:25:33 -0500276
277#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500278#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Kim Phillips1c274c42007-07-25 19:25:33 -0500279/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_HUSH_PARSER
281#ifdef CONFIG_SYS_HUSH_PARSER
282#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Kim Phillips1c274c42007-07-25 19:25:33 -0500283#endif
284
285/* pass open firmware flat tree */
286#define CONFIG_OF_LIBFDT 1
287#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600288#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Kim Phillips1c274c42007-07-25 19:25:33 -0500289
290/* I2C */
291#define CONFIG_HARD_I2C /* I2C with hardware support */
292#undef CONFIG_SOFT_I2C /* I2C bit-banged */
293#define CONFIG_FSL_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
295#define CONFIG_SYS_I2C_SLAVE 0x7F
296#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
297#define CONFIG_SYS_I2C_OFFSET 0x3000
Kim Phillips1c274c42007-07-25 19:25:33 -0500298
299/*
Michael Barkowski0fa7a1b2008-03-20 13:15:39 -0400300 * Config on-board EEPROM
Kim Phillips1c274c42007-07-25 19:25:33 -0500301 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
303#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
304#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
305#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Kim Phillips1c274c42007-07-25 19:25:33 -0500306
307/*
308 * General PCI
309 * Addresses are mapped 1-1.
310 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
312#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
313#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
314#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
315#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
316#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
317#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
318#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
319#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
Kim Phillips1c274c42007-07-25 19:25:33 -0500320
321#ifdef CONFIG_PCI
Michael Barkowski8f325cf2008-03-28 15:15:38 -0400322#define CONFIG_PCI_SKIP_HOST_BRIDGE
Kim Phillips1c274c42007-07-25 19:25:33 -0500323#define CONFIG_NET_MULTI
324#define CONFIG_PCI_PNP /* do pci plug-and-play */
325
326#undef CONFIG_EEPRO100
327#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Kim Phillips1c274c42007-07-25 19:25:33 -0500329
330#endif /* CONFIG_PCI */
331
332
333#ifndef CONFIG_NET_MULTI
334#define CONFIG_NET_MULTI 1
335#endif
336
337/*
338 * QE UEC ethernet configuration
339 */
340#define CONFIG_UEC_ETH
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500341#define CONFIG_ETHPRIME "UEC0"
Kim Phillips1c274c42007-07-25 19:25:33 -0500342
343#define CONFIG_UEC_ETH1 /* ETH3 */
344
345#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
347#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
348#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
349#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
350#define CONFIG_SYS_UEC1_PHY_ADDR 4
Heiko Schocher582c55a2010-01-20 09:04:28 +0100351#define CONFIG_SYS_UEC1_INTERFACE_TYPE MII
352#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
Kim Phillips1c274c42007-07-25 19:25:33 -0500353#endif
354
355#define CONFIG_UEC_ETH2 /* ETH4 */
356
357#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
359#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
360#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
361#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
362#define CONFIG_SYS_UEC2_PHY_ADDR 0
Heiko Schocher582c55a2010-01-20 09:04:28 +0100363#define CONFIG_SYS_UEC2_INTERFACE_TYPE MII
364#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
Kim Phillips1c274c42007-07-25 19:25:33 -0500365#endif
366
367/*
368 * Environment
369 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200371 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200373 #define CONFIG_ENV_SECT_SIZE 0x20000
374 #define CONFIG_ENV_SIZE 0x2000
Kim Phillips1c274c42007-07-25 19:25:33 -0500375#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200377 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200379 #define CONFIG_ENV_SIZE 0x2000
Kim Phillips1c274c42007-07-25 19:25:33 -0500380#endif
381
382#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kim Phillips1c274c42007-07-25 19:25:33 -0500384
385/*
386 * BOOTP options
387 */
388#define CONFIG_BOOTP_BOOTFILESIZE
389#define CONFIG_BOOTP_BOOTPATH
390#define CONFIG_BOOTP_GATEWAY
391#define CONFIG_BOOTP_HOSTNAME
392
393/*
394 * Command line configuration.
395 */
396#include <config_cmd_default.h>
397
398#define CONFIG_CMD_PING
399#define CONFIG_CMD_I2C
Michael Barkowski0fa7a1b2008-03-20 13:15:39 -0400400#define CONFIG_CMD_EEPROM
Kim Phillips1c274c42007-07-25 19:25:33 -0500401#define CONFIG_CMD_ASKENV
402
403#if defined(CONFIG_PCI)
404 #define CONFIG_CMD_PCI
405#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500407 #undef CONFIG_CMD_SAVEENV
Kim Phillips1c274c42007-07-25 19:25:33 -0500408 #undef CONFIG_CMD_LOADS
409#endif
410
411#undef CONFIG_WATCHDOG /* watchdog disabled */
412
413/*
414 * Miscellaneous configurable options
415 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_LONGHELP /* undef to save memory */
417#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
418#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Kim Phillips1c274c42007-07-25 19:25:33 -0500419
420#if (CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kim Phillips1c274c42007-07-25 19:25:33 -0500422#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kim Phillips1c274c42007-07-25 19:25:33 -0500424#endif
425
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
427#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
428#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
429#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Kim Phillips1c274c42007-07-25 19:25:33 -0500430
431/*
432 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700433 * have to be in the first 256 MB of memory, since this is
Kim Phillips1c274c42007-07-25 19:25:33 -0500434 * the maximum mapped by the Linux kernel during initialization.
435 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700436#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Kim Phillips1c274c42007-07-25 19:25:33 -0500437
438/*
439 * Core HID Setup
440 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500441#define CONFIG_SYS_HID0_INIT 0x000000000
442#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
443 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_HID2 HID2_HBE
Kim Phillips1c274c42007-07-25 19:25:33 -0500445
446/*
Kim Phillips1c274c42007-07-25 19:25:33 -0500447 * MMU Setup
448 */
Becky Bruce31d82672008-05-08 19:02:12 -0500449#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Kim Phillips1c274c42007-07-25 19:25:33 -0500450
451/* DDR: cache cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
453#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
454#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
455#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Kim Phillips1c274c42007-07-25 19:25:33 -0500456
457/* IMMRBAR & PCI IO: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
Kim Phillips1c274c42007-07-25 19:25:33 -0500459 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
461#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
462#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Kim Phillips1c274c42007-07-25 19:25:33 -0500463
464/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
466#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
467#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
Kim Phillips1c274c42007-07-25 19:25:33 -0500468 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Kim Phillips1c274c42007-07-25 19:25:33 -0500470
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_IBAT3L (0)
472#define CONFIG_SYS_IBAT3U (0)
473#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
474#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Kim Phillips1c274c42007-07-25 19:25:33 -0500475
476/* Stack in dcache: cacheable, no memory coherence */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
478#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
479#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
480#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Kim Phillips1c274c42007-07-25 19:25:33 -0500481
482#ifdef CONFIG_PCI
483/* PCI MEM space: cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
485#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
486#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
487#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Kim Phillips1c274c42007-07-25 19:25:33 -0500488/* PCI MMIO space: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
Kim Phillips1c274c42007-07-25 19:25:33 -0500490 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
492#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
493#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Kim Phillips1c274c42007-07-25 19:25:33 -0500494#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#define CONFIG_SYS_IBAT5L (0)
496#define CONFIG_SYS_IBAT5U (0)
497#define CONFIG_SYS_IBAT6L (0)
498#define CONFIG_SYS_IBAT6U (0)
499#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
500#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
501#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
502#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Kim Phillips1c274c42007-07-25 19:25:33 -0500503#endif
504
505/* Nothing in BAT7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200506#define CONFIG_SYS_IBAT7L (0)
507#define CONFIG_SYS_IBAT7U (0)
508#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
509#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Kim Phillips1c274c42007-07-25 19:25:33 -0500510
Kim Phillips1c274c42007-07-25 19:25:33 -0500511#if (CONFIG_CMD_KGDB)
512#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
513#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
514#endif
515
516/*
517 * Environment Configuration
518 */
519#define CONFIG_ENV_OVERWRITE
520
Kim Phillips977b5752008-01-09 15:24:06 -0600521#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
Kim Phillips1c274c42007-07-25 19:25:33 -0500522#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
Kim Phillips1c274c42007-07-25 19:25:33 -0500523
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200524/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
525#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 /* MAC address offset in I2C EEPROM */
Michael Barkowski5b2793a2008-03-27 14:34:43 -0400526
Kim Phillips1c274c42007-07-25 19:25:33 -0500527#define CONFIG_NETDEV eth1
528
529#define CONFIG_HOSTNAME mpc8323erdb
530#define CONFIG_ROOTPATH /nfsroot
531#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
532#define CONFIG_BOOTFILE uImage
533#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
534#define CONFIG_FDTFILE mpc832x_rdb.dtb
535
Kim Phillips79f516b2009-08-21 16:34:38 -0500536#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Kim Phillips7fd0bea2008-09-24 08:46:25 -0500537#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Kim Phillips1c274c42007-07-25 19:25:33 -0500538#define CONFIG_BAUDRATE 115200
539
540#define XMK_STR(x) #x
541#define MK_STR(x) XMK_STR(x)
542
543#define CONFIG_EXTRA_ENV_SETTINGS \
544 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
545 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
546 "tftpflash=tftp $loadaddr $uboot;" \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200547 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
548 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
549 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
550 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
551 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500552 "fdtaddr=780000\0" \
Kim Phillips1c274c42007-07-25 19:25:33 -0500553 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
554 "ramdiskaddr=1000000\0" \
555 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
556 "console=ttyS0\0" \
557 "setbootargs=setenv bootargs " \
558 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
559 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
560 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
561 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
562
563#define CONFIG_NFSBOOTCOMMAND \
564 "setenv rootdev /dev/nfs;" \
565 "run setbootargs;" \
566 "run setipargs;" \
567 "tftp $loadaddr $bootfile;" \
568 "tftp $fdtaddr $fdtfile;" \
569 "bootm $loadaddr - $fdtaddr"
570
571#define CONFIG_RAMBOOTCOMMAND \
572 "setenv rootdev /dev/ram;" \
573 "run setbootargs;" \
574 "tftp $ramdiskaddr $ramdiskfile;" \
575 "tftp $loadaddr $bootfile;" \
576 "tftp $fdtaddr $fdtfile;" \
577 "bootm $loadaddr $ramdiskaddr $fdtaddr"
578
579#undef MK_STR
580#undef XMK_STR
581
582#endif /* __CONFIG_H */