| Peter Chubb | b615267 | 2016-08-30 22:54:46 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2014 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <power/as3722.h> |
| 10 | |
| 11 | #include <asm/arch/gpio.h> |
| 12 | #include <asm/arch/pinmux.h> |
| 13 | |
| 14 | #include "pinmux-config-cei-tk1-som.h" |
| 15 | |
| 16 | DECLARE_GLOBAL_DATA_PTR; |
| 17 | |
| 18 | /* |
| 19 | * Routine: pinmux_init |
| 20 | * Description: Do individual peripheral pinmux configs |
| 21 | */ |
| 22 | void pinmux_init(void) |
| 23 | { |
| 24 | pinmux_clear_tristate_input_clamping(); |
| 25 | |
| 26 | gpio_config_table(cei_tk1_som_gpio_inits, |
| 27 | ARRAY_SIZE(cei_tk1_som_gpio_inits)); |
| 28 | |
| 29 | pinmux_config_pingrp_table(cei_tk1_som_pingrps, |
| 30 | ARRAY_SIZE(cei_tk1_som_pingrps)); |
| 31 | |
| 32 | pinmux_config_drvgrp_table(cei_tk1_som_drvgrps, |
| 33 | ARRAY_SIZE(cei_tk1_som_drvgrps)); |
| 34 | |
| 35 | pinmux_config_mipipadctrlgrp_table(cei_tk1_som_mipipadctrlgrps, |
| 36 | ARRAY_SIZE(cei_tk1_som_mipipadctrlgrps)); |
| 37 | } |
| 38 | |
| 39 | #ifdef CONFIG_PCI_TEGRA |
| 40 | int tegra_pcie_board_init(void) |
| 41 | { |
| 42 | struct udevice *pmic; |
| 43 | int err; |
| 44 | |
| 45 | err = as3722_init(&pmic); |
| 46 | if (err) { |
| 47 | error("failed to initialize AS3722 PMIC: %d\n", err); |
| 48 | return err; |
| 49 | } |
| 50 | |
| 51 | err = as3722_sd_enable(pmic, 4); |
| 52 | if (err < 0) { |
| 53 | error("failed to enable SD4: %d\n", err); |
| 54 | return err; |
| 55 | } |
| 56 | |
| 57 | err = as3722_sd_set_voltage(pmic, 4, 0x24); |
| 58 | if (err < 0) { |
| 59 | error("failed to set SD4 voltage: %d\n", err); |
| 60 | return err; |
| 61 | } |
| 62 | |
| 63 | return 0; |
| 64 | } |
| 65 | #endif /* PCI */ |