| Mike Frysinger | d4d7730 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 1 | /* DO NOT EDIT THIS FILE |
| 2 | * Automatically generated by generate-cdef-headers.xsl |
| 3 | * DO NOT EDIT THIS FILE |
| 4 | */ |
| 5 | |
| 6 | #ifndef __BFIN_CDEF_ADSP_BF524_proc__ |
| 7 | #define __BFIN_CDEF_ADSP_BF524_proc__ |
| 8 | |
| 9 | #include "../mach-common/ADSP-EDN-core_cdef.h" |
| 10 | |
| 11 | #include "ADSP-EDN-BF52x-extended_cdef.h" |
| 12 | |
| 13 | #define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ |
| 14 | #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) |
| 15 | #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) |
| 16 | #define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ |
| 17 | #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) |
| 18 | #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) |
| 19 | #define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ |
| 20 | #define bfin_read_VR_CTL() bfin_read16(VR_CTL) |
| 21 | #define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) |
| 22 | #define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ |
| 23 | #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) |
| 24 | #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) |
| 25 | #define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ |
| 26 | #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) |
| 27 | #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) |
| 28 | #define pCHIPID ((uint32_t volatile *)CHIPID) |
| 29 | #define bfin_read_CHIPID() bfin_read32(CHIPID) |
| 30 | #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) |
| 31 | #define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ |
| 32 | #define bfin_read_SWRST() bfin_read16(SWRST) |
| 33 | #define bfin_write_SWRST(val) bfin_write16(SWRST, val) |
| 34 | #define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ |
| 35 | #define bfin_read_SYSCR() bfin_read16(SYSCR) |
| 36 | #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) |
| 37 | #define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ |
| 38 | #define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) |
| 39 | #define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) |
| 40 | #define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ |
| 41 | #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) |
| 42 | #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) |
| 43 | #define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ |
| 44 | #define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) |
| 45 | #define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) |
| 46 | #define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ |
| 47 | #define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) |
| 48 | #define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) |
| 49 | #define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ |
| 50 | #define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) |
| 51 | #define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) |
| 52 | #define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ |
| 53 | #define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) |
| 54 | #define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) |
| 55 | #define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ |
| 56 | #define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) |
| 57 | #define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) |
| 58 | #define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ |
| 59 | #define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) |
| 60 | #define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) |
| 61 | #define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ |
| 62 | #define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) |
| 63 | #define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) |
| 64 | #define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ |
| 65 | #define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) |
| 66 | #define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) |
| 67 | #define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ |
| 68 | #define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) |
| 69 | #define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) |
| 70 | #define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ |
| 71 | #define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) |
| 72 | #define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) |
| 73 | #define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ |
| 74 | #define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) |
| 75 | #define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) |
| 76 | #define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ |
| 77 | #define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) |
| 78 | #define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) |
| 79 | #define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ |
| 80 | #define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) |
| 81 | #define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) |
| 82 | #define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ |
| 83 | #define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) |
| 84 | #define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) |
| 85 | #define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ |
| 86 | #define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) |
| 87 | #define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) |
| 88 | #define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ |
| 89 | #define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) |
| 90 | #define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) |
| 91 | #define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ |
| 92 | #define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) |
| 93 | #define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) |
| 94 | #define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ |
| 95 | #define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) |
| 96 | #define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) |
| 97 | #define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ |
| 98 | #define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) |
| 99 | #define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) |
| 100 | #define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ |
| 101 | #define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) |
| 102 | #define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) |
| 103 | #define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ |
| 104 | #define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) |
| 105 | #define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) |
| 106 | #define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ |
| 107 | #define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) |
| 108 | #define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) |
| 109 | #define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ |
| 110 | #define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) |
| 111 | #define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) |
| 112 | #define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ |
| 113 | #define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) |
| 114 | #define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) |
| 115 | #define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ |
| 116 | #define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) |
| 117 | #define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) |
| 118 | #define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ |
| 119 | #define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) |
| 120 | #define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) |
| 121 | #define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ |
| 122 | #define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) |
| 123 | #define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) |
| 124 | #define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ |
| 125 | #define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) |
| 126 | #define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) |
| 127 | #define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ |
| 128 | #define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) |
| 129 | #define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) |
| 130 | #define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ |
| 131 | #define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) |
| 132 | #define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) |
| 133 | #define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ |
| 134 | #define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) |
| 135 | #define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) |
| 136 | #define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ |
| 137 | #define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) |
| 138 | #define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) |
| 139 | #define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ |
| 140 | #define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) |
| 141 | #define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) |
| 142 | #define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ |
| 143 | #define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) |
| 144 | #define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) |
| 145 | #define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ |
| 146 | #define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) |
| 147 | #define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) |
| 148 | #define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ |
| 149 | #define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) |
| 150 | #define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) |
| 151 | #define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ |
| 152 | #define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) |
| 153 | #define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) |
| 154 | #define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ |
| 155 | #define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) |
| 156 | #define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) |
| 157 | #define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ |
| 158 | #define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) |
| 159 | #define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) |
| 160 | #define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ |
| 161 | #define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) |
| 162 | #define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) |
| 163 | #define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ |
| 164 | #define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) |
| 165 | #define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) |
| 166 | #define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ |
| 167 | #define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) |
| 168 | #define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) |
| 169 | #define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ |
| 170 | #define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) |
| 171 | #define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) |
| 172 | #define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ |
| 173 | #define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) |
| 174 | #define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) |
| 175 | #define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ |
| 176 | #define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) |
| 177 | #define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) |
| 178 | #define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ |
| 179 | #define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) |
| 180 | #define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) |
| 181 | #define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ |
| 182 | #define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) |
| 183 | #define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) |
| 184 | #define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ |
| 185 | #define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) |
| 186 | #define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) |
| 187 | #define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ |
| 188 | #define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) |
| 189 | #define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) |
| 190 | #define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ |
| 191 | #define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) |
| 192 | #define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) |
| 193 | #define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ |
| 194 | #define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) |
| 195 | #define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) |
| 196 | #define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ |
| 197 | #define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) |
| 198 | #define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) |
| 199 | #define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ |
| 200 | #define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) |
| 201 | #define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) |
| 202 | #define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ |
| 203 | #define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) |
| 204 | #define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) |
| 205 | #define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ |
| 206 | #define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) |
| 207 | #define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) |
| 208 | #define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ |
| 209 | #define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) |
| 210 | #define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) |
| 211 | #define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ |
| 212 | #define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) |
| 213 | #define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) |
| 214 | #define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ |
| 215 | #define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) |
| 216 | #define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) |
| 217 | #define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ |
| 218 | #define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) |
| 219 | #define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) |
| 220 | #define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ |
| 221 | #define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) |
| 222 | #define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) |
| 223 | #define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ |
| 224 | #define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) |
| 225 | #define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) |
| 226 | #define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ |
| 227 | #define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) |
| 228 | #define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) |
| 229 | #define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ |
| 230 | #define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) |
| 231 | #define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) |
| 232 | #define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ |
| 233 | #define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) |
| 234 | #define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) |
| 235 | #define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ |
| 236 | #define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) |
| 237 | #define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) |
| 238 | #define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ |
| 239 | #define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) |
| 240 | #define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) |
| 241 | #define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ |
| 242 | #define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) |
| 243 | #define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) |
| 244 | #define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ |
| 245 | #define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) |
| 246 | #define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) |
| 247 | #define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ |
| 248 | #define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) |
| 249 | #define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) |
| 250 | #define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ |
| 251 | #define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) |
| 252 | #define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) |
| 253 | #define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ |
| 254 | #define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) |
| 255 | #define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) |
| 256 | #define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ |
| 257 | #define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) |
| 258 | #define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) |
| 259 | #define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ |
| 260 | #define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) |
| 261 | #define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) |
| 262 | #define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ |
| 263 | #define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) |
| 264 | #define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) |
| 265 | #define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ |
| 266 | #define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) |
| 267 | #define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) |
| 268 | #define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ |
| 269 | #define bfin_read_EVT0() bfin_readPTR(EVT0) |
| 270 | #define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) |
| 271 | #define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ |
| 272 | #define bfin_read_EVT1() bfin_readPTR(EVT1) |
| 273 | #define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) |
| 274 | #define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ |
| 275 | #define bfin_read_EVT2() bfin_readPTR(EVT2) |
| 276 | #define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) |
| 277 | #define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ |
| 278 | #define bfin_read_EVT3() bfin_readPTR(EVT3) |
| 279 | #define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) |
| 280 | #define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ |
| 281 | #define bfin_read_EVT4() bfin_readPTR(EVT4) |
| 282 | #define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) |
| 283 | #define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ |
| 284 | #define bfin_read_EVT5() bfin_readPTR(EVT5) |
| 285 | #define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) |
| 286 | #define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ |
| 287 | #define bfin_read_EVT6() bfin_readPTR(EVT6) |
| 288 | #define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) |
| 289 | #define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ |
| 290 | #define bfin_read_EVT7() bfin_readPTR(EVT7) |
| 291 | #define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) |
| 292 | #define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ |
| 293 | #define bfin_read_EVT8() bfin_readPTR(EVT8) |
| 294 | #define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) |
| 295 | #define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ |
| 296 | #define bfin_read_EVT9() bfin_readPTR(EVT9) |
| 297 | #define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) |
| 298 | #define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ |
| 299 | #define bfin_read_EVT10() bfin_readPTR(EVT10) |
| 300 | #define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) |
| 301 | #define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ |
| 302 | #define bfin_read_EVT11() bfin_readPTR(EVT11) |
| 303 | #define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) |
| 304 | #define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ |
| 305 | #define bfin_read_EVT12() bfin_readPTR(EVT12) |
| 306 | #define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) |
| 307 | #define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ |
| 308 | #define bfin_read_EVT13() bfin_readPTR(EVT13) |
| 309 | #define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) |
| 310 | #define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ |
| 311 | #define bfin_read_EVT14() bfin_readPTR(EVT14) |
| 312 | #define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) |
| 313 | #define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ |
| 314 | #define bfin_read_EVT15() bfin_readPTR(EVT15) |
| 315 | #define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) |
| 316 | #define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ |
| 317 | #define bfin_read_ILAT() bfin_read32(ILAT) |
| 318 | #define bfin_write_ILAT(val) bfin_write32(ILAT, val) |
| 319 | #define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ |
| 320 | #define bfin_read_IMASK() bfin_read32(IMASK) |
| 321 | #define bfin_write_IMASK(val) bfin_write32(IMASK, val) |
| 322 | #define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ |
| 323 | #define bfin_read_IPEND() bfin_read32(IPEND) |
| 324 | #define bfin_write_IPEND(val) bfin_write32(IPEND, val) |
| 325 | #define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ |
| 326 | #define bfin_read_IPRIO() bfin_read32(IPRIO) |
| 327 | #define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) |
| 328 | #define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ |
| 329 | #define bfin_read_TCNTL() bfin_read32(TCNTL) |
| 330 | #define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) |
| 331 | #define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ |
| 332 | #define bfin_read_TPERIOD() bfin_read32(TPERIOD) |
| 333 | #define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) |
| 334 | #define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ |
| 335 | #define bfin_read_TSCALE() bfin_read32(TSCALE) |
| 336 | #define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) |
| 337 | #define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ |
| 338 | #define bfin_read_TCOUNT() bfin_read32(TCOUNT) |
| 339 | #define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) |
| Mike Frysinger | d4d7730 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 340 | #define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ |
| 341 | #define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) |
| 342 | #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) |
| 343 | #define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ |
| 344 | #define bfin_read_USB_POWER() bfin_read16(USB_POWER) |
| 345 | #define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) |
| 346 | #define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ |
| 347 | #define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) |
| 348 | #define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) |
| 349 | #define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ |
| 350 | #define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) |
| 351 | #define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) |
| 352 | #define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ |
| 353 | #define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) |
| 354 | #define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) |
| 355 | #define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ |
| 356 | #define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) |
| 357 | #define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) |
| 358 | #define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ |
| 359 | #define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) |
| 360 | #define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) |
| 361 | #define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ |
| 362 | #define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) |
| 363 | #define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) |
| 364 | #define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ |
| 365 | #define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) |
| 366 | #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) |
| 367 | #define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ |
| 368 | #define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) |
| 369 | #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) |
| 370 | #define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ |
| 371 | #define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) |
| 372 | #define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) |
| 373 | #define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ |
| 374 | #define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) |
| 375 | #define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) |
| 376 | #define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ |
| 377 | #define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) |
| 378 | #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) |
| 379 | #define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ |
| 380 | #define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) |
| 381 | #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) |
| 382 | #define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ |
| 383 | #define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) |
| 384 | #define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) |
| 385 | #define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ |
| 386 | #define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) |
| 387 | #define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) |
| 388 | #define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ |
| 389 | #define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) |
| 390 | #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) |
| 391 | #define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ |
| 392 | #define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) |
| 393 | #define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) |
| 394 | #define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ |
| 395 | #define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) |
| 396 | #define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) |
| 397 | #define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ |
| 398 | #define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) |
| 399 | #define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) |
| 400 | #define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ |
| 401 | #define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) |
| 402 | #define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) |
| 403 | #define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ |
| 404 | #define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) |
| 405 | #define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) |
| 406 | #define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ |
| 407 | #define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) |
| 408 | #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) |
| 409 | #define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ |
| 410 | #define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) |
| 411 | #define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) |
| 412 | #define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ |
| 413 | #define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) |
| 414 | #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) |
| 415 | #define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ |
| 416 | #define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) |
| 417 | #define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) |
| 418 | #define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ |
| 419 | #define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) |
| 420 | #define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) |
| 421 | #define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ |
| 422 | #define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) |
| 423 | #define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) |
| 424 | #define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ |
| 425 | #define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) |
| 426 | #define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) |
| 427 | #define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ |
| 428 | #define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) |
| 429 | #define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) |
| 430 | #define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ |
| 431 | #define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) |
| 432 | #define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) |
| 433 | #define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ |
| 434 | #define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) |
| 435 | #define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) |
| 436 | #define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ |
| 437 | #define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) |
| 438 | #define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) |
| 439 | #define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ |
| 440 | #define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) |
| 441 | #define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) |
| 442 | #define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ |
| 443 | #define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) |
| 444 | #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) |
| 445 | #define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ |
| 446 | #define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) |
| 447 | #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) |
| 448 | #define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ |
| 449 | #define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) |
| 450 | #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) |
| 451 | #define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ |
| 452 | #define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) |
| 453 | #define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) |
| 454 | #define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ |
| 455 | #define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) |
| 456 | #define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) |
| 457 | #define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ |
| 458 | #define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) |
| 459 | #define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) |
| 460 | #define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ |
| 461 | #define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) |
| 462 | #define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) |
| 463 | #define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ |
| 464 | #define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) |
| 465 | #define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) |
| 466 | #define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ |
| 467 | #define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) |
| 468 | #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) |
| 469 | #define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ |
| 470 | #define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) |
| 471 | #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) |
| 472 | #define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ |
| 473 | #define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) |
| 474 | #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) |
| 475 | #define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ |
| 476 | #define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) |
| 477 | #define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) |
| 478 | #define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ |
| 479 | #define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) |
| 480 | #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) |
| 481 | #define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ |
| 482 | #define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) |
| 483 | #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) |
| 484 | #define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ |
| 485 | #define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) |
| 486 | #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) |
| 487 | #define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ |
| 488 | #define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) |
| 489 | #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) |
| 490 | #define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ |
| 491 | #define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) |
| 492 | #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) |
| 493 | #define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ |
| 494 | #define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) |
| 495 | #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) |
| 496 | #define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ |
| 497 | #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) |
| 498 | #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) |
| 499 | #define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ |
| 500 | #define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) |
| 501 | #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) |
| 502 | #define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ |
| 503 | #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) |
| 504 | #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) |
| 505 | #define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ |
| 506 | #define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) |
| 507 | #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) |
| 508 | #define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ |
| 509 | #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) |
| 510 | #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) |
| 511 | #define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ |
| 512 | #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) |
| 513 | #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) |
| 514 | #define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ |
| 515 | #define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) |
| 516 | #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) |
| 517 | #define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ |
| 518 | #define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) |
| 519 | #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) |
| 520 | #define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ |
| 521 | #define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) |
| 522 | #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) |
| 523 | #define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ |
| 524 | #define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) |
| 525 | #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) |
| 526 | #define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ |
| 527 | #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) |
| 528 | #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) |
| 529 | #define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ |
| 530 | #define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) |
| 531 | #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) |
| 532 | #define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ |
| 533 | #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) |
| 534 | #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) |
| 535 | #define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ |
| 536 | #define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) |
| 537 | #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) |
| 538 | #define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ |
| 539 | #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) |
| 540 | #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) |
| 541 | #define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ |
| 542 | #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) |
| 543 | #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) |
| 544 | #define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ |
| 545 | #define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) |
| 546 | #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) |
| 547 | #define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ |
| 548 | #define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) |
| 549 | #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) |
| 550 | #define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ |
| 551 | #define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) |
| 552 | #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) |
| 553 | #define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ |
| 554 | #define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) |
| 555 | #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) |
| 556 | #define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ |
| 557 | #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) |
| 558 | #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) |
| 559 | #define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ |
| 560 | #define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) |
| 561 | #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) |
| 562 | #define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ |
| 563 | #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) |
| 564 | #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) |
| 565 | #define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ |
| 566 | #define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) |
| 567 | #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) |
| 568 | #define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ |
| 569 | #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) |
| 570 | #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) |
| 571 | #define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ |
| 572 | #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) |
| 573 | #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) |
| 574 | #define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ |
| 575 | #define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) |
| 576 | #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) |
| 577 | #define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ |
| 578 | #define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) |
| 579 | #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) |
| 580 | #define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ |
| 581 | #define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) |
| 582 | #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) |
| 583 | #define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ |
| 584 | #define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) |
| 585 | #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) |
| 586 | #define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ |
| 587 | #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) |
| 588 | #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) |
| 589 | #define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ |
| 590 | #define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) |
| 591 | #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) |
| 592 | #define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ |
| 593 | #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) |
| 594 | #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) |
| 595 | #define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ |
| 596 | #define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) |
| 597 | #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) |
| 598 | #define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ |
| 599 | #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) |
| 600 | #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) |
| 601 | #define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ |
| 602 | #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) |
| 603 | #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) |
| 604 | #define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ |
| 605 | #define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) |
| 606 | #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) |
| 607 | #define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ |
| 608 | #define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) |
| 609 | #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) |
| 610 | #define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ |
| 611 | #define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) |
| 612 | #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) |
| 613 | #define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ |
| 614 | #define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) |
| 615 | #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) |
| 616 | #define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ |
| 617 | #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) |
| 618 | #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) |
| 619 | #define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ |
| 620 | #define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) |
| 621 | #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) |
| 622 | #define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ |
| 623 | #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) |
| 624 | #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) |
| 625 | #define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ |
| 626 | #define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) |
| 627 | #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) |
| 628 | #define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ |
| 629 | #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) |
| 630 | #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) |
| 631 | #define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ |
| 632 | #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) |
| 633 | #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) |
| 634 | #define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ |
| 635 | #define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) |
| 636 | #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) |
| 637 | #define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ |
| 638 | #define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) |
| 639 | #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) |
| 640 | #define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ |
| 641 | #define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) |
| 642 | #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) |
| 643 | #define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ |
| 644 | #define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) |
| 645 | #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) |
| 646 | #define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ |
| 647 | #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) |
| 648 | #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) |
| 649 | #define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ |
| 650 | #define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) |
| 651 | #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) |
| 652 | #define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ |
| 653 | #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) |
| 654 | #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) |
| 655 | #define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ |
| 656 | #define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) |
| 657 | #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) |
| 658 | #define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ |
| 659 | #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) |
| 660 | #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) |
| 661 | #define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */ |
| 662 | #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) |
| 663 | #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) |
| 664 | #define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ |
| 665 | #define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) |
| 666 | #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) |
| 667 | #define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ |
| 668 | #define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) |
| 669 | #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) |
| 670 | #define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ |
| 671 | #define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) |
| 672 | #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) |
| 673 | #define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ |
| 674 | #define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) |
| 675 | #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) |
| 676 | #define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ |
| 677 | #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) |
| 678 | #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) |
| 679 | #define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ |
| 680 | #define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) |
| 681 | #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) |
| 682 | #define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ |
| 683 | #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) |
| 684 | #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) |
| 685 | #define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ |
| 686 | #define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) |
| 687 | #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) |
| 688 | #define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ |
| 689 | #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) |
| 690 | #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) |
| 691 | #define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ |
| 692 | #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) |
| 693 | #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) |
| 694 | #define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ |
| 695 | #define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) |
| 696 | #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) |
| 697 | #define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ |
| 698 | #define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) |
| 699 | #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) |
| 700 | #define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ |
| 701 | #define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) |
| 702 | #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) |
| 703 | #define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ |
| 704 | #define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) |
| 705 | #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) |
| 706 | #define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ |
| 707 | #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) |
| 708 | #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) |
| 709 | #define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ |
| 710 | #define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) |
| 711 | #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) |
| 712 | #define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ |
| 713 | #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) |
| 714 | #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) |
| 715 | #define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ |
| 716 | #define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) |
| 717 | #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) |
| 718 | #define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ |
| 719 | #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) |
| 720 | #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) |
| 721 | #define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ |
| 722 | #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) |
| 723 | #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) |
| 724 | #define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ |
| 725 | #define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) |
| 726 | #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) |
| 727 | #define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ |
| 728 | #define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) |
| 729 | #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) |
| 730 | #define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ |
| 731 | #define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) |
| 732 | #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) |
| 733 | #define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ |
| 734 | #define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) |
| 735 | #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) |
| 736 | #define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ |
| 737 | #define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) |
| 738 | #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) |
| 739 | #define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ |
| 740 | #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) |
| 741 | #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) |
| 742 | #define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ |
| 743 | #define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) |
| 744 | #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) |
| 745 | #define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ |
| 746 | #define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) |
| 747 | #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) |
| 748 | #define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ |
| 749 | #define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) |
| 750 | #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) |
| 751 | #define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ |
| 752 | #define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) |
| 753 | #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) |
| 754 | #define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ |
| 755 | #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) |
| 756 | #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) |
| 757 | #define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ |
| 758 | #define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) |
| 759 | #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) |
| 760 | #define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ |
| 761 | #define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) |
| 762 | #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) |
| 763 | #define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ |
| 764 | #define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) |
| 765 | #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) |
| 766 | #define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ |
| 767 | #define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) |
| 768 | #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) |
| 769 | #define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ |
| 770 | #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) |
| 771 | #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) |
| 772 | #define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ |
| 773 | #define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) |
| 774 | #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) |
| 775 | #define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ |
| 776 | #define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) |
| 777 | #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) |
| 778 | #define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ |
| 779 | #define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) |
| 780 | #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) |
| 781 | #define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ |
| 782 | #define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) |
| 783 | #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) |
| 784 | #define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ |
| 785 | #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) |
| 786 | #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) |
| 787 | #define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ |
| 788 | #define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) |
| 789 | #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) |
| 790 | #define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ |
| 791 | #define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) |
| 792 | #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) |
| 793 | #define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ |
| 794 | #define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) |
| 795 | #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) |
| 796 | #define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ |
| 797 | #define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) |
| 798 | #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) |
| 799 | #define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ |
| 800 | #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) |
| 801 | #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) |
| 802 | #define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ |
| 803 | #define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) |
| 804 | #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) |
| 805 | #define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ |
| 806 | #define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) |
| 807 | #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) |
| 808 | #define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ |
| 809 | #define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) |
| 810 | #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) |
| 811 | #define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ |
| 812 | #define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) |
| 813 | #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) |
| 814 | #define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ |
| 815 | #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) |
| 816 | #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) |
| 817 | #define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ |
| 818 | #define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) |
| 819 | #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) |
| 820 | #define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ |
| 821 | #define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) |
| 822 | #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) |
| 823 | #define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ |
| 824 | #define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) |
| 825 | #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) |
| 826 | #define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ |
| 827 | #define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) |
| 828 | #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) |
| 829 | #define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ |
| 830 | #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) |
| 831 | #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) |
| 832 | #define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ |
| 833 | #define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) |
| 834 | #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) |
| 835 | #define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ |
| 836 | #define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) |
| 837 | #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) |
| 838 | #define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ |
| 839 | #define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) |
| 840 | #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) |
| 841 | #define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ |
| 842 | #define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) |
| 843 | #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) |
| 844 | #define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ |
| 845 | #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) |
| 846 | #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) |
| 847 | |
| 848 | #endif /* __BFIN_CDEF_ADSP_BF524_proc__ */ |