blob: ec7d34aa9e6eb1a9e57bd17e5f2375772e0e7ecf [file] [log] [blame]
wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
12 *
13 * Configuration settings for the WindRiver SBC8260 board.
14 * See http://www.windriver.com/products/html/sbc8260.html
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
wdenkfe8c2802002-11-03 00:38:21 +000038#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
39
wdenk78137c32003-09-15 18:00:00 +000040#undef CONFIG_LOGBUFFER /* External logbuffer support */
41
wdenkfe8c2802002-11-03 00:38:21 +000042/*****************************************************************************
43 *
44 * These settings must match the way _your_ board is set up
45 *
46 *****************************************************************************/
47
48/* What is the oscillator's (UX2) frequency in Hz? */
49#define CONFIG_8260_CLKIN 66666600
50
51/*-----------------------------------------------------------------------
52 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
53 *-----------------------------------------------------------------------
54 * What should MODCK_H be? It is dependent on the oscillator
55 * frequency, MODCK[1-3], and desired CPM and core frequencies.
56 * Here are some example values (all frequencies are in MHz):
57 *
58 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
59 * ------- ---------- --- --- ---- ----- ----- -----
60 * 0x1 0x5 33 100 133 Open Close Open
61 * 0x1 0x6 33 100 166 Open Open Close
62 * 0x1 0x7 33 100 200 Open Open Open
63 *
64 * 0x2 0x2 33 133 133 Close Open Close
65 * 0x2 0x3 33 133 166 Close Open Open
66 * 0x2 0x4 33 133 200 Open Close Close
67 * 0x2 0x5 33 133 233 Open Close Open
68 * 0x2 0x6 33 133 266 Open Open Close
69 *
70 * 0x5 0x5 66 133 133 Open Close Open
71 * 0x5 0x6 66 133 166 Open Open Close
72 * 0x5 0x7 66 133 200 Open Open Open
73 * 0x6 0x0 66 133 233 Close Close Close
74 * 0x6 0x1 66 133 266 Close Close Open
75 * 0x6 0x2 66 133 300 Close Open Close
76 */
77#define CFG_SBC_MODCK_H 0x05
78
79/* Define this if you want to boot from 0x00000100. If you don't define
80 * this, you will need to program the bootloader to 0xfff00000, and
81 * get the hardware reset config words at 0xfe000000. The simplest
82 * way to do that is to program the bootloader at both addresses.
83 * It is suggested that you just let U-Boot live at 0x00000000.
84 */
85#define CFG_SBC_BOOT_LOW 1
86
87/* What should the base address of the main FLASH be and how big is
88 * it (in MBytes)? This must contain TEXT_BASE from board/sacsng/config.mk
89 * The main FLASH is whichever is connected to *CS0.
90 */
91#define CFG_FLASH0_BASE 0x40000000
92#define CFG_FLASH0_SIZE 2
93
94/* What should the base address of the secondary FLASH be and how big
95 * is it (in Mbytes)? The secondary FLASH is whichever is connected
96 * to *CS6.
97 */
98#define CFG_FLASH1_BASE 0x60000000
99#define CFG_FLASH1_SIZE 2
100
101/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
102 */
103#define CONFIG_VERY_BIG_RAM 1
104
105/* What should be the base address of SDRAM DIMM and how big is
106 * it (in Mbytes)? This will normally auto-configure via the SPD.
107*/
108#define CFG_SDRAM0_BASE 0x00000000
109#define CFG_SDRAM0_SIZE 64
110
111/*
112 * Memory map example with 64 MB DIMM:
113 *
114 * 0x0000 0000 Exception Vector code, 8k
115 * :
116 * 0x0000 1FFF
117 * 0x0000 2000 Free for Application Use
118 * :
119 * :
120 *
121 * :
122 * :
123 * 0x03F5 FF30 Monitor Stack (Growing downward)
124 * Monitor Stack Buffer (0x80)
125 * 0x03F5 FFB0 Board Info Data
126 * 0x03F6 0000 Malloc Arena
127 * : CFG_ENV_SECT_SIZE, 16k
128 * : CFG_MALLOC_LEN, 128k
129 * 0x03FC 0000 RAM Copy of Monitor Code
130 * : CFG_MONITOR_LEN, 256k
131 * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
132 */
133
134#define CONFIG_POST (CFG_POST_MEMORY | \
135 CFG_POST_CPU)
136
137
138/*
139 * select serial console configuration
140 *
141 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
142 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
143 * for SCC).
144 *
145 * if CONFIG_CONS_NONE is defined, then the serial console routines must
146 * defined elsewhere.
147 */
148#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
149#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
150#undef CONFIG_CONS_NONE /* define if console on neither */
151#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
152
153/*
154 * select ethernet configuration
155 *
156 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
157 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
158 * for FCC)
159 *
160 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500161 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkfe8c2802002-11-03 00:38:21 +0000162 */
163
164#undef CONFIG_ETHER_ON_SCC
165#define CONFIG_ETHER_ON_FCC
166#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
167
168#ifdef CONFIG_ETHER_ON_SCC
169#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
170#endif /* CONFIG_ETHER_ON_SCC */
171
172#ifdef CONFIG_ETHER_ON_FCC
173#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
wdenk78137c32003-09-15 18:00:00 +0000174#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
wdenkfe8c2802002-11-03 00:38:21 +0000175#define CONFIG_MII /* MII PHY management */
176#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
177/*
178 * Port pins used for bit-banged MII communictions (if applicable).
179 */
180
181#define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */
182#define MDIO_ACTIVE (iop->pdir |= 0x40000000)
183#define MDIO_TRISTATE (iop->pdir &= ~0x40000000)
184#define MDIO_READ ((iop->pdat & 0x40000000) != 0)
185
186#define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \
187 else iop->pdat &= ~0x40000000
188
189#define MDC(bit) if(bit) iop->pdat |= 0x80000000; \
190 else iop->pdat &= ~0x80000000
191
192#define MIIDELAY udelay(50)
193#endif /* CONFIG_ETHER_ON_FCC */
194
195#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
196
197/*
198 * - RX clk is CLK11
199 * - TX clk is CLK12
200 */
201# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
202
203#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
204
205/*
206 * - Rx-CLK is CLK13
207 * - Tx-CLK is CLK14
208 * - Select bus for bd/buffers (see 28-13)
209 * - Enable Full Duplex in FSMR
210 */
211# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
212# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
213# define CFG_CPMFCR_RAMTYPE 0
214# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
215
216#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
217
218#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */
219
220/*
221 * Configure for RAM tests.
222 */
223#undef CFG_DRAM_TEST /* calls other tests in board.c */
224
225
226/*
227 * Status LED for power up status feedback.
228 */
229#define CONFIG_STATUS_LED 1 /* Status LED enabled */
230
231#define STATUS_LED_PAR im_ioport.iop_ppara
232#define STATUS_LED_DIR im_ioport.iop_pdira
233#define STATUS_LED_ODR im_ioport.iop_podra
234#define STATUS_LED_DAT im_ioport.iop_pdata
235
236#define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */
237#define STATUS_LED_PERIOD (CFG_HZ)
238#define STATUS_LED_STATE STATUS_LED_OFF
239#define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */
240#define STATUS_LED_PERIOD1 (CFG_HZ)
241#define STATUS_LED_STATE1 STATUS_LED_OFF
242#define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */
243#define STATUS_LED_PERIOD2 (CFG_HZ/2)
244#define STATUS_LED_STATE2 STATUS_LED_ON
245
246#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
247
248#define STATUS_LED_YELLOW 0
249#define STATUS_LED_GREEN 1
250#define STATUS_LED_RED 2
251#define STATUS_LED_BOOT 1
252
253
254/*
wdenk1d0350e2002-11-11 21:14:20 +0000255 * Select SPI support configuration
wdenkfe8c2802002-11-03 00:38:21 +0000256 */
wdenk1d0350e2002-11-11 21:14:20 +0000257#define CONFIG_SOFT_SPI /* Enable SPI driver */
258#define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */
wdenk8bde7f72003-06-27 21:31:46 +0000259#undef DEBUG_SPI /* Disable SPI debugging */
260
wdenkfe8c2802002-11-03 00:38:21 +0000261/*
262 * Software (bit-bang) SPI driver configuration
263 */
264#ifdef CONFIG_SOFT_SPI
265
266/*
267 * Software (bit-bang) SPI driver configuration
268 */
269#define I2C_SCLK 0x00002000 /* PD 18: Shift clock */
270#define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */
271#define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */
272
273#undef SPI_INIT /* no port initialization needed */
274#define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
275#define SPI_SDA(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \
wdenk8bde7f72003-06-27 21:31:46 +0000276 else immr->im_ioport.iop_pdatd &= ~I2C_MOSI
wdenkfe8c2802002-11-03 00:38:21 +0000277#define SPI_SCL(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \
wdenk8bde7f72003-06-27 21:31:46 +0000278 else immr->im_ioport.iop_pdatd &= ~I2C_SCLK
wdenk1d0350e2002-11-11 21:14:20 +0000279#define SPI_DELAY /* No delay is needed */
wdenkfe8c2802002-11-03 00:38:21 +0000280#endif /* CONFIG_SOFT_SPI */
281
282
283/*
284 * select I2C support configuration
285 *
286 * Supported configurations are {none, software, hardware} drivers.
287 * If the software driver is chosen, there are some additional
288 * configuration items that the driver uses to drive the port pins.
289 */
290#undef CONFIG_HARD_I2C /* I2C with hardware support */
291#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
292#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
293#define CFG_I2C_SLAVE 0x7F
294
295/*
296 * Software (bit-bang) I2C driver configuration
297 */
298#ifdef CONFIG_SOFT_I2C
299#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
300#define I2C_ACTIVE (iop->pdir |= 0x00010000)
301#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
302#define I2C_READ ((iop->pdat & 0x00010000) != 0)
303#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
304 else iop->pdat &= ~0x00010000
305#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
306 else iop->pdat &= ~0x00020000
307#define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */
308#endif /* CONFIG_SOFT_I2C */
309
310/* Define this to reserve an entire FLASH sector for
311 * environment variables. Otherwise, the environment will be
312 * put in the same sector as U-Boot, and changing variables
313 * will erase U-Boot temporarily
314 */
315#define CFG_ENV_IN_OWN_SECT 1
316
317/* Define this to contain any number of null terminated strings that
318 * will be part of the default enviroment compiled into the boot image.
319 */
320#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk78137c32003-09-15 18:00:00 +0000321"quiet=0\0" \
322"serverip=192.168.123.205\0" \
wdenkfe8c2802002-11-03 00:38:21 +0000323"ipaddr=192.168.123.203\0" \
324"checkhostname=VR8500\0" \
325"reprog="\
wdenk78137c32003-09-15 18:00:00 +0000326 "bootp; " \
wdenkfe8c2802002-11-03 00:38:21 +0000327 "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
328 "protect off 60000000 6003FFFF; " \
329 "erase 60000000 6003FFFF; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100330 "cp.b 140000 60000000 ${filesize}; " \
wdenkfe8c2802002-11-03 00:38:21 +0000331 "protect on 60000000 6003FFFF\0" \
332"copyenv="\
333 "protect off 60040000 6004FFFF; " \
334 "erase 60040000 6004FFFF; " \
335 "cp.b 40040000 60040000 10000; " \
336 "protect on 60040000 6004FFFF\0" \
337"copyprog="\
338 "protect off 60000000 6003FFFF; " \
339 "erase 60000000 6003FFFF; " \
340 "cp.b 40000000 60000000 40000; " \
341 "protect on 60000000 6003FFFF\0" \
342"zapenv="\
343 "protect off 40040000 4004FFFF; " \
344 "erase 40040000 4004FFFF; " \
345 "protect on 40040000 4004FFFF\0" \
346"zapotherenv="\
347 "protect off 60040000 6004FFFF; " \
348 "erase 60040000 6004FFFF; " \
349 "protect on 60040000 6004FFFF\0" \
350"root-on-initrd="\
351 "setenv bootcmd "\
352 "version\\;" \
353 "echo\\;" \
354 "bootp\\;" \
355 "setenv bootargs root=/dev/ram0 rw quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100356 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000357 "run boot-hook\\;" \
358 "bootm\0" \
359"root-on-initrd-debug="\
360 "setenv bootcmd "\
361 "version\\;" \
362 "echo\\;" \
363 "bootp\\;" \
364 "setenv bootargs root=/dev/ram0 rw debug " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100365 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000366 "run debug-hook\\;" \
367 "run boot-hook\\;" \
368 "bootm\0" \
369"root-on-nfs="\
370 "setenv bootcmd "\
371 "version\\;" \
372 "echo\\;" \
373 "bootp\\;" \
374 "setenv bootargs root=/dev/nfs rw quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100375 "nfsroot=\\${serverip}:\\${rootpath} " \
376 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000377 "run boot-hook\\;" \
378 "bootm\0" \
379"root-on-nfs-debug="\
380 "setenv bootcmd "\
381 "version\\;" \
382 "echo\\;" \
383 "bootp\\;" \
384 "setenv bootargs root=/dev/nfs rw debug " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100385 "nfsroot=\\${serverip}:\\${rootpath} " \
386 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000387 "run debug-hook\\;" \
388 "run boot-hook\\;" \
389 "bootm\0" \
390"debug-checkout="\
391 "setenv checkhostname;" \
392 "setenv ethaddr 00:09:70:00:00:01;" \
393 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100394 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
395 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000396 "run debug-hook;" \
397 "run boot-hook;" \
398 "bootm\0" \
399"debug-hook="\
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100400 "echo ipaddr ${ipaddr};" \
401 "echo serverip ${serverip};" \
402 "echo gatewayip ${gatewayip};" \
403 "echo netmask ${netmask};" \
404 "echo hostname ${hostname}\0" \
wdenkfe8c2802002-11-03 00:38:21 +0000405"ana=run adc ; run dac\0" \
406"adc=run adc-12 ; run adc-34\0" \
407"adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \
408"adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \
409"dac=echo ### DAC ; imd.b 11 81 5\0" \
wdenk78137c32003-09-15 18:00:00 +0000410"boot-hook=echo\0"
wdenkfe8c2802002-11-03 00:38:21 +0000411
412/* What should the console's baud rate be? */
413#define CONFIG_BAUDRATE 9600
414
415/* Ethernet MAC address */
416#define CONFIG_ETHADDR 00:09:70:00:00:00
417
418/* The default Ethernet MAC address can be overwritten just once */
419#ifdef CONFIG_ETHADDR
420#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
421#endif
422
423/*
424 * Define this to do some miscellaneous board-specific initialization.
425 */
426#define CONFIG_MISC_INIT_R
427
428/* Set to a positive value to delay for running BOOTCOMMAND */
429#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
430
431/* Be selective on what keys can delay or stop the autoboot process
432 * To stop use: " "
433 */
434#define CONFIG_AUTOBOOT_KEYED
435#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n"
436#define CONFIG_AUTOBOOT_STOP_STR " "
437#undef CONFIG_AUTOBOOT_DELAY_STR
438#define CONFIG_ZERO_BOOTDELAY_CHECK
439#define DEBUG_BOOTKEYS 0
440
441/* Define a command string that is automatically executed when no character
442 * is read on the console interface withing "Boot Delay" after reset.
443 */
wdenkb79a11c2004-03-25 15:14:43 +0000444#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
445#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
wdenkfe8c2802002-11-03 00:38:21 +0000446
wdenk42dfe7a2004-03-14 22:25:36 +0000447#ifdef CONFIG_BOOT_ROOT_INITRD
wdenkfe8c2802002-11-03 00:38:21 +0000448#define CONFIG_BOOTCOMMAND \
449 "version;" \
450 "echo;" \
451 "bootp;" \
452 "setenv bootargs root=/dev/ram0 rw quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100453 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000454 "run boot-hook;" \
455 "bootm"
456#endif /* CONFIG_BOOT_ROOT_INITRD */
457
wdenk42dfe7a2004-03-14 22:25:36 +0000458#ifdef CONFIG_BOOT_ROOT_NFS
wdenkfe8c2802002-11-03 00:38:21 +0000459#define CONFIG_BOOTCOMMAND \
460 "version;" \
461 "echo;" \
462 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100463 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
464 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000465 "run boot-hook;" \
466 "bootm"
467#endif /* CONFIG_BOOT_ROOT_NFS */
468
469#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */
470
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500471/*
472 * BOOTP options
wdenkfe8c2802002-11-03 00:38:21 +0000473 */
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500474#define CONFIG_BOOTP_SUBNETMASK
475#define CONFIG_BOOTP_GATEWAY
476#define CONFIG_BOOTP_HOSTNAME
477#define CONFIG_BOOTP_BOOTPATH
478#define CONFIG_BOOTP_BOOTFILESIZE
479#define CONFIG_BOOTP_DNS
480#define CONFIG_BOOTP_DNS2
481#define CONFIG_BOOTP_SEND_HOSTNAME
482
wdenkfe8c2802002-11-03 00:38:21 +0000483
484/* undef this to save memory */
485#define CFG_LONGHELP
486
487/* Monitor Command Prompt */
488#define CFG_PROMPT "=> "
489
490#undef CFG_HUSH_PARSER
491#ifdef CFG_HUSH_PARSER
492#define CFG_PROMPT_HUSH_PS2 "> "
493#endif
494
wdenk1d0350e2002-11-11 21:14:20 +0000495/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
496 * of an image is printed by image commands like bootm or iminfo.
497 */
498#define CONFIG_TIMESTAMP
499
wdenk42d1f032003-10-15 23:53:47 +0000500/* If this variable is defined, an environment variable named "ver"
wdenk78137c32003-09-15 18:00:00 +0000501 * is created by U-Boot showing the U-Boot version.
502 */
503#define CONFIG_VERSION_VARIABLE
504
Jon Loeliger46da1e92007-07-04 22:33:30 -0500505
506/*
507 * Command line configuration.
508 */
509#include <config_cmd_default.h>
510
511#define CONFIG_CMD_ELF
512#define CONFIG_CMD_ASKENV
513#define CONFIG_CMD_I2C
514#define CONFIG_CMD_SPI
515#define CONFIG_CMD_SDRAM
516#define CONFIG_CMD_REGINFO
517#define CONFIG_CMD_IMMAP
518#define CONFIG_CMD_IRQ
519#define CONFIG_CMD_PING
520
521#undef CONFIG_CMD_KGDB
522
wdenkfe8c2802002-11-03 00:38:21 +0000523#ifdef CONFIG_ETHER_ON_FCC
Jon Loeliger46da1e92007-07-04 22:33:30 -0500524#define CONFIG_CMD_MII
525#endif
526
wdenkfe8c2802002-11-03 00:38:21 +0000527
528/* Where do the internal registers live? */
529#define CFG_IMMR 0xF0000000
530
wdenk78137c32003-09-15 18:00:00 +0000531#undef CONFIG_WATCHDOG /* disable the watchdog */
532
wdenkfe8c2802002-11-03 00:38:21 +0000533/*****************************************************************************
534 *
535 * You should not have to modify any of the following settings
536 *
537 *****************************************************************************/
538
539#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
540#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
541#define CONFIG_SACSng 1 /* munged for the SACSng */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500542#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkfe8c2802002-11-03 00:38:21 +0000543
wdenkfe8c2802002-11-03 00:38:21 +0000544/*
545 * Miscellaneous configurable options
546 */
wdenk78137c32003-09-15 18:00:00 +0000547#define CFG_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */
wdenk42d1f032003-10-15 23:53:47 +0000548 /* in the bootm command. */
wdenk78137c32003-09-15 18:00:00 +0000549#define CFG_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */
wdenk42d1f032003-10-15 23:53:47 +0000550 /* "## <message>" from the bootm cmd */
wdenk78137c32003-09-15 18:00:00 +0000551#define CFG_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */
wdenk42d1f032003-10-15 23:53:47 +0000552 /* defined, then the hostname param */
553 /* validated against checkhostname. */
wdenk78137c32003-09-15 18:00:00 +0000554#define CFG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
555#define CFG_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */
wdenk42d1f032003-10-15 23:53:47 +0000556 /* (limited to maximum of 1024 msec) */
wdenk78137c32003-09-15 18:00:00 +0000557#define CFG_CHK_FOR_ABORT_AT_LEAST_ONCE 1
wdenk42d1f032003-10-15 23:53:47 +0000558 /* Check for abort key presses */
559 /* at least once in dependent of the */
560 /* CONFIG_BOOTDELAY value. */
wdenk78137c32003-09-15 18:00:00 +0000561#define CFG_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */
562#define CFG_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */
wdenk42d1f032003-10-15 23:53:47 +0000563 /* state to the fault LED. */
wdenk78137c32003-09-15 18:00:00 +0000564#define CFG_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */
wdenk42d1f032003-10-15 23:53:47 +0000565 /* the Ethernet link state. */
wdenk78137c32003-09-15 18:00:00 +0000566#define CFG_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */
wdenk42d1f032003-10-15 23:53:47 +0000567 /* until the TFTP is successful. */
wdenk78137c32003-09-15 18:00:00 +0000568#define CFG_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */
wdenk42d1f032003-10-15 23:53:47 +0000569 /* turn off the STATUS LEDs. */
wdenk78137c32003-09-15 18:00:00 +0000570#define CFG_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */
wdenk42d1f032003-10-15 23:53:47 +0000571 /* incoming data. */
wdenk78137c32003-09-15 18:00:00 +0000572#define CFG_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */
wdenk42d1f032003-10-15 23:53:47 +0000573 /* to signify that tftp is moving. */
wdenk78137c32003-09-15 18:00:00 +0000574#define CFG_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */
wdenk42d1f032003-10-15 23:53:47 +0000575 /* flash the status LED. */
wdenk78137c32003-09-15 18:00:00 +0000576#define CFG_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */
wdenk42d1f032003-10-15 23:53:47 +0000577 /* during the tftp file transfer. */
wdenk78137c32003-09-15 18:00:00 +0000578#define CFG_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */
wdenk42d1f032003-10-15 23:53:47 +0000579 /* '#'s from the tftp command. */
wdenk78137c32003-09-15 18:00:00 +0000580#define CFG_TFTP_STATUS_QUIET 1 /* Suppress the status displays */
wdenk42d1f032003-10-15 23:53:47 +0000581 /* issued during the tftp command. */
wdenk78137c32003-09-15 18:00:00 +0000582#define CFG_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */
583 /* before it gives up. */
584
Jon Loeliger46da1e92007-07-04 22:33:30 -0500585#if defined(CONFIG_CMD_KGDB)
wdenkfe8c2802002-11-03 00:38:21 +0000586# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
587#else
588# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
589#endif
590
591/* Print Buffer Size */
592#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
593
594#define CFG_MAXARGS 32 /* max number of command args */
595
596#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
597
598#define CFG_LOAD_ADDR 0x400000 /* default load address */
599#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
600
wdenk1d0350e2002-11-11 21:14:20 +0000601#define CFG_ALT_MEMTEST /* Select full-featured memory test */
wdenkfe8c2802002-11-03 00:38:21 +0000602#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
603 /* the exception vector table */
604 /* to the end of the DRAM */
605 /* less monitor and malloc area */
606#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
607#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
608 + CFG_MALLOC_LEN \
609 + CFG_ENV_SECT_SIZE \
610 + CFG_STACK_USAGE )
611
612#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
613 - CFG_MEM_END_USAGE )
614
615/* valid baudrates */
616#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
617
618/*
619 * Low Level Configuration Settings
620 * (address mappings, register initial values, etc.)
621 * You should know what you are doing if you make changes here.
622 */
623
624#define CFG_FLASH_BASE CFG_FLASH0_BASE
625#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
626#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
627#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE
628
629/*-----------------------------------------------------------------------
630 * Hard Reset Configuration Words
631 */
632#if defined(CFG_SBC_BOOT_LOW)
633# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
634#else
635# define CFG_SBC_HRCW_BOOT_FLAGS (0)
636#endif /* defined(CFG_SBC_BOOT_LOW) */
637
638/* get the HRCW ISB field from CFG_IMMR */
639#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
640 ((CFG_IMMR & 0x01000000) >> 7) | \
641 ((CFG_IMMR & 0x00100000) >> 4) )
642
643#define CFG_HRCW_MASTER ( HRCW_BPS10 | \
644 HRCW_DPPC11 | \
645 CFG_SBC_HRCW_IMMR | \
646 HRCW_MMR00 | \
647 HRCW_LBPC11 | \
648 HRCW_APPC10 | \
649 HRCW_CS10PC00 | \
650 (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \
651 CFG_SBC_HRCW_BOOT_FLAGS )
652
653/* no slaves */
654#define CFG_HRCW_SLAVE1 0
655#define CFG_HRCW_SLAVE2 0
656#define CFG_HRCW_SLAVE3 0
657#define CFG_HRCW_SLAVE4 0
658#define CFG_HRCW_SLAVE5 0
659#define CFG_HRCW_SLAVE6 0
660#define CFG_HRCW_SLAVE7 0
661
662/*-----------------------------------------------------------------------
663 * Definitions for initial stack pointer and data area (in DPRAM)
664 */
665#define CFG_INIT_RAM_ADDR CFG_IMMR
666#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
667#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
668#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
669#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
670
671/*-----------------------------------------------------------------------
672 * Start addresses for the final memory configuration
673 * (Set up by the startup code)
674 * Please note that CFG_SDRAM_BASE _must_ start at 0
675 * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
676 */
677#define CFG_MONITOR_BASE CFG_FLASH0_BASE
678
679#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
680# define CFG_RAMBOOT
681#endif
682
683#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
684#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
685
686/*
687 * For booting Linux, the board info and command line data
688 * have to be in the first 8 MB of memory, since this is
689 * the maximum mapped by the Linux kernel during initialization.
690 */
691#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
692
693/*-----------------------------------------------------------------------
694 * FLASH and environment organization
695 */
696
697#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
698#undef CFG_FLASH_PROTECTION /* use hardware protection */
699#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
700#define CFG_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */
701
702#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
703#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
704
705#ifndef CFG_RAMBOOT
706# define CFG_ENV_IS_IN_FLASH 1
707
708# ifdef CFG_ENV_IN_OWN_SECT
709# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
710# define CFG_ENV_SECT_SIZE 0x10000
711# else
712# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
713# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
714# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
715# endif /* CFG_ENV_IN_OWN_SECT */
716
717#else
718# define CFG_ENV_IS_IN_NVRAM 1
719# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
720# define CFG_ENV_SIZE 0x200
721#endif /* CFG_RAMBOOT */
722
723/*-----------------------------------------------------------------------
724 * Cache Configuration
725 */
726#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
727
Jon Loeliger46da1e92007-07-04 22:33:30 -0500728#if defined(CONFIG_CMD_KGDB)
wdenkfe8c2802002-11-03 00:38:21 +0000729# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
730#endif
731
732/*-----------------------------------------------------------------------
733 * HIDx - Hardware Implementation-dependent Registers 2-11
734 *-----------------------------------------------------------------------
735 * HID0 also contains cache control - initially enable both caches and
736 * invalidate contents, then the final state leaves only the instruction
737 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
738 * but Soft reset does not.
739 *
740 * HID1 has only read-only information - nothing to set.
741 */
742#define CFG_HID0_INIT (HID0_ICE |\
743 HID0_DCE |\
744 HID0_ICFI |\
745 HID0_DCI |\
746 HID0_IFEM |\
747 HID0_ABE)
748
749#define CFG_HID0_FINAL (HID0_ICE |\
750 HID0_IFEM |\
751 HID0_ABE |\
752 HID0_EMCP)
753#define CFG_HID2 0
754
755/*-----------------------------------------------------------------------
756 * RMR - Reset Mode Register
757 *-----------------------------------------------------------------------
758 */
759#define CFG_RMR 0
760
761/*-----------------------------------------------------------------------
762 * BCR - Bus Configuration 4-25
763 *-----------------------------------------------------------------------
764 */
765#define CFG_BCR (BCR_ETM)
766
767/*-----------------------------------------------------------------------
768 * SIUMCR - SIU Module Configuration 4-31
769 *-----------------------------------------------------------------------
770 */
771
772#define CFG_SIUMCR (SIUMCR_DPPC11 |\
773 SIUMCR_L2CPC00 |\
774 SIUMCR_APPC10 |\
775 SIUMCR_MMR00)
776
777
778/*-----------------------------------------------------------------------
779 * SYPCR - System Protection Control 11-9
780 * SYPCR can only be written once after reset!
781 *-----------------------------------------------------------------------
782 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
783 */
wdenk78137c32003-09-15 18:00:00 +0000784#if defined(CONFIG_WATCHDOG)
785#define CFG_SYPCR (SYPCR_SWTC |\
786 SYPCR_BMT |\
787 SYPCR_PBME |\
788 SYPCR_LBME |\
789 SYPCR_SWRI |\
790 SYPCR_SWP |\
wdenk42d1f032003-10-15 23:53:47 +0000791 SYPCR_SWE)
wdenk78137c32003-09-15 18:00:00 +0000792#else
wdenkfe8c2802002-11-03 00:38:21 +0000793#define CFG_SYPCR (SYPCR_SWTC |\
794 SYPCR_BMT |\
795 SYPCR_PBME |\
796 SYPCR_LBME |\
797 SYPCR_SWRI |\
798 SYPCR_SWP)
wdenk78137c32003-09-15 18:00:00 +0000799#endif /* CONFIG_WATCHDOG */
wdenkfe8c2802002-11-03 00:38:21 +0000800
801/*-----------------------------------------------------------------------
802 * TMCNTSC - Time Counter Status and Control 4-40
803 *-----------------------------------------------------------------------
804 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
805 * and enable Time Counter
806 */
807#define CFG_TMCNTSC (TMCNTSC_SEC |\
808 TMCNTSC_ALR |\
809 TMCNTSC_TCF |\
810 TMCNTSC_TCE)
811
812/*-----------------------------------------------------------------------
813 * PISCR - Periodic Interrupt Status and Control 4-42
814 *-----------------------------------------------------------------------
815 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
816 * Periodic timer
817 */
818#define CFG_PISCR (PISCR_PS |\
819 PISCR_PTF |\
820 PISCR_PTE)
821
822/*-----------------------------------------------------------------------
823 * SCCR - System Clock Control 9-8
824 *-----------------------------------------------------------------------
825 */
826#define CFG_SCCR 0
827
828/*-----------------------------------------------------------------------
829 * RCCR - RISC Controller Configuration 13-7
830 *-----------------------------------------------------------------------
831 */
832#define CFG_RCCR 0
833
834/*
835 * Initialize Memory Controller:
836 *
837 * Bank Bus Machine PortSz Device
838 * ---- --- ------- ------ ------
839 * 0 60x GPCM 16 bit FLASH (primary flash - 2MB)
840 * 1 60x GPCM -- bit (Unused)
841 * 2 60x SDRAM 64 bit SDRAM (DIMM)
842 * 3 60x SDRAM 64 bit SDRAM (DIMM)
843 * 4 60x GPCM -- bit (Unused)
844 * 5 60x GPCM -- bit (Unused)
845 * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB)
846 */
847
848/*-----------------------------------------------------------------------
849 * BR0,BR1 - Base Register
850 * Ref: Section 10.3.1 on page 10-14
851 * OR0,OR1 - Option Register
852 * Ref: Section 10.3.2 on page 10-18
853 *-----------------------------------------------------------------------
854 */
855
856/* Bank 0 - Primary FLASH
857 */
858
859/* BR0 is configured as follows:
860 *
861 * - Base address of 0x40000000
862 * - 16 bit port size
863 * - Data errors checking is disabled
864 * - Read and write access
865 * - GPCM 60x bus
866 * - Access are handled by the memory controller according to MSEL
867 * - Not used for atomic operations
868 * - No data pipelining is done
869 * - Valid
870 */
871#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
872 BRx_PS_16 |\
873 BRx_MS_GPCM_P |\
874 BRx_V)
875
876/* OR0 is configured as follows:
877 *
878 * - 4 MB
879 * - *BCTL0 is asserted upon access to the current memory bank
880 * - *CW / *WE are negated a quarter of a clock earlier
881 * - *CS is output at the same time as the address lines
882 * - Uses a clock cycle length of 5
883 * - *PSDVAL is generated internally by the memory controller
884 * unless *GTA is asserted earlier externally.
885 * - Relaxed timing is generated by the GPCM for accesses
886 * initiated to this memory region.
887 * - One idle clock is inserted between a read access from the
888 * current bank and the next access.
889 */
890#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
891 ORxG_CSNT |\
892 ORxG_ACS_DIV1 |\
893 ORxG_SCY_5_CLK |\
894 ORxG_TRLX |\
895 ORxG_EHTR)
896
897/*-----------------------------------------------------------------------
898 * BR2,BR3 - Base Register
899 * Ref: Section 10.3.1 on page 10-14
900 * OR2,OR3 - Option Register
901 * Ref: Section 10.3.2 on page 10-16
902 *-----------------------------------------------------------------------
903 */
904
905/* Bank 2,3 - SDRAM DIMM
906 */
907
908/* The BR2 is configured as follows:
909 *
910 * - Base address of 0x00000000
911 * - 64 bit port size (60x bus only)
912 * - Data errors checking is disabled
913 * - Read and write access
914 * - SDRAM 60x bus
915 * - Access are handled by the memory controller according to MSEL
916 * - Not used for atomic operations
917 * - No data pipelining is done
918 * - Valid
919 */
920#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
921 BRx_PS_64 |\
922 BRx_MS_SDRAM_P |\
923 BRx_V)
924
925#define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
926 BRx_PS_64 |\
927 BRx_MS_SDRAM_P |\
928 BRx_V)
929
930/* With a 64 MB DIMM, the OR2 is configured as follows:
931 *
932 * - 64 MB
933 * - 4 internal banks per device
934 * - Row start address bit is A8 with PSDMR[PBI] = 0
935 * - 12 row address lines
936 * - Back-to-back page mode
937 * - Internal bank interleaving within save device enabled
938 */
939#if (CFG_SDRAM0_SIZE == 64)
940#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
941 ORxS_BPD_4 |\
942 ORxS_ROWST_PBI0_A8 |\
943 ORxS_NUMR_12)
944#else
945#error "INVALID SDRAM CONFIGURATION"
946#endif
947
948/*-----------------------------------------------------------------------
949 * PSDMR - 60x Bus SDRAM Mode Register
950 * Ref: Section 10.3.3 on page 10-21
951 *-----------------------------------------------------------------------
952 */
953
954/* Address that the DIMM SPD memory lives at.
955 */
956#define SDRAM_SPD_ADDR 0x50
957
958#if (CFG_SDRAM0_SIZE == 64)
959/* With a 64 MB DIMM, the PSDMR is configured as follows:
960 *
961 * - Bank Based Interleaving,
962 * - Refresh Enable,
963 * - Address Multiplexing where A5 is output on A14 pin
964 * (A6 on A15, and so on),
965 * - use address pins A14-A16 as bank select,
966 * - A9 is output on SDA10 during an ACTIVATE command,
967 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
968 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
969 * is 3 clocks,
970 * - earliest timing for READ/WRITE command after ACTIVATE command is
971 * 2 clocks,
972 * - earliest timing for PRECHARGE after last data was read is 1 clock,
973 * - earliest timing for PRECHARGE after last data was written is 1 clock,
974 * - CAS Latency is 2.
975 */
976#define CFG_PSDMR (PSDMR_RFEN |\
977 PSDMR_SDAM_A14_IS_A5 |\
978 PSDMR_BSMA_A14_A16 |\
979 PSDMR_SDA10_PBI0_A9 |\
980 PSDMR_RFRC_7_CLK |\
981 PSDMR_PRETOACT_3W |\
982 PSDMR_ACTTORW_2W |\
983 PSDMR_LDOTOPRE_1C |\
984 PSDMR_WRC_1C |\
985 PSDMR_CL_2)
986#else
987#error "INVALID SDRAM CONFIGURATION"
988#endif
989
990/*
991 * Shoot for approximately 1MHz on the prescaler.
992 */
993#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
994#define CFG_MPTPR MPTPR_PTP_DIV64
995#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
996#define CFG_MPTPR MPTPR_PTP_DIV32
997#else
998#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
999#define CFG_MPTPR MPTPR_PTP_DIV32
1000#endif
1001#define CFG_PSRT 14
1002
1003
1004/*-----------------------------------------------------------------------
1005 * BR6 - Base Register
1006 * Ref: Section 10.3.1 on page 10-14
1007 * OR6 - Option Register
1008 * Ref: Section 10.3.2 on page 10-18
1009 *-----------------------------------------------------------------------
1010 */
1011
1012/* Bank 6 - Secondary FLASH
1013 *
1014 * The secondary FLASH is connected to *CS6
1015 */
1016#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
1017
1018/* BR6 is configured as follows:
1019 *
1020 * - Base address of 0x60000000
1021 * - 16 bit port size
1022 * - Data errors checking is disabled
1023 * - Read and write access
1024 * - GPCM 60x bus
1025 * - Access are handled by the memory controller according to MSEL
1026 * - Not used for atomic operations
1027 * - No data pipelining is done
1028 * - Valid
1029 */
1030# define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
1031 BRx_PS_16 |\
1032 BRx_MS_GPCM_P |\
1033 BRx_V)
1034
1035/* OR6 is configured as follows:
1036 *
1037 * - 2 MB
1038 * - *BCTL0 is asserted upon access to the current memory bank
1039 * - *CW / *WE are negated a quarter of a clock earlier
1040 * - *CS is output at the same time as the address lines
1041 * - Uses a clock cycle length of 5
1042 * - *PSDVAL is generated internally by the memory controller
1043 * unless *GTA is asserted earlier externally.
1044 * - Relaxed timing is generated by the GPCM for accesses
1045 * initiated to this memory region.
1046 * - One idle clock is inserted between a read access from the
1047 * current bank and the next access.
1048 */
1049# define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\
1050 ORxG_CSNT |\
1051 ORxG_ACS_DIV1 |\
1052 ORxG_SCY_5_CLK |\
1053 ORxG_TRLX |\
1054 ORxG_EHTR)
1055#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
1056
1057/*
1058 * Internal Definitions
1059 *
1060 * Boot Flags
1061 */
1062#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
1063#define BOOTFLAG_WARM 0x02 /* Software reboot */
1064
1065#endif /* __CONFIG_H */