blob: e70b90765a96a60375eb01d8b7deaa6b01438406 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Scott Wood96b8a052007-04-16 14:54:15 -05002/*
Scott Woode8d3ca82010-08-30 18:04:52 -05003 * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
Scott Wood96b8a052007-04-16 14:54:15 -05004 */
5/*
6 * mpc8313epb board configuration file
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Simon Glass1af3c7f2020-05-10 11:40:09 -060012#include <linux/stringify.h>
13
Scott Wood96b8a052007-04-16 14:54:15 -050014/*
15 * High Level Configuration Options
16 */
17#define CONFIG_E300 1
Scott Wood96b8a052007-04-16 14:54:15 -050018
Scott Wood22f44422012-12-06 13:33:18 +000019#define CONFIG_SPL_INIT_MINIMAL
Scott Wood22f44422012-12-06 13:33:18 +000020#define CONFIG_SPL_FLUSH_IMAGE
21#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
22#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
23
24#ifdef CONFIG_SPL_BUILD
25#define CONFIG_NS16550_MIN_FUNCTIONS
26#endif
27
Scott Wood22f44422012-12-06 13:33:18 +000028#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
29#define CONFIG_SPL_MAX_SIZE (4 * 1024)
Benoît Thébaudeau6113d3f2013-04-11 09:35:49 +000030#define CONFIG_SPL_PAD_TO 0x4000
Scott Wood22f44422012-12-06 13:33:18 +000031
Scott Woodf1c574d2010-11-24 13:28:40 +000032#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
33#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
34#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
35#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
36#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
37#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
38
Scott Wood22f44422012-12-06 13:33:18 +000039#ifdef CONFIG_SPL_BUILD
Scott Woodf1c574d2010-11-24 13:28:40 +000040#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
Scott Wood22f44422012-12-06 13:33:18 +000041#endif
42
Scott Woodf1c574d2010-11-24 13:28:40 +000043#ifndef CONFIG_SYS_MONITOR_BASE
44#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
45#endif
46
Gabor Juhos842033e2013-05-30 07:06:12 +000047#define CONFIG_PCI_INDIRECT_BRIDGE
Scott Wood96b8a052007-04-16 14:54:15 -050048
Timur Tabi89c77842008-02-08 13:15:55 -060049/*
50 * On-board devices
York Sun4ce1e232008-05-15 15:26:27 -050051 *
52 * TSEC1 is VSC switch
53 * TSEC2 is SoC TSEC
Timur Tabi89c77842008-02-08 13:15:55 -060054 */
55#define CONFIG_VSC7385_ENET
York Sun4ce1e232008-05-15 15:26:27 -050056#define CONFIG_TSEC2
Timur Tabi89c77842008-02-08 13:15:55 -060057
Mario Six16aaca22019-01-21 09:17:36 +010058#if !defined(CONFIG_SPL_BUILD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
Scott Woode4c09502008-06-30 14:13:28 -050060#endif
61
Scott Wood96b8a052007-04-16 14:54:15 -050062/* Early revs of this board will lock up hard when attempting
63 * to access the PMC registers, unless a JTAG debugger is
64 * connected, or some resistor modifications are made.
65 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
Scott Wood96b8a052007-04-16 14:54:15 -050067
Scott Wood96b8a052007-04-16 14:54:15 -050068/*
Timur Tabi89c77842008-02-08 13:15:55 -060069 * Device configurations
70 */
71
72/* Vitesse 7385 */
73
74#ifdef CONFIG_VSC7385_ENET
75
York Sun4ce1e232008-05-15 15:26:27 -050076#define CONFIG_TSEC1
Timur Tabi89c77842008-02-08 13:15:55 -060077
78/* The flash address and size of the VSC7385 firmware image */
79#define CONFIG_VSC7385_IMAGE 0xFE7FE000
80#define CONFIG_VSC7385_IMAGE_SIZE 8192
81
82#endif
83
84/*
Scott Wood96b8a052007-04-16 14:54:15 -050085 * DDR Setup
86 */
Mario Six8a81bfd2019-01-21 09:18:15 +010087#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
Scott Wood96b8a052007-04-16 14:54:15 -050088
89/*
90 * Manually set up DDR parameters, as this board does not
91 * seem to have the SPD connected to I2C.
92 */
Joe Hershberger261c07b2011-10-11 23:57:10 -050093#define CONFIG_SYS_DDR_SIZE 128 /* MB */
Joe Hershberger2e651b22011-10-11 23:57:31 -050094#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger2fef4022011-10-11 23:57:29 -050095 | CSCONFIG_ODT_RD_NEVER \
96 | CSCONFIG_ODT_WR_ONLY_CURRENT \
Joe Hershberger261c07b2011-10-11 23:57:10 -050097 | CSCONFIG_ROW_BIT_13 \
98 | CSCONFIG_COL_BIT_10)
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +053099 /* 0x80010102 */
Scott Wood96b8a052007-04-16 14:54:15 -0500100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershberger261c07b2011-10-11 23:57:10 -0500102#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
103 | (0 << TIMING_CFG0_WRT_SHIFT) \
104 | (0 << TIMING_CFG0_RRT_SHIFT) \
105 | (0 << TIMING_CFG0_WWT_SHIFT) \
106 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
107 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
108 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
109 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Scott Wood96b8a052007-04-16 14:54:15 -0500110 /* 0x00220802 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500111#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
112 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
113 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
114 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
115 | (10 << TIMING_CFG1_REFREC_SHIFT) \
116 | (3 << TIMING_CFG1_WRREC_SHIFT) \
117 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
118 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530119 /* 0x3835a322 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500120#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
121 | (5 << TIMING_CFG2_CPO_SHIFT) \
122 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
123 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
124 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
125 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
126 | (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530127 /* 0x129048c6 */ /* P9-45,may need tuning */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500128#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
129 | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530130 /* 0x05100500 */
Scott Wood96b8a052007-04-16 14:54:15 -0500131#if defined(CONFIG_DDR_2T_TIMING)
Joe Hershberger261c07b2011-10-11 23:57:10 -0500132#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500133 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500134 | SDRAM_CFG_DBW_32 \
135 | SDRAM_CFG_2T_EN)
136 /* 0x43088000 */
Scott Wood96b8a052007-04-16 14:54:15 -0500137#else
Joe Hershberger261c07b2011-10-11 23:57:10 -0500138#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500139 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500140 | SDRAM_CFG_DBW_32)
Scott Wood96b8a052007-04-16 14:54:15 -0500141 /* 0x43080000 */
142#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_SDRAM_CFG2 0x00401000
Scott Wood96b8a052007-04-16 14:54:15 -0500144/* set burst length to 8 for 32-bit data path */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500145#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
146 | (0x0632 << SDRAM_MODE_SD_SHIFT))
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530147 /* 0x44480632 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500148#define CONFIG_SYS_DDR_MODE_2 0x8000C000
Scott Wood96b8a052007-04-16 14:54:15 -0500149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Scott Wood96b8a052007-04-16 14:54:15 -0500151 /*0x02000000*/
Joe Hershberger261c07b2011-10-11 23:57:10 -0500152#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
Scott Wood96b8a052007-04-16 14:54:15 -0500153 | DDRCDR_PZ_NOMZ \
154 | DDRCDR_NZ_NOMZ \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500155 | DDRCDR_M_ODR)
Scott Wood96b8a052007-04-16 14:54:15 -0500156
157/*
158 * FLASH on the Local Bus
159 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500161#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500162#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
Scott Wood96b8a052007-04-16 14:54:15 -0500163
Joe Hershberger261c07b2011-10-11 23:57:10 -0500164#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
165#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
Scott Wood96b8a052007-04-16 14:54:15 -0500166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
168#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Scott Wood96b8a052007-04-16 14:54:15 -0500169
Joe Hershberger261c07b2011-10-11 23:57:10 -0500170#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
Scott Wood22f44422012-12-06 13:33:18 +0000171 !defined(CONFIG_SPL_BUILD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_RAMBOOT
Scott Wood96b8a052007-04-16 14:54:15 -0500173#endif
174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershberger261c07b2011-10-11 23:57:10 -0500176#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
177#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Scott Wood96b8a052007-04-16 14:54:15 -0500178
Joe Hershberger261c07b2011-10-11 23:57:10 -0500179#define CONFIG_SYS_GBL_DATA_OFFSET \
180 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Scott Wood96b8a052007-04-16 14:54:15 -0500182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Kevin Hao16c8c172016-07-08 11:25:14 +0800184#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500185#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Scott Wood96b8a052007-04-16 14:54:15 -0500186
Miquel Raynala430fa02018-08-16 17:30:07 +0200187/* drivers/mtd/nand/raw/nand.c */
Mario Six16aaca22019-01-21 09:17:36 +0100188#if defined(CONFIG_SPL_BUILD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_NAND_BASE 0xFFF00000
Scott Woode4c09502008-06-30 14:13:28 -0500190#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_NAND_BASE 0xE2800000
Scott Woode4c09502008-06-30 14:13:28 -0500192#endif
193
Scott Woode8d3ca82010-08-30 18:04:52 -0500194#define CONFIG_MTD_PARTITION
Scott Woode8d3ca82010-08-30 18:04:52 -0500195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_MAX_NAND_DEVICE 1
Scott Woodacdab5c2008-06-26 14:06:52 -0500197#define CONFIG_NAND_FSL_ELBC 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500199#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
Scott Wood96b8a052007-04-16 14:54:15 -0500200
Mario Six16aaca22019-01-21 09:17:36 +0100201/* Still needed for spl_minimal.c */
202#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
203#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
Scott Woode4c09502008-06-30 14:13:28 -0500204
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500205/* local bus write LED / read status buffer (BCSR) mapping */
206#define CONFIG_SYS_BCSR_ADDR 0xFA000000
207#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */
208 /* map at 0xFA000000 on LCS3 */
Mario Sixa8f97532019-01-21 09:18:01 +0100209
Timur Tabi89c77842008-02-08 13:15:55 -0600210/* Vitesse 7385 */
211
Timur Tabi89c77842008-02-08 13:15:55 -0600212#ifdef CONFIG_VSC7385_ENET
213
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500214 /* VSC7385 Base address on LCS2 */
215#define CONFIG_SYS_VSC7385_BASE 0xF0000000
216#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */
217
Mario Sixa8f97532019-01-21 09:18:01 +0100218
Timur Tabi89c77842008-02-08 13:15:55 -0600219#endif
220
Joe Hershberger0eaf8f92011-11-11 15:55:38 -0600221#define CONFIG_MPC83XX_GPIO 1
Joe Hershberger0eaf8f92011-11-11 15:55:38 -0600222
Scott Wood96b8a052007-04-16 14:54:15 -0500223/*
224 * Serial Port
225 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_NS16550_SERIAL
227#define CONFIG_SYS_NS16550_REG_SIZE 1
Scott Wood96b8a052007-04-16 14:54:15 -0500228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_BAUDRATE_TABLE \
Scott Wood96b8a052007-04-16 14:54:15 -0500230 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
233#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Scott Wood96b8a052007-04-16 14:54:15 -0500234
Scott Wood96b8a052007-04-16 14:54:15 -0500235/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200236#define CONFIG_SYS_I2C
237#define CONFIG_SYS_I2C_FSL
238#define CONFIG_SYS_FSL_I2C_SPEED 400000
239#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
240#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
241#define CONFIG_SYS_FSL_I2C2_SPEED 400000
242#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
243#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
244#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Scott Wood96b8a052007-04-16 14:54:15 -0500245
Scott Wood96b8a052007-04-16 14:54:15 -0500246/*
247 * General PCI
248 * Addresses are mapped 1-1.
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
251#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
252#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
253#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
254#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
255#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
256#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
257#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
258#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Scott Wood96b8a052007-04-16 14:54:15 -0500259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Scott Wood96b8a052007-04-16 14:54:15 -0500261
262/*
Timur Tabi89c77842008-02-08 13:15:55 -0600263 * TSEC
Scott Wood96b8a052007-04-16 14:54:15 -0500264 */
Scott Wood96b8a052007-04-16 14:54:15 -0500265
Timur Tabi89c77842008-02-08 13:15:55 -0600266#define CONFIG_GMII /* MII PHY management */
267
268#ifdef CONFIG_TSEC1
269#define CONFIG_HAS_ETH0
270#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Timur Tabi89c77842008-02-08 13:15:55 -0600272#define TSEC1_PHY_ADDR 0x1c
273#define TSEC1_FLAGS TSEC_GIGABIT
274#define TSEC1_PHYIDX 0
Scott Wood96b8a052007-04-16 14:54:15 -0500275#endif
276
Timur Tabi89c77842008-02-08 13:15:55 -0600277#ifdef CONFIG_TSEC2
278#define CONFIG_HAS_ETH1
Kim Phillips255a35772007-05-16 16:52:19 -0500279#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi89c77842008-02-08 13:15:55 -0600281#define TSEC2_PHY_ADDR 4
282#define TSEC2_FLAGS TSEC_GIGABIT
283#define TSEC2_PHYIDX 0
284#endif
285
Scott Wood96b8a052007-04-16 14:54:15 -0500286/* Options are: TSEC[0-1] */
287#define CONFIG_ETHPRIME "TSEC1"
288
289/*
290 * Configure on-board RTC
291 */
292#define CONFIG_RTC_DS1337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Scott Wood96b8a052007-04-16 14:54:15 -0500294
295/*
296 * Environment
297 */
Tom Rinia09fea12019-11-18 20:02:10 -0500298#define CONFIG_ENV_RANGE (CONFIG_SYS_NAND_BLOCK_SIZE * 4)
Scott Wood96b8a052007-04-16 14:54:15 -0500299
300#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Scott Wood96b8a052007-04-16 14:54:15 -0500302
Jon Loeliger8ea54992007-07-04 22:30:06 -0500303/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500304 * BOOTP options
305 */
306#define CONFIG_BOOTP_BOOTFILESIZE
Jon Loeliger079a1362007-07-10 10:12:10 -0500307
Jon Loeliger079a1362007-07-10 10:12:10 -0500308/*
Scott Wood96b8a052007-04-16 14:54:15 -0500309 * Miscellaneous configurable options
310 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Scott Wood96b8a052007-04-16 14:54:15 -0500313
Joe Hershberger261c07b2011-10-11 23:57:10 -0500314 /* Boot Argument Buffer Size */
315#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Scott Wood96b8a052007-04-16 14:54:15 -0500316
317/*
318 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700319 * have to be in the first 256 MB of memory, since this is
Scott Wood96b8a052007-04-16 14:54:15 -0500320 * the maximum mapped by the Linux kernel during initialization.
321 */
Joe Hershberger261c07b2011-10-11 23:57:10 -0500322 /* Initial Memory map for Linux*/
323#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Kevin Hao63865272016-07-08 11:25:15 +0800324#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Scott Wood96b8a052007-04-16 14:54:15 -0500325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
Scott Wood96b8a052007-04-16 14:54:15 -0500327
Mario Sixff3bb0c2019-01-21 09:17:53 +0100328#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
Scott Wood96b8a052007-04-16 14:54:15 -0500329
330/* System IO Config */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
Joe Hershberger0eaf8f92011-11-11 15:55:38 -0600332 /* Enable Internal USB Phy and GPIO on LCD Connector */
333#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC)
Scott Wood96b8a052007-04-16 14:54:15 -0500334
Scott Wood96b8a052007-04-16 14:54:15 -0500335/*
Scott Wood96b8a052007-04-16 14:54:15 -0500336 * Environment Configuration
337 */
338#define CONFIG_ENV_OVERWRITE
339
Joe Hershberger261c07b2011-10-11 23:57:10 -0500340#define CONFIG_NETDEV "eth1"
Scott Wood96b8a052007-04-16 14:54:15 -0500341
Mario Six5bc05432018-03-28 14:38:20 +0200342#define CONFIG_HOSTNAME "mpc8313erdb"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000343#define CONFIG_ROOTPATH "/nfs/root/path"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000344#define CONFIG_BOOTFILE "uImage"
Joe Hershberger261c07b2011-10-11 23:57:10 -0500345 /* U-Boot image on TFTP server */
346#define CONFIG_UBOOTPATH "u-boot.bin"
347#define CONFIG_FDTFILE "mpc8313erdb.dtb"
Scott Wood96b8a052007-04-16 14:54:15 -0500348
Joe Hershberger261c07b2011-10-11 23:57:10 -0500349 /* default location for tftp and bootm */
350#define CONFIG_LOADADDR 800000
Scott Wood96b8a052007-04-16 14:54:15 -0500351
Scott Wood96b8a052007-04-16 14:54:15 -0500352#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500353 "netdev=" CONFIG_NETDEV "\0" \
Scott Wood96b8a052007-04-16 14:54:15 -0500354 "ethprime=TSEC1\0" \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500355 "uboot=" CONFIG_UBOOTPATH "\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200356 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut5368c552012-09-23 17:41:24 +0200357 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
358 " +$filesize; " \
359 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
360 " +$filesize; " \
361 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
362 " $filesize; " \
363 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
364 " +$filesize; " \
365 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
366 " $filesize\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500367 "fdtaddr=780000\0" \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500368 "fdtfile=" CONFIG_FDTFILE "\0" \
Scott Wood96b8a052007-04-16 14:54:15 -0500369 "console=ttyS0\0" \
370 "setbootargs=setenv bootargs " \
371 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200372 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
Joe Hershberger261c07b2011-10-11 23:57:10 -0500373 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
374 "$netdev:off " \
Scott Wood96b8a052007-04-16 14:54:15 -0500375 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
376
377#define CONFIG_NFSBOOTCOMMAND \
378 "setenv rootdev /dev/nfs;" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200379 "run setbootargs;" \
380 "run setipargs;" \
Scott Wood96b8a052007-04-16 14:54:15 -0500381 "tftp $loadaddr $bootfile;" \
382 "tftp $fdtaddr $fdtfile;" \
383 "bootm $loadaddr - $fdtaddr"
384
385#define CONFIG_RAMBOOTCOMMAND \
386 "setenv rootdev /dev/ram;" \
387 "run setbootargs;" \
388 "tftp $ramdiskaddr $ramdiskfile;" \
389 "tftp $loadaddr $bootfile;" \
390 "tftp $fdtaddr $fdtfile;" \
391 "bootm $loadaddr $ramdiskaddr $fdtaddr"
392
Scott Wood96b8a052007-04-16 14:54:15 -0500393#endif /* __CONFIG_H */