blob: 9832f85405c2330b145e523bbb2d97d2953ad989 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Biwen Lie6bd72f2020-05-01 20:04:17 +08004 * Copyright 2020 NXP
Chunhe Lan0b2e13d2014-04-14 18:42:06 +08005 */
6
7/*
8 * T4240 RDB board configuration file
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Simon Glass1af3c7f2020-05-10 11:40:09 -060013#include <linux/stringify.h>
14
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080015#define CONFIG_FSL_SATA_V2
16#define CONFIG_PCIE4
17
18#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
19
20#ifdef CONFIG_RAMBOOT_PBL
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080021#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
Chunhe Lan373762c2015-03-20 17:08:54 +080022#ifndef CONFIG_SDCARD
23#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
24#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
25#else
Chunhe Lan373762c2015-03-20 17:08:54 +080026#define CONFIG_SPL_FLUSH_IMAGE
Chunhe Lan373762c2015-03-20 17:08:54 +080027#define CONFIG_SPL_PAD_TO 0x40000
28#define CONFIG_SPL_MAX_SIZE 0x28000
29#define RESET_VECTOR_OFFSET 0x27FFC
30#define BOOT_PAGE_OFFSET 0x27000
31
32#ifdef CONFIG_SDCARD
33#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Chunhe Lan373762c2015-03-20 17:08:54 +080034#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
35#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
36#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
37#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
38#ifndef CONFIG_SPL_BUILD
39#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080040#endif
Zhao Qiangec90ac72016-09-08 12:55:32 +080041#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
Chunhe Lan373762c2015-03-20 17:08:54 +080042#endif
43
44#ifdef CONFIG_SPL_BUILD
45#define CONFIG_SPL_SKIP_RELOCATE
46#define CONFIG_SPL_COMMON_INIT_DDR
47#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Chunhe Lan373762c2015-03-20 17:08:54 +080048#endif
49
50#endif
51#endif /* CONFIG_RAMBOOT_PBL */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080052
53#define CONFIG_DDR_ECC
54
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080055/* High Level Configuration Options */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080056#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080057
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080058#ifndef CONFIG_RESET_VECTOR_ADDRESS
59#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
60#endif
61
62#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
York Sun51370d52016-12-28 08:43:45 -080063#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040064#define CONFIG_PCIE1 /* PCIE controller 1 */
65#define CONFIG_PCIE2 /* PCIE controller 2 */
66#define CONFIG_PCIE3 /* PCIE controller 3 */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080067#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
68
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080069#define CONFIG_ENV_OVERWRITE
70
71/*
72 * These can be toggled for performance analysis, otherwise use default.
73 */
74#define CONFIG_SYS_CACHE_STASHING
75#define CONFIG_BTB /* toggle branch predition */
76#ifdef CONFIG_DDR_ECC
77#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
78#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
79#endif
80
81#define CONFIG_ENABLE_36BIT_PHYS
82
83#define CONFIG_ADDR_MAP
84#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
85
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080086/*
87 * Config the L3 Cache as L3 SRAM
88 */
Chunhe Lan373762c2015-03-20 17:08:54 +080089#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
90#define CONFIG_SYS_L3_SIZE (512 << 10)
91#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
Tom Rinia09fea12019-11-18 20:02:10 -050092#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
Chunhe Lan373762c2015-03-20 17:08:54 +080093#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
94#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
95#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080096
97#define CONFIG_SYS_DCSRBAR 0xf0000000
98#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
99
100/*
101 * DDR Setup
102 */
103#define CONFIG_VERY_BIG_RAM
104#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
105#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
106
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800107#define CONFIG_DIMM_SLOTS_PER_CTLR 1
108#define CONFIG_CHIP_SELECTS_PER_CTRL 4
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800109
110#define CONFIG_DDR_SPD
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800111
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800112/*
113 * IFC Definitions
114 */
115#define CONFIG_SYS_FLASH_BASE 0xe0000000
116#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
117
Chunhe Lan373762c2015-03-20 17:08:54 +0800118#ifdef CONFIG_SPL_BUILD
119#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
120#else
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800121#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Chunhe Lan373762c2015-03-20 17:08:54 +0800122#endif
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800123
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800124#define CONFIG_HWCONFIG
125
126/* define to use L1 as initial stack */
127#define CONFIG_L1_INIT_RAM
128#define CONFIG_SYS_INIT_RAM_LOCK
129#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
130#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700131#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800132/* The assembler doesn't like typecast */
133#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
134 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
135 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
136#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
137
138#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
139 GENERATED_GBL_DATA_SIZE)
140#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
141
Chunhe Lan373762c2015-03-20 17:08:54 +0800142#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800143#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
144
145/* Serial Port - controlled on board with jumper J8
146 * open - index 2
147 * shorted - index 1
148 */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800149#define CONFIG_SYS_NS16550_SERIAL
150#define CONFIG_SYS_NS16550_REG_SIZE 1
151#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
152
153#define CONFIG_SYS_BAUDRATE_TABLE \
154 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
155
156#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
157#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
158#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
159#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
160
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800161/* I2C */
Biwen Lie6bd72f2020-05-01 20:04:17 +0800162#ifndef CONFIG_DM_I2C
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800163#define CONFIG_SYS_I2C
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800164#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
165#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
166#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
167#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
Biwen Lie6bd72f2020-05-01 20:04:17 +0800168#else
169#define CONFIG_I2C_SET_DEFAULT_BUS_NUM
170#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0
171#endif
172
173#define CONFIG_SYS_I2C_FSL
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800174
175/*
176 * General PCI
177 * Memory space is mapped 1-1, but I/O space must start from 0.
178 */
179
180/* controller 1, direct to uli, tgtid 3, Base address 20000 */
181#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800182#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800183#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800184#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800185
186/* controller 2, Slot 2, tgtid 2, Base address 201000 */
187#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800188#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800189#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800190#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800191
192/* controller 3, Slot 1, tgtid 1, Base address 202000 */
193#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800194#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800195#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800196#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800197
198/* controller 4, Base address 203000 */
199#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
200#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800201#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800202
203#ifdef CONFIG_PCI
Hou Zhiqiang75a91372019-08-27 11:03:13 +0000204#if !defined(CONFIG_DM_PCI)
205#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
206#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
207#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
208#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
209#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
210#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
211#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
212#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
213#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
214#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
215#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
216#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
217#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
218#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
219#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
220#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
221#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800222#define CONFIG_PCI_INDIRECT_BRIDGE
Hou Zhiqiang75a91372019-08-27 11:03:13 +0000223#endif
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800224
225#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800226#endif /* CONFIG_PCI */
227
228/* SATA */
229#ifdef CONFIG_FSL_SATA_V2
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800230#define CONFIG_SYS_SATA_MAX_DEVICE 2
231#define CONFIG_SATA1
232#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
233#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
234#define CONFIG_SATA2
235#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
236#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
237
238#define CONFIG_LBA48
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800239#endif
240
241#ifdef CONFIG_FMAN_ENET
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800242#define CONFIG_ETHPRIME "FM1@DTSEC1"
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800243#endif
244
245/*
246 * Environment
247 */
248#define CONFIG_LOADS_ECHO /* echo on for serial download */
249#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
250
251/*
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800252 * Miscellaneous configurable options
253 */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800254#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800255
256/*
257 * For booting Linux, the board info and command line data
258 * have to be in the first 64 MB of memory, since this is
259 * the maximum mapped by the Linux kernel during initialization.
260 */
261#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
262#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
263
264#ifdef CONFIG_CMD_KGDB
265#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
266#endif
267
268/*
269 * Environment Configuration
270 */
271#define CONFIG_ROOTPATH "/opt/nfsroot"
272#define CONFIG_BOOTFILE "uImage"
273#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
274
275/* default location for tftp and bootm */
276#define CONFIG_LOADADDR 1000000
277
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800278#define CONFIG_HVBOOT \
279 "setenv bootargs config-addr=0x60000000; " \
280 "bootm 0x01000000 - 0x00f00000"
281
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800282#if defined(CONFIG_SPIFLASH)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800283#elif defined(CONFIG_SDCARD)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800284#define CONFIG_SYS_MMC_ENV_DEV 0
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800285#endif
286
287#define CONFIG_SYS_CLK_FREQ 66666666
288#define CONFIG_DDR_CLK_FREQ 133333333
289
290#ifndef __ASSEMBLY__
291unsigned long get_board_sys_clk(void);
292unsigned long get_board_ddr_clk(void);
293#endif
294
295/*
296 * DDR Setup
297 */
298#define CONFIG_SYS_SPD_BUS_NUM 0
299#define SPD_EEPROM_ADDRESS1 0x52
300#define SPD_EEPROM_ADDRESS2 0x54
301#define SPD_EEPROM_ADDRESS3 0x56
302#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
303#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
304
305/*
306 * IFC Definitions
307 */
308#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
309#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
310 + 0x8000000) | \
311 CSPR_PORT_SIZE_16 | \
312 CSPR_MSEL_NOR | \
313 CSPR_V)
314#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
315#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
316 CSPR_PORT_SIZE_16 | \
317 CSPR_MSEL_NOR | \
318 CSPR_V)
319#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
320/* NOR Flash Timing Params */
321#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
322
323#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
324 FTIM0_NOR_TEADC(0x5) | \
325 FTIM0_NOR_TEAHC(0x5))
326#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
327 FTIM1_NOR_TRAD_NOR(0x1A) |\
328 FTIM1_NOR_TSEQRAD_NOR(0x13))
329#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
330 FTIM2_NOR_TCH(0x4) | \
331 FTIM2_NOR_TWPH(0x0E) | \
332 FTIM2_NOR_TWP(0x1c))
333#define CONFIG_SYS_NOR_FTIM3 0x0
334
335#define CONFIG_SYS_FLASH_QUIET_TEST
336#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
337
338#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
339#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
340#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
341#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
342
343#define CONFIG_SYS_FLASH_EMPTY_INFO
344#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
345 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
346
347/* NAND Flash on IFC */
348#define CONFIG_NAND_FSL_IFC
349#define CONFIG_SYS_NAND_MAX_ECCPOS 256
350#define CONFIG_SYS_NAND_MAX_OOBFREE 2
351#define CONFIG_SYS_NAND_BASE 0xff800000
352#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
353
354#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
355#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
356 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
357 | CSPR_MSEL_NAND /* MSEL = NAND */ \
358 | CSPR_V)
359#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
360
361#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
362 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
363 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
364 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
365 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
366 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
367 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
368
369#define CONFIG_SYS_NAND_ONFI_DETECTION
370
371/* ONFI NAND Flash mode0 Timing Params */
372#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
373 FTIM0_NAND_TWP(0x18) | \
374 FTIM0_NAND_TWCHT(0x07) | \
375 FTIM0_NAND_TWH(0x0a))
376#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
377 FTIM1_NAND_TWBE(0x39) | \
378 FTIM1_NAND_TRR(0x0e) | \
379 FTIM1_NAND_TRP(0x18))
380#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
381 FTIM2_NAND_TREH(0x0a) | \
382 FTIM2_NAND_TWHRE(0x1e))
383#define CONFIG_SYS_NAND_FTIM3 0x0
384
385#define CONFIG_SYS_NAND_DDR_LAW 11
386#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
387#define CONFIG_SYS_MAX_NAND_DEVICE 1
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800388
389#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
390
Miquel Raynal88718be2019-10-03 19:50:03 +0200391#if defined(CONFIG_MTD_RAW_NAND)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800392#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
393#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
394#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
395#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
396#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
397#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
398#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
399#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
400#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
401#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
402#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
403#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
404#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
405#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
406#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
407#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
408#else
409#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
410#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
411#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
412#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
413#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
414#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
415#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
416#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
417#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
418#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
419#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
420#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
421#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
422#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
423#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
424#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
425#endif
426#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
427#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
428#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
429#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
430#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
431#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
432#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
433#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
434
Chunhe Lanab06b232014-09-12 14:47:09 +0800435/* CPLD on IFC */
436#define CONFIG_SYS_CPLD_BASE 0xffdf0000
437#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
438#define CONFIG_SYS_CSPR3_EXT (0xf)
439#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
440 | CSPR_PORT_SIZE_8 \
441 | CSPR_MSEL_GPCM \
442 | CSPR_V)
443
Rajesh Bhagat088d52c2018-11-05 18:01:19 +0000444#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
Chunhe Lanab06b232014-09-12 14:47:09 +0800445#define CONFIG_SYS_CSOR3 0x0
446
447/* CPLD Timing parameters for IFC CS3 */
448#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
449 FTIM0_GPCM_TEADC(0x0e) | \
450 FTIM0_GPCM_TEAHC(0x0e))
451#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
452 FTIM1_GPCM_TRAD(0x1f))
453#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Chunhe Lan1b5c2b52014-10-20 16:03:15 +0800454 FTIM2_GPCM_TCH(0x8) | \
Chunhe Lanab06b232014-09-12 14:47:09 +0800455 FTIM2_GPCM_TWP(0x1f))
456#define CONFIG_SYS_CS3_FTIM3 0x0
457
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800458#if defined(CONFIG_RAMBOOT_PBL)
459#define CONFIG_SYS_RAMBOOT
460#endif
461
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800462/* I2C */
463#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
464#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
465#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
466#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
467
468#define I2C_MUX_CH_DEFAULT 0x8
469#define I2C_MUX_CH_VOL_MONITOR 0xa
470#define I2C_MUX_CH_VSC3316_FS 0xc
471#define I2C_MUX_CH_VSC3316_BS 0xd
472
473/* Voltage monitor on channel 2*/
474#define I2C_VOL_MONITOR_ADDR 0x40
475#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
476#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
477#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
478
Ying Zhang2f66a822016-01-22 12:15:13 +0800479#define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
480#ifndef CONFIG_SPL_BUILD
481#define CONFIG_VID
482#endif
483#define CONFIG_VOL_MONITOR_IR36021_SET
484#define CONFIG_VOL_MONITOR_IR36021_READ
485/* The lowest and highest voltage allowed for T4240RDB */
486#define VDD_MV_MIN 819
487#define VDD_MV_MAX 1212
488
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800489/*
490 * eSPI - Enhanced SPI
491 */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800492
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800493/* Qman/Bman */
494#ifndef CONFIG_NOBQFMAN
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800495#define CONFIG_SYS_BMAN_NUM_PORTALS 50
496#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
497#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
498#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500499#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
500#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
501#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
502#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
503#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
504 CONFIG_SYS_BMAN_CENA_SIZE)
505#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
506#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800507#define CONFIG_SYS_QMAN_NUM_PORTALS 50
508#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
509#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
510#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500511#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
512#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
513#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
514#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
515#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
516 CONFIG_SYS_QMAN_CENA_SIZE)
517#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
518#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800519
520#define CONFIG_SYS_DPAA_FMAN
521#define CONFIG_SYS_DPAA_PME
522#define CONFIG_SYS_PMAN
523#define CONFIG_SYS_DPAA_DCE
524#define CONFIG_SYS_DPAA_RMAN
525#define CONFIG_SYS_INTERLAKEN
526
527/* Default address of microcode for the Linux Fman driver */
528#if defined(CONFIG_SPIFLASH)
529/*
530 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
531 * env, so we got 0x110000.
532 */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800533#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
534#elif defined(CONFIG_SDCARD)
535/*
536 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Chunhe Lan373762c2015-03-20 17:08:54 +0800537 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
538 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800539 */
Chunhe Lan373762c2015-03-20 17:08:54 +0800540#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
Miquel Raynal88718be2019-10-03 19:50:03 +0200541#elif defined(CONFIG_MTD_RAW_NAND)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800542#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
543#else
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800544#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
545#endif
546#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
547#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
548#endif /* CONFIG_NOBQFMAN */
549
550#ifdef CONFIG_SYS_DPAA_FMAN
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800551#define CONFIG_CORTINA_FW_ADDR 0xefe00000
552#define CONFIG_CORTINA_FW_LENGTH 0x40000
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800553#define SGMII_PHY_ADDR1 0x0
554#define SGMII_PHY_ADDR2 0x1
555#define SGMII_PHY_ADDR3 0x2
556#define SGMII_PHY_ADDR4 0x3
557#define SGMII_PHY_ADDR5 0x4
558#define SGMII_PHY_ADDR6 0x5
559#define SGMII_PHY_ADDR7 0x6
560#define SGMII_PHY_ADDR8 0x7
561#define FM1_10GEC1_PHY_ADDR 0x10
562#define FM1_10GEC2_PHY_ADDR 0x11
563#define FM2_10GEC1_PHY_ADDR 0x12
564#define FM2_10GEC2_PHY_ADDR 0x13
565#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
566#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
567#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
568#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
569#endif
570
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800571/* SATA */
572#ifdef CONFIG_FSL_SATA_V2
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800573#define CONFIG_SYS_SATA_MAX_DEVICE 2
574#define CONFIG_SATA1
575#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
576#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
577#define CONFIG_SATA2
578#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
579#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
580
581#define CONFIG_LBA48
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800582#endif
583
584#ifdef CONFIG_FMAN_ENET
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800585#define CONFIG_ETHPRIME "FM1@DTSEC1"
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800586#endif
587
588/*
589* USB
590*/
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800591#define CONFIG_USB_EHCI_FSL
592#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800593#define CONFIG_HAS_FSL_DR_USB
594
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800595#ifdef CONFIG_MMC
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800596#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
597#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
Xiaobo Xie929dfdc2014-11-18 09:12:24 +0800598#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800599#endif
600
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800601
602#define __USB_PHY_TYPE utmi
603
604/*
605 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
606 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
607 * interleaving. It can be cacheline, page, bank, superbank.
608 * See doc/README.fsl-ddr for details.
609 */
York Sun26bc57d2016-11-21 13:35:41 -0800610#ifdef CONFIG_ARCH_T4240
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800611#define CTRL_INTLV_PREFERED 3way_4KB
Chunhe Lan1a344452014-05-07 10:56:18 +0800612#else
613#define CTRL_INTLV_PREFERED cacheline
614#endif
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800615
616#define CONFIG_EXTRA_ENV_SETTINGS \
617 "hwconfig=fsl_ddr:" \
618 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
619 "bank_intlv=auto;" \
620 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
621 "netdev=eth0\0" \
622 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
623 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
624 "tftpflash=tftpboot $loadaddr $uboot && " \
625 "protect off $ubootaddr +$filesize && " \
626 "erase $ubootaddr +$filesize && " \
627 "cp.b $loadaddr $ubootaddr $filesize && " \
628 "protect on $ubootaddr +$filesize && " \
629 "cmp.b $loadaddr $ubootaddr $filesize\0" \
630 "consoledev=ttyS0\0" \
631 "ramdiskaddr=2000000\0" \
632 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500633 "fdtaddr=1e00000\0" \
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800634 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
635 "bdev=sda3\0"
636
637#define CONFIG_HVBOOT \
638 "setenv bootargs config-addr=0x60000000; " \
639 "bootm 0x01000000 - 0x00f00000"
640
641#define CONFIG_LINUX \
642 "setenv bootargs root=/dev/ram rw " \
643 "console=$consoledev,$baudrate $othbootargs;" \
644 "setenv ramdiskaddr 0x02000000;" \
645 "setenv fdtaddr 0x00c00000;" \
646 "setenv loadaddr 0x1000000;" \
647 "bootm $loadaddr $ramdiskaddr $fdtaddr"
648
649#define CONFIG_HDBOOT \
650 "setenv bootargs root=/dev/$bdev rw " \
651 "console=$consoledev,$baudrate $othbootargs;" \
652 "tftp $loadaddr $bootfile;" \
653 "tftp $fdtaddr $fdtfile;" \
654 "bootm $loadaddr - $fdtaddr"
655
656#define CONFIG_NFSBOOTCOMMAND \
657 "setenv bootargs root=/dev/nfs rw " \
658 "nfsroot=$serverip:$rootpath " \
659 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
660 "console=$consoledev,$baudrate $othbootargs;" \
661 "tftp $loadaddr $bootfile;" \
662 "tftp $fdtaddr $fdtfile;" \
663 "bootm $loadaddr - $fdtaddr"
664
665#define CONFIG_RAMBOOTCOMMAND \
666 "setenv bootargs root=/dev/ram rw " \
667 "console=$consoledev,$baudrate $othbootargs;" \
668 "tftp $ramdiskaddr $ramdiskfile;" \
669 "tftp $loadaddr $bootfile;" \
670 "tftp $fdtaddr $fdtfile;" \
671 "bootm $loadaddr $ramdiskaddr $fdtaddr"
672
673#define CONFIG_BOOTCOMMAND CONFIG_LINUX
674
675#include <asm/fsl_secure_boot.h>
676
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800677#endif /* __CONFIG_H */