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Dirk Eibacha605ea72010-10-21 10:50:05 +02001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibacha605ea72010-10-21 10:50:05 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* this is a PPC405 CPU */
Dirk Eibacha605ea72010-10-21 10:50:05 +020012#define CONFIG_IOCON 1 /* on a IoCon board */
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16/*
17 * Include common defines/options for all AMCC eval boards
18 */
19#define CONFIG_HOSTNAME iocon
Dirk Eibachcccd4f42014-07-03 09:28:20 +020020#define CONFIG_IDENT_STRING " iocon 0.06"
Dirk Eibacha605ea72010-10-21 10:50:05 +020021#include "amcc-common.h"
22
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000023#define CONFIG_BOARD_EARLY_INIT_F
24#define CONFIG_BOARD_EARLY_INIT_R
Dirk Eibacha605ea72010-10-21 10:50:05 +020025#define CONFIG_LAST_STAGE_INIT
Dirk Eibachd9f923f2014-07-25 10:10:24 +020026#define CONFIG_SYS_GENERIC_BOARD
Dirk Eibacha605ea72010-10-21 10:50:05 +020027
28#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
29
30/*
31 * Configure PLL
32 */
33#define PLLMR0_DEFAULT PLLMR0_266_133_66
34#define PLLMR1_DEFAULT PLLMR1_266_133_66
35
Dirk Eibach996d88d2012-04-26 03:54:25 +000036#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
Dirk Eibach996d88d2012-04-26 03:54:25 +000037
Dirk Eibacha605ea72010-10-21 10:50:05 +020038/* new uImage format support */
39#define CONFIG_FIT
40#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
Dirk Eibach9a4f4792014-07-03 09:28:26 +020041#define CONFIG_FIT_DISABLE_SHA256
Dirk Eibacha605ea72010-10-21 10:50:05 +020042
43#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
44
45/*
46 * Default environment variables
47 */
48#define CONFIG_EXTRA_ENV_SETTINGS \
49 CONFIG_AMCC_DEF_ENV \
50 CONFIG_AMCC_DEF_ENV_POWERPC \
51 CONFIG_AMCC_DEF_ENV_NOR_UPD \
52 "kernel_addr=fc000000\0" \
53 "fdt_addr=fc1e0000\0" \
54 "ramdisk_addr=fc200000\0" \
55 ""
56
57#define CONFIG_PHY_ADDR 4 /* PHY address */
58#define CONFIG_HAS_ETH0
59#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
60
61/*
62 * Commands additional to the ones defined in amcc-common.h
63 */
64#define CONFIG_CMD_CACHE
Michal Simek7d2357c2014-06-17 00:36:14 +020065#define CONFIG_CMD_FPGAD
Dirk Eibacha605ea72010-10-21 10:50:05 +020066#undef CONFIG_CMD_EEPROM
Dirk Eibach4fb9b412014-07-03 09:28:25 +020067#undef CONFIG_CMD_ELF
68#undef CONFIG_CMD_I2C
69#undef CONFIG_CMD_IRQ
Dirk Eibacha605ea72010-10-21 10:50:05 +020070
71/*
72 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
73 */
74#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
75
76/* SDRAM timings used in datasheet */
77#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
78#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
79#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
80#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
81#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
82
83/*
84 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
85 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
86 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
87 * The Linux BASE_BAUD define should match this configuration.
88 * baseBaud = cpuClock/(uartDivisor*16)
89 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
90 * set Linux BASE_BAUD to 403200.
91 */
92#define CONFIG_CONS_INDEX 1 /* Use UART0 */
93#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
94#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
95#define CONFIG_SYS_BASE_BAUD 691200
96
97/*
98 * I2C stuff
99 */
Heiko Schocherea818db2013-01-29 08:53:15 +0100100#define CONFIG_SYS_I2C
Dirk Eibach880540d2013-04-25 02:40:01 +0000101#define CONFIG_SYS_I2C_PPC4XX
102#define CONFIG_SYS_I2C_PPC4XX_CH0
103#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
104#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Dirk Eibachb46226b2014-07-03 09:28:18 +0200105#define CONFIG_SYS_I2C_IHS
Dirk Eibacha605ea72010-10-21 10:50:05 +0200106
Dirk Eibache50e8962013-07-25 19:28:13 +0200107#define CONFIG_SYS_I2C_SPEED 400000
Dirk Eibachb46226b2014-07-03 09:28:18 +0200108#define CONFIG_SYS_SPD_BUS_NUM 4
Dirk Eibache50e8962013-07-25 19:28:13 +0200109
110#define CONFIG_PCA953X /* NXP PCA9554 */
111#define CONFIG_PCA9698 /* NXP PCA9698 */
112
Dirk Eibachb46226b2014-07-03 09:28:18 +0200113#define CONFIG_SYS_I2C_IHS_CH0
114#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
115#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
116#define CONFIG_SYS_I2C_IHS_CH1
117#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
118#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
119#define CONFIG_SYS_I2C_IHS_CH2
120#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
121#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
122#define CONFIG_SYS_I2C_IHS_CH3
123#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
124#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
125
Dirk Eibacha605ea72010-10-21 10:50:05 +0200126/*
127 * Software (bit-bang) I2C driver configuration
128 */
Dirk Eibache50e8962013-07-25 19:28:13 +0200129#define CONFIG_SYS_I2C_SOFT
130#define CONFIG_SYS_I2C_SOFT_SPEED 50000
131#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
132#define I2C_SOFT_DECLARATIONS2
133#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
134#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
135#define I2C_SOFT_DECLARATIONS3
136#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
137#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
138#define I2C_SOFT_DECLARATIONS4
139#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
140#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
141
Dirk Eibachb46226b2014-07-03 09:28:18 +0200142#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
143#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
144#define CONFIG_SYS_DP501_I2C {0, 1, 2, 3}
Dirk Eibacha605ea72010-10-21 10:50:05 +0200145
146#ifndef __ASSEMBLY__
Dirk Eibache50e8962013-07-25 19:28:13 +0200147void fpga_gpio_set(unsigned int bus, int pin);
148void fpga_gpio_clear(unsigned int bus, int pin);
149int fpga_gpio_get(unsigned int bus, int pin);
Dirk Eibacha605ea72010-10-21 10:50:05 +0200150#endif
151
152#define I2C_ACTIVE { }
153#define I2C_TRISTATE { }
Dirk Eibache50e8962013-07-25 19:28:13 +0200154#define I2C_READ \
155 (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
156#define I2C_SDA(bit) \
157 do { \
158 if (bit) \
159 fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
160 else \
161 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
162 } while (0)
163#define I2C_SCL(bit) \
164 do { \
165 if (bit) \
166 fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
167 else \
168 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
169 } while (0)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200170#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
171
172/*
173 * FLASH organization
174 */
175#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
176#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
177
178#define CONFIG_SYS_FLASH_BASE 0xFC000000
179#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
180
181#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
182#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
183
184#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
185#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
186
187#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
Dirk Eibacha605ea72010-10-21 10:50:05 +0200188
189#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
190#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
191
192#ifdef CONFIG_ENV_IS_IN_FLASH
193#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
194#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
195#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
196
197/* Address and size of Redundant Environment Sector */
198#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
199#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
200#endif
201
202/*
203 * PPC405 GPIO Configuration
204 */
205#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
206{ \
207/* GPIO Core 0 */ \
208{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
209{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
210{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
211{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
212{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
213{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
214{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
215{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
216{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
217{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
218{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
219{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
220{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
221{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
222{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
223{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
224{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
225{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
226{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
227{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
228{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
229{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
230{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
231{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
232{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
233{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
234{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
235{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
236{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
237{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
238{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
239{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
240} \
241}
242
243/*
244 * Definitions for initial stack pointer and data area (in data cache)
245 */
246/* use on chip memory (OCM) for temperary stack until sdram is tested */
247#define CONFIG_SYS_TEMP_STACK_OCM 1
248
249/* On Chip Memory location */
250#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
251#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
252#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
253#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
254
Dirk Eibacha605ea72010-10-21 10:50:05 +0200255#define CONFIG_SYS_GBL_DATA_OFFSET \
Masahiro Yamada627b73e2014-02-07 09:23:03 +0900256 (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200257#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
258
259/*
260 * External Bus Controller (EBC) Setup
261 */
262
263/* Memory Bank 0 (NOR-FLASH) initialization */
264#define CONFIG_SYS_EBC_PB0AP 0xa382a880
265#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
266
267/* Memory Bank 1 (NVRAM) initializatio */
268#define CONFIG_SYS_EBC_PB1AP 0x92015480
269#define CONFIG_SYS_EBC_PB1CR 0xFB858000
270
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100271/* Memory Bank 2 (FPGA0) initialization */
272#define CONFIG_SYS_FPGA0_BASE 0x7f100000
Dirk Eibacha605ea72010-10-21 10:50:05 +0200273#define CONFIG_SYS_EBC_PB2AP 0x02825080
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100274#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200275
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100276#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
277#define CONFIG_SYS_FPGA_DONE(k) 0x0010
278
279#define CONFIG_SYS_FPGA_COUNT 1
Dirk Eibacha605ea72010-10-21 10:50:05 +0200280
Dirk Eibache50e8962013-07-25 19:28:13 +0200281#define CONFIG_SYS_MCLINK_MAX 3
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200282
Dirk Eibache50e8962013-07-25 19:28:13 +0200283#define CONFIG_SYS_FPGA_PTR \
284 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200285
Dirk Eibacha605ea72010-10-21 10:50:05 +0200286/* Memory Bank 3 (Latches) initialization */
287#define CONFIG_SYS_LATCH_BASE 0x7f200000
288#define CONFIG_SYS_EBC_PB3AP 0x02025080
289#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
290
291#define CONFIG_SYS_LATCH0_RESET 0xffef
292#define CONFIG_SYS_LATCH0_BOOT 0xffff
293#define CONFIG_SYS_LATCH1_RESET 0xffff
294#define CONFIG_SYS_LATCH1_BOOT 0xffff
295
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100296/*
297 * OSD Setup
298 */
299#define CONFIG_SYS_MPC92469AC
Dirk Eibache50e8962013-07-25 19:28:13 +0200300#define CONFIG_SYS_OSD_SCREENS 1
Dirk Eibachedfe9fe2014-07-03 09:28:17 +0200301#define CONFIG_SYS_DP501_DIFFERENTIAL
302#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
Dirk Eibache50e8962013-07-25 19:28:13 +0200303
304#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
305#define CONFIG_BITBANGMII_MULTI
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100306
Dirk Eibacha605ea72010-10-21 10:50:05 +0200307#endif /* __CONFIG_H */