blob: 09d227ae4892e0ec0568afd1121c3c830bcfe994 [file] [log] [blame]
Paul Burton25c7de22018-12-16 19:25:23 -03001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * CI20 configuration
4 *
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
7 */
8
9#ifndef __CONFIG_CI20_H__
10#define __CONFIG_CI20_H__
11
12#define CONFIG_SKIP_LOWLEVEL_INIT
13
14/* Ingenic JZ4780 clock configuration. */
15#define CONFIG_SYS_HZ 1000
16#define CONFIG_SYS_MHZ 1200
17#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
18
19/* Memory configuration */
20#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
21#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
22#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
23
24#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
25#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
Paul Burton25c7de22018-12-16 19:25:23 -030026
27#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
28
29/* NS16550-ish UARTs */
30#define CONFIG_SYS_NS16550_CLK 48000000
31#define CONFIG_SYS_CONSOLE_IS_IN_ENV
32
33/* Ethernet: davicom DM9000 */
34#define CONFIG_DRIVER_DM9000 1
35#define CONFIG_DM9000_BASE 0xb6000000
36#define DM9000_IO CONFIG_DM9000_BASE
37#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
38
Paul Burton25c7de22018-12-16 19:25:23 -030039#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
40#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
41#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
42 /* Boot argument buffer size */
43#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
44
45/* Miscellaneous configuration options */
46#define CONFIG_SYS_BOOTM_LEN (64 << 20)
47
48/* SPL */
49#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */
50
Paul Burton25c7de22018-12-16 19:25:23 -030051#define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00)
52
53#define CONFIG_SPL_BSS_START_ADDR 0xf4004000
54#define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */
55
56#define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx"
57
58#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1c /* 14 KiB offset */
59
60#endif /* __CONFIG_CI20_H__ */