blob: 570131fe713607f07e431b9f6c8ec1b872b09c48 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Patrick Bruenn98d62e62016-11-04 11:57:02 +01002/*
3 * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
4 * Patrick Bruenn <p.bruenn@beckhoff.com>
5 *
6 * Configuration settings for Beckhoff CX9020.
7 *
8 * Based on Freescale's Linux i.MX mx53loco.h file:
9 * Copyright (C) 2010-2011 Freescale Semiconductor.
Patrick Bruenn98d62e62016-11-04 11:57:02 +010010 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#include <asm/arch/imx-regs.h>
16
17#define CONFIG_CMDLINE_TAG
18#define CONFIG_SETUP_MEMORY_TAGS
19#define CONFIG_INITRD_TAG
20
21#define CONFIG_SYS_FSL_CLK
22
23/* Size of malloc() pool */
Steffen Dirkwinkel943be152019-10-23 07:40:43 +020024#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
Patrick Bruenn98d62e62016-11-04 11:57:02 +010025
Patrick Bruenn98d62e62016-11-04 11:57:02 +010026#define CONFIG_REVISION_TAG
27
28#define CONFIG_MXC_UART_BASE UART2_BASE
29
30#define CONFIG_FPGA_COUNT 1
31
32/* MMC Configs */
Patrick Bruenn98d62e62016-11-04 11:57:02 +010033#define CONFIG_SYS_FSL_ESDHC_ADDR 0
34#define CONFIG_SYS_FSL_ESDHC_NUM 2
35
Patrick Bruenn98d62e62016-11-04 11:57:02 +010036/* bootz: zImage/initrd.img support */
Patrick Bruenn98d62e62016-11-04 11:57:02 +010037
Patrick Bruenn98d62e62016-11-04 11:57:02 +010038
39/* USB Configs */
Patrick Bruenn98d62e62016-11-04 11:57:02 +010040#define CONFIG_MXC_USB_PORT 1
41#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
42#define CONFIG_MXC_USB_FLAGS 0
43
Patrick Bruenn98d62e62016-11-04 11:57:02 +010044/* Command definition */
Patrick Bruenn98d62e62016-11-04 11:57:02 +010045
Steffen Dirkwinkel943be152019-10-23 07:40:43 +020046#define BOOT_TARGET_DEVICES(func) \
47 func(MMC, mmc, 0) \
48 func(MMC, mmc, 1) \
49 func(USB, usb, 0) \
50 func(PXE, pxe, na)
51
52#include <config_distro_bootcmd.h>
53
Patrick Bruenn98d62e62016-11-04 11:57:02 +010054#define CONFIG_EXTRA_ENV_SETTINGS \
Steffen Dirkwinkel943be152019-10-23 07:40:43 +020055 "fdt_addr_r=0x75000000\0" \
Patrick Bruennbc104a72017-07-11 11:23:21 +020056 "pxefile_addr_r=0x73000000\0" \
Steffen Dirkwinkel943be152019-10-23 07:40:43 +020057 "scriptaddr=0x74000000\0" \
58 "ramdisk_addr_r=0x80000000\0" \
59 "kernel_addr_r=0x72000000\0" \
60 "fdt_high=0xffffffff\0" \
Patrick Bruenn98d62e62016-11-04 11:57:02 +010061 "console=ttymxc1,115200\0" \
Steffen Dirkwinkeldd7e7fe2019-10-23 07:40:42 +020062 "stdin=serial\0" \
63 "stdout=serial,vidconsole\0" \
64 "stderr=serial,vidconsole\0" \
Steffen Dirkwinkel943be152019-10-23 07:40:43 +020065 "fdtfile=imx53-cx9020.dtb\0" \
66 BOOTENV
Patrick Bruenn98d62e62016-11-04 11:57:02 +010067
68#define CONFIG_ARP_TIMEOUT 200UL
69
70/* Miscellaneous configurable options */
Patrick Bruenn98d62e62016-11-04 11:57:02 +010071#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
72
Patrick Bruenn98d62e62016-11-04 11:57:02 +010073/* Physical Memory Map */
Patrick Bruenn98d62e62016-11-04 11:57:02 +010074#define PHYS_SDRAM_1 CSD0_BASE_ADDR
75#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
76#define PHYS_SDRAM_2 CSD1_BASE_ADDR
77#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
78#define PHYS_SDRAM_SIZE (gd->ram_size)
79
80#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
81#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
82#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
83
84#define CONFIG_SYS_INIT_SP_OFFSET \
85 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
86#define CONFIG_SYS_INIT_SP_ADDR \
87 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
88
Masahiro Yamadae856bdc2017-02-11 22:43:54 +090089/* environment organization */
Patrick Bruenn98d62e62016-11-04 11:57:02 +010090
91/* Framebuffer and LCD */
Steffen Dirkwinkel29771c22019-04-17 13:57:17 +020092#define CONFIG_IMX_VIDEO_SKIP
Patrick Bruenn98d62e62016-11-04 11:57:02 +010093
94#endif /* __CONFIG_H */