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Nobuhiro Iwamatsu8ca805e2012-01-12 11:12:28 +09001/*
2 * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
3 * Copyright (C) 2011 Renesas Solutions Corp.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu8ca805e2012-01-12 11:12:28 +09006 */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/processor.h>
11#include <netdev.h>
Nobuhiro Iwamatsud7405552012-03-02 12:58:33 +090012#include <i2c.h>
Nobuhiro Iwamatsu8ca805e2012-01-12 11:12:28 +090013
14DECLARE_GLOBAL_DATA_PTR;
15
16#define MODEMR (0xFFCC0020)
17#define MODEMR_MASK (0x6)
18#define MODEMR_533MHZ (0x2)
19
20int checkboard(void)
21{
22 u32 r = readl(MODEMR);
23 if ((r & MODEMR_MASK) & MODEMR_533MHZ)
24 puts("CPU Clock: 533MHz\n");
25 else
26 puts("CPU Clock: 400MHz\n");
27
28 puts("BOARD: Renesas Technology Corp. R0P7734C00000RZ\n");
29 return 0;
30}
31
32#define MSTPSR1 (0xFFC80044)
33#define MSTPCR1 (0xFFC80034)
34#define MSTPSR1_GETHER (1 << 14)
35
36int board_init(void)
37{
38#if defined(CONFIG_SH_ETHER)
39 u32 r = readl(MSTPSR1);
40 if (r & MSTPSR1_GETHER)
41 writel((r & ~MSTPSR1_GETHER), MSTPCR1);
42#endif
Nobuhiro Iwamatsud7405552012-03-02 12:58:33 +090043
44 return 0;
45}
46
47int board_late_init(void)
48{
49 u8 mac[6];
50
51 /* Read Mac Address and set*/
52 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
53 i2c_set_bus_num(CONFIG_SYS_I2C_MODULE);
54
55 /* Read MAC address */
56 i2c_read(0x50, 0x10, 0, mac, 6);
57
58 if (is_valid_ether_addr(mac))
59 eth_setenv_enetaddr("ethaddr", mac);
60
Nobuhiro Iwamatsu8ca805e2012-01-12 11:12:28 +090061 return 0;
62}
63
64int dram_init(void)
65{
66 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
67 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
68 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
69
70 return 0;
71}
72
73#ifdef CONFIG_SMC911X
74int board_eth_init(bd_t *bis)
75{
76 int rc = 0;
77 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
78 return rc;
79}
80#endif