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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / ab9b4f35e38bf9725a13d2e487d1d5962ab412bb / . / arch / arm / dts / imx6qdl-gw552x.dtsi
blob: 5462907f12eb7baf6cbe1e92618de0cbf56d7360 [file] [log] [blame]
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2014 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 led2 = &led2;
16 nand = &gpmi;
17 usb0 = &usbh1;
18 usb1 = &usbotg;
19 };
20
21 chosen {
22 bootargs = "console=ttymxc1,115200";
23 };
24
25 gpio-keys {
26 compatible = "gpio-keys";
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 user-pb {
31 label = "user_pb";
32 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
33 linux,code = <BTN_0>;
34 };
35
36 user-pb1x {
37 label = "user_pb1x";
38 linux,code = <BTN_1>;
39 interrupt-parent = <&gsc>;
40 interrupts = <0>;
41 };
42
43 key-erased {
44 label = "key-erased";
45 linux,code = <BTN_2>;
46 interrupt-parent = <&gsc>;
47 interrupts = <1>;
48 };
49
50 eeprom-wp {
51 label = "eeprom_wp";
52 linux,code = <BTN_3>;
53 interrupt-parent = <&gsc>;
54 interrupts = <2>;
55 };
56
57 tamper {
58 label = "tamper";
59 linux,code = <BTN_4>;
60 interrupt-parent = <&gsc>;
61 interrupts = <5>;
62 };
63
64 switch-hold {
65 label = "switch_hold";
66 linux,code = <BTN_5>;
67 interrupt-parent = <&gsc>;
68 interrupts = <7>;
69 };
70 };
71
72 leds {
73 compatible = "gpio-leds";
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_gpio_leds>;
76
77 led0: user1 {
78 label = "user1";
79 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
80 default-state = "on";
81 linux,default-trigger = "heartbeat";
82 };
83
84 led1: user2 {
85 label = "user2";
86 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
87 default-state = "off";
88 };
89
90 led2: user3 {
91 label = "user3";
92 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
93 default-state = "off";
94 };
95 };
96
97 memory@10000000 {
98 device_type = "memory";
99 reg = <0x10000000 0x20000000>;
100 };
101
102 reg_1p0v: regulator-1p0v {
103 compatible = "regulator-fixed";
104 regulator-name = "1P0V";
105 regulator-min-microvolt = <1000000>;
106 regulator-max-microvolt = <1000000>;
107 regulator-always-on;
108 };
109
110 reg_3p3v: regulator-3p3v {
111 compatible = "regulator-fixed";
112 regulator-name = "3P3V";
113 regulator-min-microvolt = <3300000>;
114 regulator-max-microvolt = <3300000>;
115 regulator-always-on;
116 };
117
118 reg_5p0v: regulator-5p0v {
119 compatible = "regulator-fixed";
120 regulator-name = "5P0V";
121 regulator-min-microvolt = <5000000>;
122 regulator-max-microvolt = <5000000>;
123 regulator-always-on;
124 };
125};
126
127&gpmi {
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_gpmi_nand>;
130 status = "okay";
131};
132
133&hdmi {
134 ddc-i2c-bus = <&i2c3>;
135 status = "okay";
136};
137
138&i2c1 {
139 clock-frequency = <100000>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_i2c1>;
142 status = "okay";
143
144 gsc: gsc@20 {
145 compatible = "gw,gsc";
146 reg = <0x20>;
147 interrupt-parent = <&gpio1>;
148 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
149 interrupt-controller;
150 #interrupt-cells = <1>;
151 #size-cells = <0>;
152
153 adc {
154 compatible = "gw,gsc-adc";
155 #address-cells = <1>;
156 #size-cells = <0>;
157
158 channel@0 {
159 gw,mode = <0>;
160 reg = <0x00>;
161 label = "temp";
162 };
163
164 channel@2 {
165 gw,mode = <1>;
166 reg = <0x02>;
167 label = "vdd_vin";
168 };
169
170 channel@5 {
171 gw,mode = <1>;
172 reg = <0x05>;
173 label = "vdd_3p3";
174 };
175
176 channel@8 {
177 gw,mode = <1>;
178 reg = <0x08>;
179 label = "vdd_bat";
180 };
181
182 channel@b {
183 gw,mode = <1>;
184 reg = <0x0b>;
185 label = "vdd_5p0";
186 };
187
188 channel@e {
189 gw,mode = <1>;
190 reg = <0xe>;
191 label = "vdd_arm";
192 };
193
194 channel@11 {
195 gw,mode = <1>;
196 reg = <0x11>;
197 label = "vdd_soc";
198 };
199
200 channel@14 {
201 gw,mode = <1>;
202 reg = <0x14>;
203 label = "vdd_3p0";
204 };
205
206 channel@17 {
207 gw,mode = <1>;
208 reg = <0x17>;
209 label = "vdd_1p5";
210 };
211
212 channel@1d {
213 gw,mode = <1>;
214 reg = <0x1d>;
215 label = "vdd_1p8";
216 };
217
218 channel@20 {
219 gw,mode = <1>;
220 reg = <0x20>;
221 label = "vdd_1p0";
222 };
223
224 channel@23 {
225 gw,mode = <1>;
226 reg = <0x23>;
227 label = "vdd_2p5";
228 };
229 };
230 };
231
232 gsc_gpio: gpio@23 {
233 compatible = "nxp,pca9555";
234 reg = <0x23>;
235 gpio-controller;
236 #gpio-cells = <2>;
237 interrupt-parent = <&gsc>;
238 interrupts = <4>;
239 };
240
241 eeprom1: eeprom@50 {
242 compatible = "atmel,24c02";
243 reg = <0x50>;
244 pagesize = <16>;
245 };
246
247 eeprom2: eeprom@51 {
248 compatible = "atmel,24c02";
249 reg = <0x51>;
250 pagesize = <16>;
251 };
252
253 eeprom3: eeprom@52 {
254 compatible = "atmel,24c02";
255 reg = <0x52>;
256 pagesize = <16>;
257 };
258
259 eeprom4: eeprom@53 {
260 compatible = "atmel,24c02";
261 reg = <0x53>;
262 pagesize = <16>;
263 };
264
265 rtc: ds1672@68 {
266 compatible = "dallas,ds1672";
267 reg = <0x68>;
268 };
269};
270
271&i2c2 {
272 clock-frequency = <100000>;
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_i2c2>;
275 status = "okay";
276
277 ltc3676: pmic@3c {
278 compatible = "lltc,ltc3676";
279 reg = <0x3c>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_pmic>;
282 interrupt-parent = <&gpio1>;
283 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
284
285 regulators {
286 /* VDD_SOC (1+R1/R2 = 1.635) */
287 reg_vdd_soc: sw1 {
288 regulator-name = "vddsoc";
289 regulator-min-microvolt = <674400>;
290 regulator-max-microvolt = <1308000>;
291 lltc,fb-voltage-divider = <127000 200000>;
292 regulator-ramp-delay = <7000>;
293 regulator-boot-on;
294 regulator-always-on;
295 };
296
297 /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */
298 reg_1p8v: sw2 {
299 regulator-name = "vdd1p8";
300 regulator-min-microvolt = <1033310>;
301 regulator-max-microvolt = <2004000>;
302 lltc,fb-voltage-divider = <301000 200000>;
303 regulator-ramp-delay = <7000>;
304 regulator-boot-on;
305 regulator-always-on;
306 };
307
308 /* VDD_ARM (1+R1/R2 = 1.635) */
309 reg_vdd_arm: sw3 {
310 regulator-name = "vddarm";
311 regulator-min-microvolt = <674400>;
312 regulator-max-microvolt = <1308000>;
313 lltc,fb-voltage-divider = <127000 200000>;
314 regulator-ramp-delay = <7000>;
315 regulator-boot-on;
316 regulator-always-on;
317 };
318
319 /* VDD_DDR (1+R1/R2 = 2.105) */
320 reg_vdd_ddr: sw4 {
321 regulator-name = "vddddr";
322 regulator-min-microvolt = <868310>;
323 regulator-max-microvolt = <1684000>;
324 lltc,fb-voltage-divider = <221000 200000>;
325 regulator-ramp-delay = <7000>;
326 regulator-boot-on;
327 regulator-always-on;
328 };
329
330 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
331 reg_2p5v: ldo2 {
332 regulator-name = "vdd2p5";
333 regulator-min-microvolt = <2490375>;
334 regulator-max-microvolt = <2490375>;
335 lltc,fb-voltage-divider = <487000 200000>;
336 regulator-boot-on;
337 regulator-always-on;
338 };
339
340 /* VDD_HIGH (1+R1/R2 = 4.17) */
341 reg_3p0v: ldo4 {
342 regulator-name = "vdd3p0";
343 regulator-min-microvolt = <3023250>;
344 regulator-max-microvolt = <3023250>;
345 lltc,fb-voltage-divider = <634000 200000>;
346 regulator-boot-on;
347 regulator-always-on;
348 };
349 };
350 };
351};
352
353&i2c3 {
354 clock-frequency = <100000>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_i2c3>;
357 status = "okay";
358};
359
360&pcie {
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_pcie>;
363 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
364 status = "okay";
365};
366
367&pwm2 {
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
370 status = "disabled";
371};
372
373&pwm3 {
374 pinctrl-names = "default";
375 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
376 status = "disabled";
377};
378
379&uart2 {
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_uart2>;
382 status = "okay";
383};
384
385&uart3 {
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_uart3>;
388 status = "okay";
389};
390
391&uart5 {
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_uart5>;
394 status = "okay"; };
395
396&usbh1 {
397 status = "okay";
398};
399
400&usbotg {
401 vbus-supply = <&reg_5p0v>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_usbotg>;
404 disable-over-current;
Tim Harvey13acc632021-03-01 14:33:31 -0800[diff] [blame]405 dr_mode = "otg";
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]406 status = "okay";
407};
408
409&wdog1 {
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_wdog>;
412 fsl,ext-reset-output;
413};
414
415&iomuxc {
416 pinctrl_gpio_leds: gpioledsgrp {
417 fsl,pins = <
418 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
419 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
420 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
421 >;
422 };
423
424 pinctrl_gpmi_nand: gpminandgrp {
425 fsl,pins = <
426 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
427 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
428 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
429 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
430 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
431 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
432 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
433 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
434 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
435 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
436 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
437 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
438 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
439 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
440 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
441 >;
442 };
443
444 pinctrl_i2c1: i2c1grp {
445 fsl,pins = <
446 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
447 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
448 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
449 >;
450 };
451
452 pinctrl_i2c2: i2c2grp {
453 fsl,pins = <
454 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
455 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
456 >;
457 };
458
459 pinctrl_i2c3: i2c3grp {
460 fsl,pins = <
461 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
462 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
463 >;
464 };
465
466 pinctrl_pcie: pciegrp {
467 fsl,pins = <
468 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
469 >;
470 };
471
472 pinctrl_pmic: pmicgrp {
473 fsl,pins = <
474 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
475 >;
476 };
477
478 pinctrl_pwm2: pwm2grp {
479 fsl,pins = <
480 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
481 >;
482 };
483
484 pinctrl_pwm3: pwm3grp {
485 fsl,pins = <
486 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
487 >;
488 };
489
490 pinctrl_uart2: uart2grp {
491 fsl,pins = <
492 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
493 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
494 >;
495 };
496
497 pinctrl_uart3: uart3grp {
498 fsl,pins = <
499 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
500 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
501 >;
502 };
503
504 pinctrl_uart5: uart5grp {
505 fsl,pins = <
506 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
507 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
508 >;
509 };
510
511 pinctrl_usbotg: usbotggrp {
512 fsl,pins = <
513 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059
514 >;
515 };
516
517 pinctrl_wdog: wdoggrp {
518 fsl,pins = <
519 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
520 >;
521 };
522};