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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotard791651e2017-12-12 09:49:33 +01002/*
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
Patrice Chotard7ccaa312021-01-04 17:00:56 +01004 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
Patrice Chotard791651e2017-12-12 09:49:33 +01005 */
6
7#include <dt-bindings/memory/stm32-sdram.h>
8/{
9 clocks {
10 u-boot,dm-pre-reloc;
11 };
12
13 aliases {
14 /* Aliases for gpios so as to use sequence */
15 gpio0 = &gpioa;
16 gpio1 = &gpiob;
17 gpio2 = &gpioc;
18 gpio3 = &gpiod;
19 gpio4 = &gpioe;
20 gpio5 = &gpiof;
21 gpio6 = &gpiog;
22 gpio7 = &gpioh;
23 gpio8 = &gpioi;
24 gpio9 = &gpioj;
25 gpio10 = &gpiok;
26 };
27
28 soc {
29 u-boot,dm-pre-reloc;
30 pin-controller {
31 u-boot,dm-pre-reloc;
32 };
33
34 fmc: fmc@A0000000 {
35 compatible = "st,stm32-fmc";
36 reg = <0xA0000000 0x1000>;
37 clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
38 pinctrl-0 = <&fmc_pins>;
39 pinctrl-names = "default";
Radoslaw Pietrzyk246a5e52018-05-16 17:27:11 +020040 st,syscfg = <&syscfg>;
41 st,swp_fmc = <1>;
Patrice Chotard791651e2017-12-12 09:49:33 +010042 u-boot,dm-pre-reloc;
43
44 /*
45 * Memory configuration from sdram datasheet
46 * IS42S16400J
47 */
48 bank1: bank@1 {
49 st,sdram-control = /bits/ 8 <NO_COL_8
50 NO_ROW_12
51 MWIDTH_16
52 BANKS_4
53 CAS_3
54 SDCLK_2
55 RD_BURST_EN
56 RD_PIPE_DL_0>;
57 st,sdram-timing = /bits/ 8 <TMRD_3
58 TXSR_7
59 TRAS_4
60 TRC_6
61 TWR_2
62 TRP_2 TRCD_2>;
63 st,sdram-refcount = < 1386 >;
64 };
65 };
66 };
67};
68
69&clk_hse {
70 u-boot,dm-pre-reloc;
71};
72
Patrice Chotard791651e2017-12-12 09:49:33 +010073&clk_i2s_ckin {
74 u-boot,dm-pre-reloc;
75};
76
Patrice Chotard933f84c2019-02-18 22:46:25 +010077&clk_lse {
Patrice Chotard791651e2017-12-12 09:49:33 +010078 u-boot,dm-pre-reloc;
79};
80
81&gpioa {
Patrice Chotard791651e2017-12-12 09:49:33 +010082 u-boot,dm-pre-reloc;
83};
84
85&gpiob {
Patrice Chotard791651e2017-12-12 09:49:33 +010086 u-boot,dm-pre-reloc;
87};
88
89&gpioc {
Patrice Chotard791651e2017-12-12 09:49:33 +010090 u-boot,dm-pre-reloc;
91};
92
93&gpiod {
Patrice Chotard791651e2017-12-12 09:49:33 +010094 u-boot,dm-pre-reloc;
95};
96
97&gpioe {
Patrice Chotard791651e2017-12-12 09:49:33 +010098 u-boot,dm-pre-reloc;
99};
100
101&gpiof {
Patrice Chotard791651e2017-12-12 09:49:33 +0100102 u-boot,dm-pre-reloc;
103};
104
105&gpiog {
Patrice Chotard791651e2017-12-12 09:49:33 +0100106 u-boot,dm-pre-reloc;
107};
108
109&gpioh {
Patrice Chotard791651e2017-12-12 09:49:33 +0100110 u-boot,dm-pre-reloc;
111};
112
113&gpioi {
Patrice Chotard791651e2017-12-12 09:49:33 +0100114 u-boot,dm-pre-reloc;
115};
116
117&gpioj {
Patrice Chotard791651e2017-12-12 09:49:33 +0100118 u-boot,dm-pre-reloc;
119};
120
121&gpiok {
Patrice Chotard791651e2017-12-12 09:49:33 +0100122 u-boot,dm-pre-reloc;
123};
124
125&pinctrl {
Patrice Chotard61c88ac2020-11-06 08:11:58 +0100126 usart1_pins_a: usart1-0 {
Patrice Chotard791651e2017-12-12 09:49:33 +0100127 u-boot,dm-pre-reloc;
128 pins1 {
129 u-boot,dm-pre-reloc;
130 };
131 pins2 {
132 u-boot,dm-pre-reloc;
133 };
134 };
135
136 fmc_pins: fmc@0 {
137 u-boot,dm-pre-reloc;
138 pins
139 {
140 pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
141 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
142 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
143 <STM32_PINMUX('E',15, AF12)>, /* D12 */
144 <STM32_PINMUX('E',14, AF12)>, /* D11 */
145 <STM32_PINMUX('E',13, AF12)>, /* D10 */
146 <STM32_PINMUX('E',12, AF12)>, /* D09 */
147 <STM32_PINMUX('E',11, AF12)>, /* D08 */
148 <STM32_PINMUX('E',10, AF12)>, /* D07 */
149 <STM32_PINMUX('E', 9, AF12)>, /* D06 */
150 <STM32_PINMUX('E', 8, AF12)>, /* D05 */
151 <STM32_PINMUX('E', 7, AF12)>, /* D04 */
152 <STM32_PINMUX('D', 1, AF12)>, /* D03 */
153 <STM32_PINMUX('D', 0, AF12)>, /* D02 */
154 <STM32_PINMUX('D',15, AF12)>, /* D01 */
155 <STM32_PINMUX('D',14, AF12)>, /* D00 */
156
157 <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
158 <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
159
160 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
161 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
162
163 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
164 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
165 <STM32_PINMUX('F',15, AF12)>, /* A09 */
166 <STM32_PINMUX('F',14, AF12)>, /* A08 */
167 <STM32_PINMUX('F',13, AF12)>, /* A07 */
168 <STM32_PINMUX('F',12, AF12)>, /* A06 */
169 <STM32_PINMUX('F', 5, AF12)>, /* A05 */
170 <STM32_PINMUX('F', 4, AF12)>, /* A04 */
171 <STM32_PINMUX('F', 3, AF12)>, /* A03 */
172 <STM32_PINMUX('F', 2, AF12)>, /* A02 */
173 <STM32_PINMUX('F', 1, AF12)>, /* A01 */
174 <STM32_PINMUX('F', 0, AF12)>, /* A00 */
175
176 <STM32_PINMUX('B', 6, AF12)>, /* SDNE1 */
177 <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
178 <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
179 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
180 <STM32_PINMUX('B', 5, AF12)>, /* SDCKE1 */
181 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK */
182 slew-rate = <2>;
183 u-boot,dm-pre-reloc;
184 };
185 };
186};
Patrice Chotard933f84c2019-02-18 22:46:25 +0100187
188&pwrcfg {
189 u-boot,dm-pre-reloc;
190};
191
192&rcc {
193 u-boot,dm-pre-reloc;
194};
Patrice Chotard18336292020-11-06 08:11:59 +0100195
196&timer5 {
197 u-boot,dm-pre-reloc;
198};