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Sergey Kubushync74b2102007-08-10 20:26:18 +02001/*
2 * Ethernet driver for TI TMS320DM644x (DaVinci) chips.
3 *
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
5 *
6 * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
7 * follows:
8 *
9 * ----------------------------------------------------------------------------
10 *
11 * dm644x_emac.c
12 *
13 * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
14 *
15 * Copyright (C) 2005 Texas Instruments.
16 *
17 * ----------------------------------------------------------------------------
18 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020019 * SPDX-License-Identifier: GPL-2.0+
Sergey Kubushync74b2102007-08-10 20:26:18 +020020 *
Sergey Kubushync74b2102007-08-10 20:26:18 +020021 * Modifications:
22 * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
23 * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
Sergey Kubushync74b2102007-08-10 20:26:18 +020024 */
25#include <common.h>
26#include <command.h>
27#include <net.h>
28#include <miiphy.h>
Ben Warren84535872009-05-26 00:34:07 -070029#include <malloc.h>
Jeroen Hofsteeee3fad82014-10-08 22:57:56 +020030#include <netdev.h>
Ilya Yanok2aa87202011-11-28 06:37:33 +000031#include <linux/compiler.h>
Sergey Kubushync74b2102007-08-10 20:26:18 +020032#include <asm/arch/emac_defs.h>
Nick Thompsond7e35432009-12-18 13:33:07 +000033#include <asm/io.h>
Ilya Yanok7c587d32011-11-28 06:37:29 +000034#include "davinci_emac.h"
Sergey Kubushync74b2102007-08-10 20:26:18 +020035
Sergey Kubushync74b2102007-08-10 20:26:18 +020036unsigned int emac_dbg = 0;
37#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
38
Ilya Yanok82b77212011-11-28 06:37:30 +000039#ifdef EMAC_HW_RAM_ADDR
40static inline unsigned long BD_TO_HW(unsigned long x)
41{
42 if (x == 0)
43 return 0;
44
45 return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR;
46}
47
48static inline unsigned long HW_TO_BD(unsigned long x)
49{
50 if (x == 0)
51 return 0;
52
53 return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR;
54}
55#else
56#define BD_TO_HW(x) (x)
57#define HW_TO_BD(x) (x)
58#endif
59
Nick Thompsond7e35432009-12-18 13:33:07 +000060#ifdef DAVINCI_EMAC_GIG_ENABLE
Manjunath Hadlifb1d6332011-10-13 03:40:55 +000061#define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr)
Nick Thompsond7e35432009-12-18 13:33:07 +000062#else
Manjunath Hadlifb1d6332011-10-13 03:40:55 +000063#define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
Nick Thompsond7e35432009-12-18 13:33:07 +000064#endif
65
Heiko Schocher882ecfa2011-11-01 20:00:27 +000066#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
67#define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
68 EMAC_MDIO_CLOCK_FREQ) - 1)
69#endif
70
Sandeep Paulrajfcaac582008-08-31 00:39:46 +020071static void davinci_eth_mdio_enable(void);
Sergey Kubushync74b2102007-08-10 20:26:18 +020072
73static int gen_init_phy(int phy_addr);
74static int gen_is_phy_connected(int phy_addr);
75static int gen_get_link_speed(int phy_addr);
76static int gen_auto_negotiate(int phy_addr);
77
Sergey Kubushync74b2102007-08-10 20:26:18 +020078void eth_mdio_enable(void)
79{
Sandeep Paulrajfcaac582008-08-31 00:39:46 +020080 davinci_eth_mdio_enable();
Sergey Kubushync74b2102007-08-10 20:26:18 +020081}
Sergey Kubushync74b2102007-08-10 20:26:18 +020082
Sergey Kubushync74b2102007-08-10 20:26:18 +020083/* EMAC Addresses */
84static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
85static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
86static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
87
88/* EMAC descriptors */
89static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
90static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
91static volatile emac_desc *emac_rx_active_head = 0;
92static volatile emac_desc *emac_rx_active_tail = 0;
93static int emac_rx_queue_active = 0;
94
95/* Receive packet buffers */
Ilya Yanok2aa87202011-11-28 06:37:33 +000096static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE]
97 __aligned(ARCH_DMA_MINALIGN);
Sergey Kubushync74b2102007-08-10 20:26:18 +020098
Heiko Schocherdc02bad2011-11-15 10:00:04 -050099#ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
100#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3
101#endif
Sergey Kubushync74b2102007-08-10 20:26:18 +0200102
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000103/* PHY address for a discovered PHY (0xff - not found) */
Heiko Schocherdc02bad2011-11-15 10:00:04 -0500104static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000105
106/* number of PHY found active */
107static u_int8_t num_phy;
108
Heiko Schocherdc02bad2011-11-15 10:00:04 -0500109phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
Sergey Kubushync74b2102007-08-10 20:26:18 +0200110
Ilya Yanok2aa87202011-11-28 06:37:33 +0000111static inline void davinci_flush_rx_descs(void)
112{
113 /* flush the whole RX descs area */
114 flush_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE,
115 EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
116}
117
118static inline void davinci_invalidate_rx_descs(void)
119{
120 /* invalidate the whole RX descs area */
121 invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE,
122 EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
123}
124
125static inline void davinci_flush_desc(emac_desc *desc)
126{
127 flush_dcache_range((unsigned long)desc,
128 (unsigned long)desc + sizeof(*desc));
129}
130
Ben Gardiner7b37a272010-09-23 09:58:43 -0400131static int davinci_eth_set_mac_addr(struct eth_device *dev)
132{
133 unsigned long mac_hi;
134 unsigned long mac_lo;
135
136 /*
137 * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
138 * receive)
139 * Using channel 0 only - other channels are disabled
140 * */
141 writel(0, &adap_emac->MACINDEX);
142 mac_hi = (dev->enetaddr[3] << 24) |
143 (dev->enetaddr[2] << 16) |
144 (dev->enetaddr[1] << 8) |
145 (dev->enetaddr[0]);
146 mac_lo = (dev->enetaddr[5] << 8) |
147 (dev->enetaddr[4]);
148
149 writel(mac_hi, &adap_emac->MACADDRHI);
150#if defined(DAVINCI_EMAC_VERSION2)
151 writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
152 &adap_emac->MACADDRLO);
153#else
154 writel(mac_lo, &adap_emac->MACADDRLO);
155#endif
156
157 writel(0, &adap_emac->MACHASH1);
158 writel(0, &adap_emac->MACHASH2);
159
160 /* Set source MAC address - REQUIRED */
161 writel(mac_hi, &adap_emac->MACSRCADDRHI);
162 writel(mac_lo, &adap_emac->MACSRCADDRLO);
163
164
165 return 0;
166}
167
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200168static void davinci_eth_mdio_enable(void)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200169{
170 u_int32_t clkdiv;
171
Heiko Schocher882ecfa2011-11-01 20:00:27 +0000172 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200173
Nick Thompsond7e35432009-12-18 13:33:07 +0000174 writel((clkdiv & 0xff) |
175 MDIO_CONTROL_ENABLE |
176 MDIO_CONTROL_FAULT |
177 MDIO_CONTROL_FAULT_ENABLE,
178 &adap_mdio->CONTROL);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200179
Nick Thompsond7e35432009-12-18 13:33:07 +0000180 while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
181 ;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200182}
183
184/*
185 * Tries to find an active connected PHY. Returns 1 if address if found.
186 * If no active PHY (or more than one PHY) found returns 0.
187 * Sets active_phy_addr variable.
188 */
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200189static int davinci_eth_phy_detect(void)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200190{
191 u_int32_t phy_act_state;
192 int i;
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000193 int j;
194 unsigned int count = 0;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200195
Heiko Schocherdc02bad2011-11-15 10:00:04 -0500196 for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
197 active_phy_addr[i] = 0xff;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200198
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000199 udelay(1000);
200 phy_act_state = readl(&adap_mdio->ALIVE);
201
Nick Thompsond7e35432009-12-18 13:33:07 +0000202 if (phy_act_state == 0)
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000203 return 0; /* No active PHYs */
Sergey Kubushync74b2102007-08-10 20:26:18 +0200204
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200205 debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200206
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000207 for (i = 0, j = 0; i < 32; i++)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200208 if (phy_act_state & (1 << i)) {
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000209 count++;
Prabhakar Ladb6090092011-11-17 02:53:23 +0000210 if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
Heiko Schocherdc02bad2011-11-15 10:00:04 -0500211 active_phy_addr[j++] = i;
212 } else {
213 printf("%s: to many PHYs detected.\n",
214 __func__);
215 count = 0;
216 break;
217 }
Sergey Kubushync74b2102007-08-10 20:26:18 +0200218 }
Sergey Kubushync74b2102007-08-10 20:26:18 +0200219
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000220 num_phy = count;
221
222 return count;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200223}
224
225
226/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200227int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200228{
229 int tmp;
230
Nick Thompsond7e35432009-12-18 13:33:07 +0000231 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
232 ;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200233
Nick Thompsond7e35432009-12-18 13:33:07 +0000234 writel(MDIO_USERACCESS0_GO |
235 MDIO_USERACCESS0_WRITE_READ |
236 ((reg_num & 0x1f) << 21) |
237 ((phy_addr & 0x1f) << 16),
238 &adap_mdio->USERACCESS0);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200239
240 /* Wait for command to complete */
Nick Thompsond7e35432009-12-18 13:33:07 +0000241 while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
242 ;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200243
244 if (tmp & MDIO_USERACCESS0_ACK) {
245 *data = tmp & 0xffff;
246 return(1);
247 }
248
249 *data = -1;
250 return(0);
251}
252
253/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200254int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200255{
256
Nick Thompsond7e35432009-12-18 13:33:07 +0000257 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
258 ;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200259
Nick Thompsond7e35432009-12-18 13:33:07 +0000260 writel(MDIO_USERACCESS0_GO |
261 MDIO_USERACCESS0_WRITE_WRITE |
262 ((reg_num & 0x1f) << 21) |
263 ((phy_addr & 0x1f) << 16) |
264 (data & 0xffff),
265 &adap_mdio->USERACCESS0);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200266
267 /* Wait for command to complete */
Nick Thompsond7e35432009-12-18 13:33:07 +0000268 while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
269 ;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200270
271 return(1);
272}
273
274/* PHY functions for a generic PHY */
275static int gen_init_phy(int phy_addr)
276{
277 int ret = 1;
278
279 if (gen_get_link_speed(phy_addr)) {
280 /* Try another time */
281 ret = gen_get_link_speed(phy_addr);
282 }
283
284 return(ret);
285}
286
287static int gen_is_phy_connected(int phy_addr)
288{
289 u_int16_t dummy;
290
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000291 return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
292}
293
294static int get_active_phy(void)
295{
296 int i;
297
298 for (i = 0; i < num_phy; i++)
299 if (phy[i].get_link_speed(active_phy_addr[i]))
300 return i;
301
302 return -1; /* Return error if no link */
Sergey Kubushync74b2102007-08-10 20:26:18 +0200303}
304
305static int gen_get_link_speed(int phy_addr)
306{
307 u_int16_t tmp;
308
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500309 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
310 (tmp & 0x04)) {
311#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
312 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
Ben Gardiner7d2fade2011-01-11 14:48:17 -0500313 davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500314
315 /* Speed doesn't matter, there is no setting for it in EMAC. */
Ben Gardiner7d2fade2011-01-11 14:48:17 -0500316 if (tmp & (LPA_100FULL | LPA_10FULL)) {
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500317 /* set EMAC for Full Duplex */
318 writel(EMAC_MACCONTROL_MIIEN_ENABLE |
319 EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
320 &adap_emac->MACCONTROL);
321 } else {
322 /*set EMAC for Half Duplex */
323 writel(EMAC_MACCONTROL_MIIEN_ENABLE,
324 &adap_emac->MACCONTROL);
325 }
326
Ben Gardiner7d2fade2011-01-11 14:48:17 -0500327 if (tmp & (LPA_100FULL | LPA_100HALF))
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500328 writel(readl(&adap_emac->MACCONTROL) |
329 EMAC_MACCONTROL_RMIISPEED_100,
330 &adap_emac->MACCONTROL);
331 else
332 writel(readl(&adap_emac->MACCONTROL) &
333 ~EMAC_MACCONTROL_RMIISPEED_100,
334 &adap_emac->MACCONTROL);
335#endif
Sergey Kubushync74b2102007-08-10 20:26:18 +0200336 return(1);
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500337 }
Sergey Kubushync74b2102007-08-10 20:26:18 +0200338
339 return(0);
340}
341
342static int gen_auto_negotiate(int phy_addr)
343{
344 u_int16_t tmp;
Manjunath Hadlicc4bd472011-10-13 03:40:53 +0000345 u_int16_t val;
346 unsigned long cntr = 0;
347
348 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
349 return 0;
350
351 val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
352 BMCR_SPEED100;
353 davinci_eth_phy_write(phy_addr, MII_BMCR, val);
354
355 if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
356 return 0;
357
358 val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
359 ADVERTISE_10HALF);
360 davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200361
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500362 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
Sergey Kubushync74b2102007-08-10 20:26:18 +0200363 return(0);
364
365 /* Restart Auto_negotiation */
Manjunath Hadlicc4bd472011-10-13 03:40:53 +0000366 tmp |= BMCR_ANRESTART;
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500367 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200368
369 /*check AutoNegotiate complete */
Manjunath Hadlicc4bd472011-10-13 03:40:53 +0000370 do {
371 udelay(40000);
372 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
373 return 0;
374
375 if (tmp & BMSR_ANEGCOMPLETE)
376 break;
377
378 cntr++;
379 } while (cntr < 200);
380
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500381 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
Sergey Kubushync74b2102007-08-10 20:26:18 +0200382 return(0);
383
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500384 if (!(tmp & BMSR_ANEGCOMPLETE))
Sergey Kubushync74b2102007-08-10 20:26:18 +0200385 return(0);
386
387 return(gen_get_link_speed(phy_addr));
388}
389/* End of generic PHY functions */
390
391
Wolfgang Denkafaac862007-08-12 14:27:39 +0200392#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Mike Frysinger5700bb62010-07-27 18:35:08 -0400393static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200394{
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200395 return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200396}
397
Mike Frysinger5700bb62010-07-27 18:35:08 -0400398static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200399{
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200400 return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200401}
Sergey Kubushync74b2102007-08-10 20:26:18 +0200402#endif
403
Manjunath Hadlifb1d6332011-10-13 03:40:55 +0000404static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
Nick Thompsond7e35432009-12-18 13:33:07 +0000405{
406 u_int16_t data;
407
Manjunath Hadlifb1d6332011-10-13 03:40:55 +0000408 if (davinci_eth_phy_read(phy_addr, 0, &data)) {
Nick Thompsond7e35432009-12-18 13:33:07 +0000409 if (data & (1 << 6)) { /* speed selection MSB */
410 /*
411 * Check if link detected is giga-bit
412 * If Gigabit mode detected, enable gigbit in MAC
413 */
Sandeep Paulraj4b9b9e72010-12-28 14:37:33 -0500414 writel(readl(&adap_emac->MACCONTROL) |
415 EMAC_MACCONTROL_GIGFORCE |
416 EMAC_MACCONTROL_GIGABIT_ENABLE,
417 &adap_emac->MACCONTROL);
Nick Thompsond7e35432009-12-18 13:33:07 +0000418 }
419 }
420}
Sergey Kubushync74b2102007-08-10 20:26:18 +0200421
422/* Eth device open */
Ben Warren84535872009-05-26 00:34:07 -0700423static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200424{
425 dv_reg_p addr;
426 u_int32_t clkdiv, cnt;
427 volatile emac_desc *rx_desc;
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000428 int index;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200429
430 debug_emac("+ emac_open\n");
431
432 /* Reset EMAC module and disable interrupts in wrapper */
Nick Thompsond7e35432009-12-18 13:33:07 +0000433 writel(1, &adap_emac->SOFTRESET);
434 while (readl(&adap_emac->SOFTRESET) != 0)
435 ;
436#if defined(DAVINCI_EMAC_VERSION2)
437 writel(1, &adap_ewrap->softrst);
438 while (readl(&adap_ewrap->softrst) != 0)
439 ;
440#else
441 writel(0, &adap_ewrap->EWCTL);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200442 for (cnt = 0; cnt < 5; cnt++) {
Nick Thompsond7e35432009-12-18 13:33:07 +0000443 clkdiv = readl(&adap_ewrap->EWCTL);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200444 }
Nick Thompsond7e35432009-12-18 13:33:07 +0000445#endif
Sergey Kubushync74b2102007-08-10 20:26:18 +0200446
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500447#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
448 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
449 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
450 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
451 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
452#endif
Sergey Kubushync74b2102007-08-10 20:26:18 +0200453 rx_desc = emac_rx_desc;
454
Nick Thompsond7e35432009-12-18 13:33:07 +0000455 writel(1, &adap_emac->TXCONTROL);
456 writel(1, &adap_emac->RXCONTROL);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200457
Ben Gardiner7b37a272010-09-23 09:58:43 -0400458 davinci_eth_set_mac_addr(dev);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200459
460 /* Set DMA 8 TX / 8 RX Head pointers to 0 */
461 addr = &adap_emac->TX0HDP;
462 for(cnt = 0; cnt < 16; cnt++)
Nick Thompsond7e35432009-12-18 13:33:07 +0000463 writel(0, addr++);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200464
465 addr = &adap_emac->RX0HDP;
466 for(cnt = 0; cnt < 16; cnt++)
Nick Thompsond7e35432009-12-18 13:33:07 +0000467 writel(0, addr++);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200468
469 /* Clear Statistics (do this before setting MacControl register) */
470 addr = &adap_emac->RXGOODFRAMES;
471 for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
Nick Thompsond7e35432009-12-18 13:33:07 +0000472 writel(0, addr++);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200473
474 /* No multicast addressing */
Nick Thompsond7e35432009-12-18 13:33:07 +0000475 writel(0, &adap_emac->MACHASH1);
476 writel(0, &adap_emac->MACHASH2);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200477
478 /* Create RX queue and set receive process in place */
479 emac_rx_active_head = emac_rx_desc;
480 for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
Ilya Yanok82b77212011-11-28 06:37:30 +0000481 rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1));
Ilya Yanok2aa87202011-11-28 06:37:33 +0000482 rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE];
Sergey Kubushync74b2102007-08-10 20:26:18 +0200483 rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
484 rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
485 rx_desc++;
486 }
487
Nick Thompsond7e35432009-12-18 13:33:07 +0000488 /* Finalize the rx desc list */
Sergey Kubushync74b2102007-08-10 20:26:18 +0200489 rx_desc--;
490 rx_desc->next = 0;
491 emac_rx_active_tail = rx_desc;
492 emac_rx_queue_active = 1;
493
Ilya Yanok2aa87202011-11-28 06:37:33 +0000494 davinci_flush_rx_descs();
495
Sergey Kubushync74b2102007-08-10 20:26:18 +0200496 /* Enable TX/RX */
Nick Thompsond7e35432009-12-18 13:33:07 +0000497 writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
498 writel(0, &adap_emac->RXBUFFEROFFSET);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200499
Nick Thompsond7e35432009-12-18 13:33:07 +0000500 /*
501 * No fancy configs - Use this for promiscous debug
502 * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
503 */
504 writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200505
506 /* Enable ch 0 only */
Nick Thompsond7e35432009-12-18 13:33:07 +0000507 writel(1, &adap_emac->RXUNICASTSET);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200508
509 /* Enable MII interface and Full duplex mode */
Ilya Yanok80deda52011-11-28 06:37:34 +0000510#if defined(CONFIG_SOC_DA8XX) || \
511 (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII))
Nick Thompsond7e35432009-12-18 13:33:07 +0000512 writel((EMAC_MACCONTROL_MIIEN_ENABLE |
513 EMAC_MACCONTROL_FULLDUPLEX_ENABLE |
514 EMAC_MACCONTROL_RMIISPEED_100),
515 &adap_emac->MACCONTROL);
516#else
517 writel((EMAC_MACCONTROL_MIIEN_ENABLE |
518 EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
519 &adap_emac->MACCONTROL);
520#endif
Sergey Kubushync74b2102007-08-10 20:26:18 +0200521
522 /* Init MDIO & get link state */
Heiko Schocher882ecfa2011-11-01 20:00:27 +0000523 clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
Nick Thompsond7e35432009-12-18 13:33:07 +0000524 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
525 &adap_mdio->CONTROL);
526
527 /* We need to wait for MDIO to start */
528 udelay(1000);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200529
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000530 index = get_active_phy();
531 if (index == -1)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200532 return(0);
533
Manjunath Hadlifb1d6332011-10-13 03:40:55 +0000534 emac_gigabit_enable(active_phy_addr[index]);
Nick Thompsond7e35432009-12-18 13:33:07 +0000535
Sergey Kubushync74b2102007-08-10 20:26:18 +0200536 /* Start receive process */
Ilya Yanok82b77212011-11-28 06:37:30 +0000537 writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200538
539 debug_emac("- emac_open\n");
540
541 return(1);
542}
543
544/* EMAC Channel Teardown */
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200545static void davinci_eth_ch_teardown(int ch)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200546{
547 dv_reg dly = 0xff;
548 dv_reg cnt;
549
550 debug_emac("+ emac_ch_teardown\n");
551
552 if (ch == EMAC_CH_TX) {
553 /* Init TX channel teardown */
Nagabhushana Netagunteba511f72011-09-03 22:20:33 -0400554 writel(0, &adap_emac->TXTEARDOWN);
Nick Thompsond7e35432009-12-18 13:33:07 +0000555 do {
556 /*
557 * Wait here for Tx teardown completion interrupt to
558 * occur. Note: A task delay can be called here to pend
559 * rather than occupying CPU cycles - anyway it has
560 * been found that teardown takes very few cpu cycles
561 * and does not affect functionality
562 */
563 dly--;
564 udelay(1);
565 if (dly == 0)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200566 break;
Nick Thompsond7e35432009-12-18 13:33:07 +0000567 cnt = readl(&adap_emac->TX0CP);
568 } while (cnt != 0xfffffffc);
569 writel(cnt, &adap_emac->TX0CP);
570 writel(0, &adap_emac->TX0HDP);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200571 } else {
572 /* Init RX channel teardown */
Nagabhushana Netagunteba511f72011-09-03 22:20:33 -0400573 writel(0, &adap_emac->RXTEARDOWN);
Nick Thompsond7e35432009-12-18 13:33:07 +0000574 do {
575 /*
576 * Wait here for Rx teardown completion interrupt to
577 * occur. Note: A task delay can be called here to pend
578 * rather than occupying CPU cycles - anyway it has
579 * been found that teardown takes very few cpu cycles
580 * and does not affect functionality
581 */
582 dly--;
583 udelay(1);
584 if (dly == 0)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200585 break;
Nick Thompsond7e35432009-12-18 13:33:07 +0000586 cnt = readl(&adap_emac->RX0CP);
587 } while (cnt != 0xfffffffc);
588 writel(cnt, &adap_emac->RX0CP);
589 writel(0, &adap_emac->RX0HDP);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200590 }
591
592 debug_emac("- emac_ch_teardown\n");
593}
594
595/* Eth device close */
Ben Warren84535872009-05-26 00:34:07 -0700596static void davinci_eth_close(struct eth_device *dev)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200597{
598 debug_emac("+ emac_close\n");
599
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200600 davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
Jeroen Hofstee0b830192015-06-07 17:30:38 +0200601 if (readl(&adap_emac->RXCONTROL) & 1)
602 davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
Sergey Kubushync74b2102007-08-10 20:26:18 +0200603
604 /* Reset EMAC module and disable interrupts in wrapper */
Nick Thompsond7e35432009-12-18 13:33:07 +0000605 writel(1, &adap_emac->SOFTRESET);
606#if defined(DAVINCI_EMAC_VERSION2)
607 writel(1, &adap_ewrap->softrst);
608#else
609 writel(0, &adap_ewrap->EWCTL);
610#endif
Sergey Kubushync74b2102007-08-10 20:26:18 +0200611
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500612#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
613 defined(CONFIG_MACH_DAVINCI_DA850_EVM)
614 adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
615 adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
616 adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
617#endif
Sergey Kubushync74b2102007-08-10 20:26:18 +0200618 debug_emac("- emac_close\n");
Sergey Kubushync74b2102007-08-10 20:26:18 +0200619}
620
621static int tx_send_loop = 0;
622
623/*
624 * This function sends a single packet on the network and returns
625 * positive number (number of bytes transmitted) or negative for error
626 */
Ben Warren84535872009-05-26 00:34:07 -0700627static int davinci_eth_send_packet (struct eth_device *dev,
Joe Hershbergerbbcdefb2012-05-21 05:54:01 +0000628 void *packet, int length)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200629{
630 int ret_status = -1;
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000631 int index;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200632 tx_send_loop = 0;
633
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000634 index = get_active_phy();
635 if (index == -1) {
636 printf(" WARN: emac_send_packet: No link\n");
Sergey Kubushync74b2102007-08-10 20:26:18 +0200637 return (ret_status);
638 }
639
Manjunath Hadlifb1d6332011-10-13 03:40:55 +0000640 emac_gigabit_enable(active_phy_addr[index]);
Nick Thompsond7e35432009-12-18 13:33:07 +0000641
Sergey Kubushync74b2102007-08-10 20:26:18 +0200642 /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200643 if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
Sergey Kubushync74b2102007-08-10 20:26:18 +0200644 length = EMAC_MIN_ETHERNET_PKT_SIZE;
645 }
646
647 /* Populate the TX descriptor */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200648 emac_tx_desc->next = 0;
649 emac_tx_desc->buffer = (u_int8_t *) packet;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200650 emac_tx_desc->buff_off_len = (length & 0xffff);
651 emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200652 EMAC_CPPI_SOP_BIT |
653 EMAC_CPPI_OWNERSHIP_BIT |
654 EMAC_CPPI_EOP_BIT);
Ilya Yanok2aa87202011-11-28 06:37:33 +0000655
656 flush_dcache_range((unsigned long)packet,
657 (unsigned long)packet + length);
658 davinci_flush_desc(emac_tx_desc);
659
Sergey Kubushync74b2102007-08-10 20:26:18 +0200660 /* Send the packet */
Ilya Yanok82b77212011-11-28 06:37:30 +0000661 writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200662
663 /* Wait for packet to complete or link down */
664 while (1) {
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000665 if (!phy[index].get_link_speed(active_phy_addr[index])) {
Sandeep Paulrajfcaac582008-08-31 00:39:46 +0200666 davinci_eth_ch_teardown (EMAC_CH_TX);
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200667 return (ret_status);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200668 }
Nick Thompsond7e35432009-12-18 13:33:07 +0000669
Manjunath Hadlifb1d6332011-10-13 03:40:55 +0000670 emac_gigabit_enable(active_phy_addr[index]);
Nick Thompsond7e35432009-12-18 13:33:07 +0000671
672 if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200673 ret_status = length;
674 break;
675 }
676 tx_send_loop++;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200677 }
678
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200679 return (ret_status);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200680}
681
682/*
683 * This function handles receipt of a packet from the network
684 */
Ben Warren84535872009-05-26 00:34:07 -0700685static int davinci_eth_rcv_packet (struct eth_device *dev)
Sergey Kubushync74b2102007-08-10 20:26:18 +0200686{
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200687 volatile emac_desc *rx_curr_desc;
688 volatile emac_desc *curr_desc;
689 volatile emac_desc *tail_desc;
690 int status, ret = -1;
Sergey Kubushync74b2102007-08-10 20:26:18 +0200691
Ilya Yanok2aa87202011-11-28 06:37:33 +0000692 davinci_invalidate_rx_descs();
693
Sergey Kubushync74b2102007-08-10 20:26:18 +0200694 rx_curr_desc = emac_rx_active_head;
695 status = rx_curr_desc->pkt_flag_len;
696 if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200697 if (status & EMAC_CPPI_RX_ERROR_FRAME) {
698 /* Error in packet - discard it and requeue desc */
699 printf ("WARN: emac_rcv_pkt: Error in packet\n");
Sergey Kubushync74b2102007-08-10 20:26:18 +0200700 } else {
Ilya Yanok2aa87202011-11-28 06:37:33 +0000701 unsigned long tmp = (unsigned long)rx_curr_desc->buffer;
702
703 invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE);
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500704 net_process_received_packet(
705 rx_curr_desc->buffer,
706 rx_curr_desc->buff_off_len & 0xffff);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200707 ret = rx_curr_desc->buff_off_len & 0xffff;
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200708 }
Sergey Kubushync74b2102007-08-10 20:26:18 +0200709
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200710 /* Ack received packet descriptor */
Ilya Yanok82b77212011-11-28 06:37:30 +0000711 writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP);
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200712 curr_desc = rx_curr_desc;
713 emac_rx_active_head =
Ilya Yanok82b77212011-11-28 06:37:30 +0000714 (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next));
Sergey Kubushync74b2102007-08-10 20:26:18 +0200715
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200716 if (status & EMAC_CPPI_EOQ_BIT) {
717 if (emac_rx_active_head) {
Ilya Yanok82b77212011-11-28 06:37:30 +0000718 writel(BD_TO_HW((ulong)emac_rx_active_head),
Nick Thompsond7e35432009-12-18 13:33:07 +0000719 &adap_emac->RX0HDP);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200720 } else {
721 emac_rx_queue_active = 0;
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200722 printf ("INFO:emac_rcv_packet: RX Queue not active\n");
Sergey Kubushync74b2102007-08-10 20:26:18 +0200723 }
724 }
725
726 /* Recycle RX descriptor */
727 rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
728 rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
729 rx_curr_desc->next = 0;
Ilya Yanok2aa87202011-11-28 06:37:33 +0000730 davinci_flush_desc(rx_curr_desc);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200731
732 if (emac_rx_active_head == 0) {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200733 printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
Sergey Kubushync74b2102007-08-10 20:26:18 +0200734 emac_rx_active_head = curr_desc;
735 emac_rx_active_tail = curr_desc;
736 if (emac_rx_queue_active != 0) {
Ilya Yanok82b77212011-11-28 06:37:30 +0000737 writel(BD_TO_HW((ulong)emac_rx_active_head),
Nick Thompsond7e35432009-12-18 13:33:07 +0000738 &adap_emac->RX0HDP);
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200739 printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
Sergey Kubushync74b2102007-08-10 20:26:18 +0200740 emac_rx_queue_active = 1;
741 }
742 } else {
743 tail_desc = emac_rx_active_tail;
744 emac_rx_active_tail = curr_desc;
Ilya Yanok82b77212011-11-28 06:37:30 +0000745 tail_desc->next = BD_TO_HW((ulong) curr_desc);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200746 status = tail_desc->pkt_flag_len;
747 if (status & EMAC_CPPI_EOQ_BIT) {
Ilya Yanok2aa87202011-11-28 06:37:33 +0000748 davinci_flush_desc(tail_desc);
Ilya Yanok82b77212011-11-28 06:37:30 +0000749 writel(BD_TO_HW((ulong)curr_desc),
Nick Thompsond7e35432009-12-18 13:33:07 +0000750 &adap_emac->RX0HDP);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200751 status &= ~EMAC_CPPI_EOQ_BIT;
752 tail_desc->pkt_flag_len = status;
753 }
Ilya Yanok2aa87202011-11-28 06:37:33 +0000754 davinci_flush_desc(tail_desc);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200755 }
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200756 return (ret);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200757 }
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200758 return (0);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200759}
760
Ben Warren8cc13c12009-04-27 23:19:10 -0700761/*
762 * This function initializes the emac hardware. It does NOT initialize
763 * EMAC modules power or pin multiplexors, that is done by board_init()
764 * much earlier in bootup process. Returns 1 on success, 0 otherwise.
765 */
Ben Warren84535872009-05-26 00:34:07 -0700766int davinci_emac_initialize(void)
Ben Warren8cc13c12009-04-27 23:19:10 -0700767{
768 u_int32_t phy_id;
769 u_int16_t tmp;
770 int i;
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000771 int ret;
Ben Warren84535872009-05-26 00:34:07 -0700772 struct eth_device *dev;
773
774 dev = malloc(sizeof *dev);
775
776 if (dev == NULL)
777 return -1;
778
779 memset(dev, 0, sizeof *dev);
Sandeep Paulraj2a7d6032010-12-28 14:42:27 -0500780 sprintf(dev->name, "DaVinci-EMAC");
Ben Warren84535872009-05-26 00:34:07 -0700781
782 dev->iobase = 0;
783 dev->init = davinci_eth_open;
784 dev->halt = davinci_eth_close;
785 dev->send = davinci_eth_send_packet;
786 dev->recv = davinci_eth_rcv_packet;
Ben Gardiner7b37a272010-09-23 09:58:43 -0400787 dev->write_hwaddr = davinci_eth_set_mac_addr;
Ben Warren84535872009-05-26 00:34:07 -0700788
789 eth_register(dev);
Sergey Kubushync74b2102007-08-10 20:26:18 +0200790
Ben Warren8cc13c12009-04-27 23:19:10 -0700791 davinci_eth_mdio_enable();
792
Heiko Schocher19fdf9a2011-09-14 19:37:42 +0000793 /* let the EMAC detect the PHYs */
794 udelay(5000);
795
Ben Warren8cc13c12009-04-27 23:19:10 -0700796 for (i = 0; i < 256; i++) {
Nick Thompsond7e35432009-12-18 13:33:07 +0000797 if (readl(&adap_mdio->ALIVE))
Ben Warren8cc13c12009-04-27 23:19:10 -0700798 break;
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000799 udelay(1000);
Ben Warren8cc13c12009-04-27 23:19:10 -0700800 }
801
802 if (i >= 256) {
803 printf("No ETH PHY detected!!!\n");
804 return(0);
805 }
806
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000807 /* Find if PHY(s) is/are connected */
808 ret = davinci_eth_phy_detect();
809 if (!ret)
Ben Warren8cc13c12009-04-27 23:19:10 -0700810 return(0);
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000811 else
Heiko Schocherdc02bad2011-11-15 10:00:04 -0500812 debug_emac(" %d ETH PHY detected\n", ret);
Ben Warren8cc13c12009-04-27 23:19:10 -0700813
814 /* Get PHY ID and initialize phy_ops for a detected PHY */
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000815 for (i = 0; i < num_phy; i++) {
816 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
817 &tmp)) {
818 active_phy_addr[i] = 0xff;
819 continue;
820 }
Ben Warren8cc13c12009-04-27 23:19:10 -0700821
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000822 phy_id = (tmp << 16) & 0xffff0000;
Ben Warren8cc13c12009-04-27 23:19:10 -0700823
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000824 if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
825 &tmp)) {
826 active_phy_addr[i] = 0xff;
827 continue;
828 }
Ben Warren8cc13c12009-04-27 23:19:10 -0700829
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000830 phy_id |= tmp & 0x0000ffff;
Ben Warren8cc13c12009-04-27 23:19:10 -0700831
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000832 switch (phy_id) {
Ilya Yanok918588c2011-11-28 06:37:31 +0000833#ifdef PHY_KSZ8873
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000834 case PHY_KSZ8873:
835 sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
836 active_phy_addr[i]);
837 phy[i].init = ksz8873_init_phy;
838 phy[i].is_phy_connected = ksz8873_is_phy_connected;
839 phy[i].get_link_speed = ksz8873_get_link_speed;
840 phy[i].auto_negotiate = ksz8873_auto_negotiate;
841 break;
Ilya Yanok918588c2011-11-28 06:37:31 +0000842#endif
843#ifdef PHY_LXT972
Ben Warren8cc13c12009-04-27 23:19:10 -0700844 case PHY_LXT972:
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000845 sprintf(phy[i].name, "LXT972 @ 0x%02x",
846 active_phy_addr[i]);
847 phy[i].init = lxt972_init_phy;
848 phy[i].is_phy_connected = lxt972_is_phy_connected;
849 phy[i].get_link_speed = lxt972_get_link_speed;
850 phy[i].auto_negotiate = lxt972_auto_negotiate;
Ben Warren8cc13c12009-04-27 23:19:10 -0700851 break;
Ilya Yanok918588c2011-11-28 06:37:31 +0000852#endif
853#ifdef PHY_DP83848
Ben Warren8cc13c12009-04-27 23:19:10 -0700854 case PHY_DP83848:
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000855 sprintf(phy[i].name, "DP83848 @ 0x%02x",
856 active_phy_addr[i]);
857 phy[i].init = dp83848_init_phy;
858 phy[i].is_phy_connected = dp83848_is_phy_connected;
859 phy[i].get_link_speed = dp83848_get_link_speed;
860 phy[i].auto_negotiate = dp83848_auto_negotiate;
Ben Warren8cc13c12009-04-27 23:19:10 -0700861 break;
Ilya Yanok918588c2011-11-28 06:37:31 +0000862#endif
863#ifdef PHY_ET1011C
Sandeep Paulraj840f8922010-12-28 15:43:16 -0500864 case PHY_ET1011C:
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000865 sprintf(phy[i].name, "ET1011C @ 0x%02x",
866 active_phy_addr[i]);
867 phy[i].init = gen_init_phy;
868 phy[i].is_phy_connected = gen_is_phy_connected;
869 phy[i].get_link_speed = et1011c_get_link_speed;
870 phy[i].auto_negotiate = gen_auto_negotiate;
Sandeep Paulraj840f8922010-12-28 15:43:16 -0500871 break;
Ilya Yanok918588c2011-11-28 06:37:31 +0000872#endif
Ben Warren8cc13c12009-04-27 23:19:10 -0700873 default:
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000874 sprintf(phy[i].name, "GENERIC @ 0x%02x",
875 active_phy_addr[i]);
876 phy[i].init = gen_init_phy;
877 phy[i].is_phy_connected = gen_is_phy_connected;
878 phy[i].get_link_speed = gen_get_link_speed;
879 phy[i].auto_negotiate = gen_auto_negotiate;
880 }
881
Ilya Yanoke0297a52011-11-01 13:15:55 +0000882 debug("Ethernet PHY: %s\n", phy[i].name);
Manjunath Hadli062fe7d2011-10-13 03:40:54 +0000883
884 miiphy_register(phy[i].name, davinci_mii_phy_read,
885 davinci_mii_phy_write);
Ben Warren8cc13c12009-04-27 23:19:10 -0700886 }
Rajashekhara, Sudhakarb78375a2012-06-07 00:27:44 +0000887
888#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
Bastian Ruppertde575502012-09-13 22:29:03 +0000889 defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
890 !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)
Rajashekhara, Sudhakarb78375a2012-06-07 00:27:44 +0000891 for (i = 0; i < num_phy; i++) {
892 if (phy[i].is_phy_connected(i))
893 phy[i].auto_negotiate(i);
894 }
895#endif
Ben Warren8cc13c12009-04-27 23:19:10 -0700896 return(1);
897}