blob: 94f056275914ca5128fc4d2eabdc28737e1b4484 [file] [log] [blame]
Michal Simekf7e2e0e2007-05-05 18:27:16 +02001/*
2 * (C) Copyright 2007 Michal Simek
3 *
4 * Michal SIMEK <monstr@monstr.eu>
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
Michal Simekf7e2e0e2007-05-05 18:27:16 +02007 */
8
9/* FSL macros */
10#define NGET(val, fslnum) \
11 __asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val));
Michal Simekab874d52007-05-08 14:39:11 +020012
Michal Simekf7e2e0e2007-05-05 18:27:16 +020013#define GET(val, fslnum) \
14 __asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val));
Michal Simekab874d52007-05-08 14:39:11 +020015
16#define NCGET(val, fslnum) \
17 __asm__ __volatile__ ("ncget %0, rfsl" #fslnum :"=r" (val));
18
19#define CGET(val, fslnum) \
20 __asm__ __volatile__ ("cget %0, rfsl" #fslnum :"=r" (val));
21
Michal Simekf7e2e0e2007-05-05 18:27:16 +020022#define NPUT(val, fslnum) \
23 __asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val));
Michal Simekab874d52007-05-08 14:39:11 +020024
Michal Simekf7e2e0e2007-05-05 18:27:16 +020025#define PUT(val, fslnum) \
26 __asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val));
Michal Simek48fbd3a2007-05-07 17:11:09 +020027
Michal Simekab874d52007-05-08 14:39:11 +020028#define NCPUT(val, fslnum) \
29 __asm__ __volatile__ ("ncput %0, rfsl" #fslnum ::"r" (val));
30
31#define CPUT(val, fslnum) \
32 __asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val));
33
Michal Simekf7e2e0e2007-05-05 18:27:16 +020034/* CPU dependent */
Michal Simek1a50f1642007-05-08 14:52:52 +020035/* machine status register */
Michal Simeke69f66c2007-05-08 15:57:43 +020036#define MFS(val, reg) \
37 __asm__ __volatile__ ("mfs %0," #reg :"=r" (val));
Michal Simek48fbd3a2007-05-07 17:11:09 +020038
Michal Simeke69f66c2007-05-08 15:57:43 +020039#define MTS(val, reg) \
40 __asm__ __volatile__ ("mts " #reg ", %0"::"r" (val));
Michal Simek1a50f1642007-05-08 14:52:52 +020041
Michal Simekfb05f6d2007-05-07 23:58:31 +020042/* get return address from interrupt */
Michal Simek48fbd3a2007-05-07 17:11:09 +020043#define R14(val) \
44 __asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));
Michal Simekfb05f6d2007-05-07 23:58:31 +020045
Michal Simek1c424d22015-01-26 14:32:23 +010046/* get return address from interrupt */
47#define R17(val) \
48 __asm__ __volatile__ ("addi %0, r17, 0" : "=r" (val));
49
Michal Simeke69f66c2007-05-08 15:57:43 +020050#define NOP __asm__ __volatile__ ("nop");
51
Michal Simekfb05f6d2007-05-07 23:58:31 +020052/* use machine status registe USE_MSR_REG */
Michal Simekac551e32016-05-24 11:45:11 +020053#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR == 1
Michal Simekfb05f6d2007-05-07 23:58:31 +020054#define MSRSET(val) \
55 __asm__ __volatile__ ("msrset r0," #val );
56
57#define MSRCLR(val) \
58 __asm__ __volatile__ ("msrclr r0," #val );
59
60#else
61#define MSRSET(val) \
62{ \
63 register unsigned tmp; \
64 __asm__ __volatile__ (" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020065 mfs %0, rmsr; \
Michal Simekfb05f6d2007-05-07 23:58:31 +020066 ori %0, %0, "#val"; \
67 mts rmsr, %0; \
68 nop;" \
69 : "=r" (tmp) \
70 : "d" (val) \
71 : "memory"); \
72}
73
74#define MSRCLR(val) \
75{ \
76 register unsigned tmp; \
77 __asm__ __volatile__ (" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020078 mfs %0, rmsr; \
Michal Simekfb05f6d2007-05-07 23:58:31 +020079 andi %0, %0, ~"#val"; \
80 mts rmsr, %0; \
81 nop;" \
82 : "=r" (tmp) \
83 : "d" (val) \
84 : "memory"); \
85}
86#endif