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Matthias Fuchs8ba132c2007-12-28 17:07:24 +01001/*
Matthias Fuchs76b565b2008-10-28 13:36:58 +01002 * (C) Copyright 2007-2008
Matthias Fuchs8ba132c2007-12-28 17:07:24 +01003 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
4 * Based on the sequoia configuration file.
5 *
6 * (C) Copyright 2006-2007
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
9 * (C) Copyright 2006
10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
11 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
12 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020013 * SPDX-License-Identifier: GPL-2.0+
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010014 */
15
16/************************************************************************
17 * PMC440.h - configuration for esd PMC440 boards
18 ***********************************************************************/
19#ifndef __CONFIG_H
20#define __CONFIG_H
21
22/*-----------------------------------------------------------------------
23 * High Level Configuration Options
24 *----------------------------------------------------------------------*/
25#define CONFIG_440EPX 1 /* Specific PPC440EPx */
26#define CONFIG_440 1 /* ... PPC440 family */
27#define CONFIG_4xx 1 /* ... PPC4xx family */
28
Wolfgang Denk2ae18242010-10-06 09:05:45 +020029#ifndef CONFIG_SYS_TEXT_BASE
30#define CONFIG_SYS_TEXT_BASE 0xFFF90000
31#endif
32
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010033#define CONFIG_SYS_CLK_FREQ 33333400
34
Matthias Fuchsff41ffc2008-01-11 14:55:16 +010035#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010036#define CONFIG_4xx_DCACHE /* enable dcache */
Matthias Fuchsff41ffc2008-01-11 14:55:16 +010037#endif
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010038
39#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Matthias Fuchs76b565b2008-10-28 13:36:58 +010040#define CONFIG_MISC_INIT_F 1
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010041#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
42#define CONFIG_BOARD_TYPES 1 /* support board types */
43/*-----------------------------------------------------------------------
44 * Base addresses -- Note these are effective addresses where the
45 * actual resources get mapped (not physical addresses)
46 *----------------------------------------------------------------------*/
Wolfgang Denk14d0a022010-10-07 21:51:12 +020047#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 256 kB for malloc() */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010049
50#define CONFIG_PRAM 0 /* use pram variable to overwrite */
51
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
53#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
54#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
Wolfgang Denk14d0a022010-10-07 21:51:12 +020055#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
57#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
58#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
59#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
60#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
61#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
62#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
63#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
64#define CONFIG_SYS_PCI_MEMSIZE 0x80000000 /* 2GB! */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010065
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_USB2D0_BASE 0xe0000100
67#define CONFIG_SYS_USB_DEVICE 0xe0000000
68#define CONFIG_SYS_USB_HOST 0xe0000400
69#define CONFIG_SYS_FPGA_BASE0 0xef000000 /* 32 bit */
70#define CONFIG_SYS_FPGA_BASE1 0xef100000 /* 16 bit */
Matthias Fuchs76b565b2008-10-28 13:36:58 +010071#define CONFIG_SYS_RESET_BASE 0xef200000
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010072
73/*-----------------------------------------------------------------------
74 * Initial RAM & stack pointer
75 *----------------------------------------------------------------------*/
76/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
Wolfgang Denk553f0982010-10-26 13:32:32 +020078#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020079#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Michael Zaidman800eb092010-09-20 08:51:53 +020080#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010081
82/*-----------------------------------------------------------------------
83 * Serial Port
84 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020085#define CONFIG_CONS_INDEX 1 /* Use UART0 */
86#define CONFIG_SYS_NS16550
87#define CONFIG_SYS_NS16550_SERIAL
88#define CONFIG_SYS_NS16550_REG_SIZE 1
89#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#undef CONFIG_SYS_EXT_SERIAL_CLOCK
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010091#define CONFIG_BAUDRATE 115200
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_BAUDRATE_TABLE \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010094 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
95
96/*-----------------------------------------------------------------------
97 * Environment
98 *----------------------------------------------------------------------*/
99#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200100#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100101#else
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200102#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200103#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100104#endif
105
106/*-----------------------------------------------------------------------
107 * RTC
108 *----------------------------------------------------------------------*/
109#define CONFIG_RTC_RX8025
110
111/*-----------------------------------------------------------------------
112 * FLASH related
113 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200115#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
120#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
123#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
126#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
129#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100130
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200131#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200132#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100134#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100135
136/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200137#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
138#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100139#endif
140
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200141#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200142#define CONFIG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */
143#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100144#endif
145
146/*
147 * IPL (Initial Program Loader, integrated inside CPU)
148 * Will load first 4k from NAND (SPL) into cache and execute it from there.
149 *
150 * SPL (Secondary Program Loader)
151 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
152 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
153 * controller and the NAND controller so that the special U-Boot image can be
154 * loaded from NAND to SDRAM.
155 *
156 * NUB (NAND U-Boot)
157 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
158 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
159 *
160 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
161 * set up. While still running from cache, I experienced problems accessing
162 * the NAND controller. sr - 2006-08-25
163 */
Matthias Fuchs7d5d7562008-01-08 11:13:09 +0100164#if defined (CONFIG_NAND_U_BOOT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
166#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
167#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
168#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
169#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
170#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100171
172/*
173 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
176#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100177
178/*
179 * Now the NAND chip has to be defined (no autodetection used!)
180 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
182#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
183#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
184#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
185#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_NAND_ECCSIZE 256
188#define CONFIG_SYS_NAND_ECCBYTES 3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_NAND_OOBSIZE 16
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
Matthias Fuchs7d5d7562008-01-08 11:13:09 +0100191#endif
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100192
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200193#ifdef CONFIG_ENV_IS_IN_NAND
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100194/*
195 * For NAND booting the environment is embedded in the U-Boot image. Please take
196 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
197 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
199#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200200#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100201#endif
202
203/*-----------------------------------------------------------------------
204 * DDR SDRAM
205 *----------------------------------------------------------------------*/
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100206#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
207#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
208#endif
Jean-Christophe PLAGNIOL-VILLARD3aed3aa2008-12-14 10:29:39 +0100209#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
210 /* 440EPx errata CHIP 11 */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100211
212/*-----------------------------------------------------------------------
213 * I2C
214 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000215#define CONFIG_SYS_I2C
216#define CONFIG_SYS_I2C_PPC4XX
217#define CONFIG_SYS_I2C_PPC4XX_CH0
218#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
219#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
220#define CONFIG_SYS_I2C_PPC4XX_CH1
221#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000
222#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_I2C_MULTI_EEPROMS
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
227#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
228#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
229#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
230#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_EEPROM_WREN 1
233#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100234
235/*
236 * standard dtt sensor configuration - bottom bit will determine local or
237 * remote sensor of the TMP401
238 */
239#define CONFIG_DTT_SENSORS { 0, 1 }
240
241/*
242 * The PMC440 uses a TI TMP401 temperature sensor. This part
243 * is basically compatible to the ADM1021 that is supported
244 * by U-Boot.
245 *
246 * - i2c addr 0x4c
247 * - conversion rate 0x02 = 0.25 conversions/second
248 * - ALERT ouput disabled
249 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
250 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
251 */
252#define CONFIG_DTT_ADM1021
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100254
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100255#define CONFIG_PREBOOT "echo Add \\\"run fpga\\\" and " \
256 "\\\"painit\\\" to preboot command"
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100257
258#undef CONFIG_BOOTARGS
259
260/* Setup some board specific values for the default environment variables */
261#define CONFIG_HOSTNAME pmc440
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100262#define CONFIG_SYS_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0"
263#define CONFIG_SYS_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100264
265#define CONFIG_EXTRA_ENV_SETTINGS \
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100266 CONFIG_SYS_BOOTFILE \
267 CONFIG_SYS_ROOTPATH \
268 "fdt_file=/tftpboot/pmc440/pmc440.dtb\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100269 "netdev=eth0\0" \
Matthias Fuchsff41ffc2008-01-11 14:55:16 +0100270 "ethrotate=no\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100271 "nfsargs=setenv bootargs root=/dev/nfs rw " \
272 "nfsroot=${serverip}:${rootpath}\0" \
273 "ramargs=setenv bootargs root=/dev/ram rw\0" \
274 "addip=setenv bootargs ${bootargs} " \
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100275 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
276 ":${hostname}:${netdev}:off panic=1\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100277 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100278 "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \
279 "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100280 "nand_boot_fdt=run nandargs addip addtty addmisc;" \
281 "bootm ${kernel_addr} - ${fdt_addr}\0" \
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100282 "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};" \
283 "tftp ${fdt_addr_r} ${fdt_file};" \
284 "run nfsargs addip addtty addmisc;" \
285 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
286 "kernel_addr=ffc00000\0" \
287 "kernel_addr_r=200000\0" \
288 "fpga_addr=fff00000\0" \
289 "fdt_addr=fff80000\0" \
290 "fdt_addr_r=800000\0" \
291 "fpga=fpga loadb 0 ${fpga_addr}\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100292 "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \
Matthias Fuchs5baefbb2010-07-26 17:17:53 +0200293 "update=protect off fff90000 ffffffff;era fff90000 ffffffff;" \
294 "cp.b 200000 fff90000 70000\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100295 ""
296
297#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
298
299#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100301
Ben Warren96e21f82008-10-27 23:50:15 -0700302#define CONFIG_PPC4xx_EMAC
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100303#define CONFIG_IBM_EMAC4_V4 1
304#define CONFIG_MII 1 /* MII PHY management */
305#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
306
307#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
308
309#define CONFIG_HAS_ETH0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100311
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100312#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
313#define CONFIG_PHY1_ADDR 1
314#define CONFIG_RESET_PHY_R 1
315
316/* USB */
317#define CONFIG_USB_OHCI_NEW
318#define CONFIG_USB_STORAGE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_OHCI_BE_CONTROLLER
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
322#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
323#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
324#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
325#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100326
327/* Comment this out to enable USB 1.1 device */
328#define USB_2_0_DEVICE
329
330/* Partitions */
331#define CONFIG_MAC_PARTITION
332#define CONFIG_DOS_PARTITION
333#define CONFIG_ISO_PARTITION
334
335#include <config_cmd_default.h>
336
337#define CONFIG_CMD_BSP
338#define CONFIG_CMD_DATE
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100339#define CONFIG_CMD_DHCP
340#define CONFIG_CMD_DTT
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100341#define CONFIG_CMD_EEPROM
342#define CONFIG_CMD_ELF
343#define CONFIG_CMD_FAT
344#define CONFIG_CMD_I2C
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100345#define CONFIG_CMD_MII
346#define CONFIG_CMD_NAND
347#define CONFIG_CMD_NET
348#define CONFIG_CMD_NFS
349#define CONFIG_CMD_PCI
350#define CONFIG_CMD_PING
351#define CONFIG_CMD_USB
352#define CONFIG_CMD_REGINFO
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100353
354/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
356 CONFIG_SYS_POST_CPU | \
357 CONFIG_SYS_POST_UART | \
358 CONFIG_SYS_POST_I2C | \
359 CONFIG_SYS_POST_CACHE | \
360 CONFIG_SYS_POST_FPU | \
361 CONFIG_SYS_POST_ETHER | \
362 CONFIG_SYS_POST_SPR)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100363
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100364#define CONFIG_LOGBUFFER
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100365#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100366
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100368
369#define CONFIG_SUPPORT_VFAT
370
371/*-----------------------------------------------------------------------
372 * Miscellaneous configurable options
373 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_LONGHELP /* undef to save memory */
Stefan Roesebe88b162008-01-17 07:50:17 +0100375#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100377#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100379#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
381#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
382#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100383
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
385#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100386
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
388#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100389
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100390#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
391#define CONFIG_LOOPW 1 /* enable loopw command */
392#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
393#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
394#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
395
396#define CONFIG_AUTOBOOT_KEYED 1
Wolfgang Denkc37207d2008-07-16 16:38:59 +0200397#define CONFIG_AUTOBOOT_PROMPT \
398 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100399#undef CONFIG_AUTOBOOT_DELAY_STR
400#define CONFIG_AUTOBOOT_STOP_STR " "
401
402/*-----------------------------------------------------------------------
403 * PCI stuff
404 *----------------------------------------------------------------------*/
405/* General PCI */
406#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000407#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100408#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100410#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100412
413/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_PCI_TARGET_INIT
415#define CONFIG_SYS_PCI_MASTER_INIT
Stefan Roesea760b022009-11-12 16:41:09 +0100416#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100417
Matthias Fuchs2fe6b7f2011-10-13 15:12:22 +0200418#define CONFIG_PCI_BOOTDELAY 0
419
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100420/* PCI identification */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
422#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */
423#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
Stefan Roese10954932009-11-12 12:00:49 +0100424/* for weak __pci_target_init() */
425#define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
427#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100428
429/*
430 * For booting Linux, the board info and command line data
431 * have to be in the first 8 MB of memory, since this is
432 * the maximum mapped by the Linux kernel during initialization.
433 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100435
436/*-----------------------------------------------------------------------
437 * FPGA stuff
438 *----------------------------------------------------------------------*/
439#define CONFIG_FPGA
440#define CONFIG_FPGA_XILINX
441#define CONFIG_FPGA_SPARTAN2
442#define CONFIG_FPGA_SPARTAN3
443
444#define CONFIG_FPGA_COUNT 2
445/*-----------------------------------------------------------------------
446 * External Bus Controller (EBC) Setup
447 *----------------------------------------------------------------------*/
448
449/*
450 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
451 */
452#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_NAND_CS 2 /* NAND chip connected to CSx */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100454
455/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_EBC_PB0AP 0x03017200
457#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100458
459/* Memory Bank 2 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_EBC_PB2AP 0x018003c0
461#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100462#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100464/* Memory Bank 2 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_EBC_PB2AP 0x03017200
466#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH_BASE | 0xda000)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100467
468/* Memory Bank 0 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469#define CONFIG_SYS_EBC_PB0AP 0x018003c0
470#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100471#endif
472
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100473/* Memory Bank 1 (RESET) initialization */
Wolfgang Denk455ae7e2008-12-16 01:02:17 +0100474#define CONFIG_SYS_EBC_PB1AP 0x7f817200 /* 0x03017200 */
Jean-Christophe PLAGNIOL-VILLARD3aed3aa2008-12-14 10:29:39 +0100475#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000)
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100476
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100477/* Memory Bank 4 (FPGA / 32Bit) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
479#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_FPGA_BASE0 | 0x1c000) /* BS=1M,BU=R/W,BW=32bit */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100480
481/* Memory Bank 5 (FPGA / 16Bit) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_EBC_PB5AP 0x03840f40 /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
483#define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_FPGA_BASE1 | 0x1a000) /* BS=1M,BU=R/W,BW=16bit */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100484
485/*-----------------------------------------------------------------------
486 * NAND FLASH
487 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488#define CONFIG_SYS_MAX_NAND_DEVICE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
490#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
491#define CONFIG_SYS_NAND_QUIET_TEST 1
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100492
Stefan Roesebe88b162008-01-17 07:50:17 +0100493#if defined(CONFIG_CMD_KGDB)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100494#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
495#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
496#endif
497
498/* pass open firmware flat tree */
499#define CONFIG_OF_LIBFDT 1
500#define CONFIG_OF_BOARD_SETUP 1
501
Matthias Fuchs76b565b2008-10-28 13:36:58 +0100502#define CONFIG_API 1
503
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100504#endif /* __CONFIG_H */