blob: 33e04963e6782caa8e7aaef5d9491af379f57ff7 [file] [log] [blame]
Tirumala Marrid0e66652010-09-28 14:15:21 -07001/*
2 * bluestone.h - configuration for Bluestone (APM821XX)
3 *
4 * Copyright (c) 2010, Applied Micro Circuits Corporation
5 * Author: Tirumala R Marri <tmarri@apm.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Tirumala Marrid0e66652010-09-28 14:15:21 -07008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * High Level Configuration Options
15 */
16#define CONFIG_APM821XX 1 /* APM821XX series */
17#define CONFIG_HOSTNAME bluestone
18
19#define CONFIG_4xx 1 /* ... PPC4xx family */
20#define CONFIG_440 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021
22#ifndef CONFIG_SYS_TEXT_BASE
23#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
24#endif
25
Tirumala Marrid0e66652010-09-28 14:15:21 -070026/*
27 * Include common defines/options for all AMCC eval boards
28 */
29#include "amcc-common.h"
30#define CONFIG_SYS_CLK_FREQ 50000000
31
32#define CONFIG_BOARD_TYPES 1 /* support board types */
33#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
34#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
35
36/*
37 * Base addresses -- Note these are effective addresses where the
38 * actual resources get mapped (not physical addresses)
39 */
40/* EBC stuff */
41/* later mapped to this addr */
42#define CONFIG_SYS_FLASH_BASE 0xFFF00000
43#define CONFIG_SYS_FLASH_SIZE (4 << 20) /* 1MB usable */
44
45/* EBC Boot Space: 0xFF000000 */
46#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000
47#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */
48#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
49#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/
50
51#define CONFIG_SYS_SRAM_SIZE (256 << 10)
52/*
53 * Initial RAM & stack pointer (placed in OCM)
54 */
55#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
Wolfgang Denk553f0982010-10-26 13:32:32 +020056#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Tirumala Marrid0e66652010-09-28 14:15:21 -070057#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020058 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Tirumala Marrid0e66652010-09-28 14:15:21 -070059#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
60
61/*
62 * Environment
63 */
64/*
65 * Define here the location of the environment variables (FLASH).
66 */
67#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
68
69/*
70 * FLASH related
71 */
72#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
73#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
74#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
75#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
76/* max number of memory banks */
77#define CONFIG_SYS_MAX_FLASH_BANKS 1
78/* max number of sectors on one chip */
79#define CONFIG_SYS_MAX_FLASH_SECT 80
80/* Timeout for Flash Erase (in ms) */
81#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
82/* Timeout for Flash Write (in ms) */
83#define CONFIG_SYS_FLASH_WRITE_TOUT 500
84/* use buffered writes (20x faster) */
85#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
86/* print 'E' for empty sector on flinfo */
87#define CONFIG_SYS_FLASH_EMPTY_INFO
88#ifdef CONFIG_ENV_IS_IN_FLASH
89#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
90#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
91#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
92/* Address and size of Redundant Environment Sector */
93#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
94#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
95#endif /* CONFIG_ENV_IS_IN_FLASH */
96
97/* SDRAM */
98#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
99#define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */
100#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
101#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
102#define CONFIG_DDR_ECC 1 /* with ECC support */
103
104/*
105 * Serial Port
106 */
107#define CONFIG_CONS_INDEX 1 /* Use UART0 */
108
109/*
110 * I2C
111 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000112#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Tirumala Marrid0e66652010-09-28 14:15:21 -0700113#define CONFIG_SYS_I2C_MULTI_EEPROMS
114#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
115#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
116#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
117#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */
118
119/* I2C bootstrap EEPROM */
120#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
121#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
122#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
123
124/*
125 * Ethernet
126 */
127#define CONFIG_IBM_EMAC4_V4 1
128#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII
129#define CONFIG_HAS_ETH0
130/* PHY address, See schematics */
131#define CONFIG_PHY_ADDR 0x1f
132/* reset phy upon startup */
133#define CONFIG_PHY_RESET 1
134/* Include GbE speed/duplex detection */
135#define CONFIG_PHY_GIGE 1
136#define CONFIG_PHY_DYNAMIC_ANEG 1
137
138/*
139 * External Bus Controller (EBC) Setup
140 **/
141#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \
142 EBC_CFG_PTD_ENABLE | \
143 EBC_CFG_RTC_2048PERCLK | \
144 EBC_CFG_ATC_HI | \
145 EBC_CFG_DTC_HI | \
146 EBC_CFG_CTC_HI | \
147 EBC_CFG_OEO_PREVIOUS)
148/* NOR Flash */
149#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
150 EBC_BXAP_TWT_ENCODE(64) | \
151 EBC_BXAP_BCE_DISABLE | \
152 EBC_BXAP_BCT_2TRANS | \
153 EBC_BXAP_CSN_ENCODE(1) | \
154 EBC_BXAP_OEN_ENCODE(2) | \
155 EBC_BXAP_WBN_ENCODE(2) | \
156 EBC_BXAP_WBF_ENCODE(2) | \
157 EBC_BXAP_TH_ENCODE(7) | \
158 EBC_BXAP_SOR_DELAYED | \
159 EBC_BXAP_BEM_WRITEONLY | \
160 EBC_BXAP_PEN_DISABLED)
161/* Peripheral Bank Configuration Register - EBC_BxCR */
162#define CONFIG_SYS_EBC_PB0CR \
163 (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
164 EBC_BXCR_BS_1MB | \
165 EBC_BXCR_BU_RW | \
166 EBC_BXCR_BW_8BIT)
167
168
169#endif /* __CONFIG_H */